DIGITAL DESIGN TECHNOLOGY & TECHNIQUES

Transcription

1 DIGITAL DESIGN TECHNOLOGY & TECHNIQUES CAD for ASIC Design 1

2 INTEGRATED CIRCUITS (IC) An integrated circuit (IC) consists complex electronic circuitries and their interconnections. William Shockley et al. of Bell Laboratories invented transistor in Most current integrated circuits are built with MOSFET (metaloxide semiconductor field effect transistor) transistors. ICs commercially available since early 1960s. Phenomenal advancement in IC design and fabrication technologies. CAD for ASIC Design 2

3 More and more transistors are packed in a chip SSI, MSI, LSI, and VLSI. Currently millions of transistors in a single chip. E.g., Intel Pentium IV processor has 40 million transistors using 0.13 µm technology. Integration Number Scale of Transistors Examples SSI < 10 Logic gates MSI 10 1,000 Adders, counters LSI 1,000 10,000 Multipliers VLSI > 10,000 Microprocessors CAD for ASIC Design 3

4 Moore's Law Maximum number of transistors on a chip approximately doubles every eighteen months. This prediction has been accurate for the last four decades. CAD for ASIC Design 4

5 DIGITAL IC IMPLEMENTATION ALTERNATIVES Various implementation of digital logic designs Traditional off the shelf IC chips, e.g., SSI and MSI TTL, perform a fixed operation defined by the device manufacturer. Application specific Integrated Circuits (ASICs) are customized ICs whose internal functional operation is user defined. CPLD or FPGA requires user hardware programming to perform the desired operation. The circuit level design of a VLSI or ASIC chip involves circuit components design, placement, and interconnect routing. CAD for ASIC Design 5

6 Digital Implementation Alternatives Standard Components VLSI Integrated Circuits SoC (System-on-Chip) Applications fixed Applications by Programming Reconfigurable ASIC Semicustom VLSI Structured ASIC Full-custom VLSI Logic Gates & Logic Modules Software Programming Hardware Programming Prefabricated Reconfigurable Microchip Masked Gate Array (MGA) Standard Cell-based Design CMOS TTL ECL Microprocessor & EPROM PLA PLD ROM FPGA CPLD Channeled GA Sea-of-gates GA master slice CAD for ASIC Design 6

7 Full custom VLSI uses circuit elements, e.g., transistors and connections as the primitive components. Offers a designer flexibility to optimize circuit characteristics, placement, and their interconnects, as long as certain design rules are satisfied. Very time consuming for complex ICs and requires a full knowledge of the operation of the components at the circuit level. Semicustom design uses a library of circuit level cells (standard cells) specified by their functions and characteristics. The use of standard cells at the logic level simplifies the design process, but reduces design flexibility. CAD for ASIC Design 7

8 Another semicustom style is the gate array design. Basic components (usually basic gates) are placed on a regular structure within a chip, and the design consists of determining the connections between the gates. Horizontal routing channel (y = abc + a'c + c'd) a y a' abd b b' a'c c c' c'd d Vertical routing channel (z = a + b) z CAD for ASIC Design 8

9 A combination of full custom and semicustom design is best, where the critical portions of the system are designed using full custom. IC TYPE Mask layers Logic cells Fabrication customized customized lead time Full custom VLSI All Some > 2 months Standard Cell based All None ~2 months ASIC Masked Gate Arrays Some None ~1 to 2 weeks FPGA / CPLD None None CAD for ASIC Design 9

10 DIGITAL DESIGN ABSTRACTION Today s circuits are more complex. Time to market is one of the crucial factors. New techniques must be used when we move from a small scale to large scale designs Digital designers use two techniques Design abstraction Hierarchical modular design Need electronic design automation (EDA) or computer aided design (CAD) tools. CAD for ASIC Design 10

11 Design abstraction At each design level, the internal details of a complex module may be abstracted away and replaced by a black box view or model. This model contains virtually all the information needed to deal with the block at the next (lower) level of the design hierarchy. For all purposes, the model can be considered a black box with known characteristics. As there is no need for the system designer to look inside this box, design complexity is substantially reduced. Design abstraction is crucial in hardware system design. Hardware designers use these multiple levels of design abstraction to meet performance goals for very large designs and reduce design lead times. CAD for ASIC Design 11

12 CAD for ASIC Design 12

13 Hierarchical modular design technique The solution to working in any complex environment is modularization (divide and conquer) The complexity of design is broken down (divided) into a hierarchy of modules general (top) to specific (bottom). Benefits to Focus on a single module at a time Create customized low level modules for design reuse. CAD for ASIC Design 13

14 The top down approach decomposes the system into smaller subsystems up to a level which the subsystems can be realized. The bottom up approach connects available modules to form bigger, more complex subsystems. Usually combined top down decomposition and bottom up composition (reuse of primitive modules). CAD for ASIC Design 14

15 Top Level A B C D Bottom Level A B C D (a) Top down approach (b) Bottom up approach. CAD for ASIC Design 15

16 ELECTRONIC DESIGN PROCESS System Specification Circuit Design Architectural Design Physical Design Functional Design Fabrication Logic Design Packaging CAD for ASIC Design 16

17 System Specification Architectural Modelling HW/SW Partition Hardware Spec Hardware Modelling Software Spec Software Modelling Hardware Implementation Software Implementation Integrated Circuits ASIC FPGA PLD Standard Parts Boards and Systems Software CAD for ASIC Design 17

18 COMPUTER AIDED DESIGN (CAD) A.k.a Electronic Design Automation (EDA) systems. Makes design process efficient, timely, and economical. CAD tools are intended to support all phases of a digital design: Description (specification), Design (synthesis), including various optimizations to reduce cost and improve performance, Verification (by simulation or formal approach) with respect to its specification. These three phases typically require several passes to obtain a suitable implementation. CAD for ASIC Design 18

19 HDL (Hardware Description Language) It is replacing schematic capture Today, VHDL and Verilog are the two widely used languages These two description approaches can coexist. CAD for ASIC Design 19

20 Schematic Design vs. HDL Design The traditional way is by (schematic capture) logic diagram of the system (modules and their interconnects). An alternative is using hardware description language (HDL), e.g., VHDL and Verilog are the two languages widely used to model and design digital hardware. HDLs offer/allow Reduction in development time and allows more exploration of design alternatives. Description in higher levels of abstraction. A mean to standardize or method of specifying a design. Representation of sequential logic and manipulation of data type. CAD for ASIC Design 20

21 CAD for ASIC Design 21

22 CAD Methodology with HDL Design entry in HDL format (e.g. UTM VHDLmg, Altera Quartus II ). HDL behavioural simulation (e.g. Aldec Active VHDL). Synthesis (e.g., Altera Quartus II, Synopsys FPGA Express), converting the code to a logic netlist file. Functional simulation to verify for design correctness (e.g. Altera Quartus II). Implementation converting netlist file to a physical design to the target implementation technology. Timing Simulation the physical layout is verified with timing information. CAD for ASIC Design 22

23 CAD for ASIC Design 23

24 Logic Synthesis RTL Description Translation Unoptimized Intermediate Representation Logic Optimization Design Constraints (Timing, Area, Power) Technology Mapping and Optimization Technology Library (library of available gates, and leaf-level cells) Gate-level Netlist (Optimized Gate-Level Representation) CAD for ASIC Design 24

25 Altera Quartus II CAD Tool A sophisticated CAD system. Comprehensively an integrated design environment (IDE) for the design of digital systems. Includes solutions for all phases of FPGA based designs. Modelsim Cost effective HDL simulation solution Intuitive GUI for efficient interactive debug Integrated project management simplifies managing project data CAD for ASIC Design 25

26 EVOLVING TRENDS Increasing Design Density and Complexity Electronic System Level - ESL (systemc/ systemverilog) Behavioural or Algorithmic Synthesis Gate Count 1 M 500K Register-Transfer Level - RTL (VHDL/ Verilog) 100K Simple HDL, PLA-based (eg ABEL) Schematicbased 10K 1K 1970's 1980's 1990's 2000 CAD for ASIC Design 26

27 Further Reading 1.Jan M.Rabaey, A.Chandrakasan & B.Nikolic, Digital Integrated Circuits A Design Perspective, 2 nd edition, Prentice Hall, 2003, Chapter Neil W.E. Weste & David Harris, CMOS VLSI Design A Circuits and Systems Perspective, 3 rd edition, Pearson Addison Wesley, 2005, Chapter 1. CAD for ASIC Design 27