Lab #12: ArithmeticLogic Unit
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1 Lab #12: ArithmeticLogic Unit Zack Mattis Lab: 3/27/17 Report: 4/8/17 Partner: Brendan Schuster
2 Purpose In this lab, a fully functioning 4-bit Arithmetic Logic Unit (ALU) was designed and fully implemented onto a protoboard that is capable of performing a number of operations. ALUs can perform both arithmetic operations such as addition and subtraction as well as logical operations including ANDs and ORs. ALUs are utilized by CPUs to provide the data calculations of the specified functions. This implementation utilizes a 4 x 4 register previously created and a 4-bit latch to provide the inputs to the ALU. Additionally, the output of the ALU is fed back into the 4 x 4 register through the use of a 4 x 2:1 MUX to store the calculated hexadecimal values in the registers. Two 7-segment displays are included to observe the output of the ALU as well as the output value of the 4 x 4 register. The design can be seen in Figure 1 below. The operation of the design was verified using the LogicPort Logic Analyzer to observe the signals of the circuit. The design was implemented using one 4x4 register (74LS670), one ALU (74LS181), two counters (74LS193), one 4 x 2:1 MUX (74LS157), two D Flip-Flops (74LS74), two 7-segment display drivers/decoders (74LS247), two 7segment displays, three 8-bit DIP SPST switches, one SPST switch, 18 resistors, and 4 LEDs. Figure 1 4 bit ALU
3 Procedure The design for the 4-bit ALU was created using the Altera Quartus 9.1 software and can be seen in Figure 2 (see attached). The design uses a 4x4 register combined with 2 counters for the read/write, and 4-bit latch, a 4-bit ALU, and two decoders for the seven segment displays that convert the hexadecimal input/output into a visual 7 segment output display. Additionally, a 4 x 2:1 MUX supplies the input of the 4 x 4 register from either user-selected input data or the output of the ALU to store the calculated data in the registers. This design was then tested using the Quartus simulation tool that allows for user selected data for each of the inputs. By manipulating the data in the 4 x 4 register, and sending it to the latch, the user can select the two data operands of the ALU. By changing the select lines of the ALU (S[3] S[0]), the mode (M), and the carry in (Cin), the user can select which ALU operation he/she wishes to perform. Four different operations (addition, subtraction, AND, OR) were tested using Quartus and their respective waveforms can be seen in Figures 3-6 (see attached). Finally, 4 hexadecimal digits were added together using the 4 registers of the 4x4 register. The values 1, 2, 2, and 3 were added to get the final output of 8, which can be seen in Figure 7 (see attached). The verified design was then implemented onto the protoboard using the previously mentioned IC chips. DIP switches were used to provide the control signals as well as the 4-bit data signals. A SPST switch was used to provide the clocking signal for the latch to store the 4-bit hex value from the register. The ALU inputs were from the 4-bit latch and from the 4x4 register. Through the use of the 4 x 2:1 MUX, the output of the ALU was wired back into the register so that it could be stored. Both the register value and the output from the ALU were wired to seven-segment display decoders and then seven segment displays. These displays allowed for easy viewing of the hexadecimal value that was being produced. Additionally, LEDs were added to the output of each counter to view which register was active. This protoboard implementation was then analyzed using the LogicPort Logic Analyzer. This device converts the analog signal of the circuit into a digital form of 0s and 1s. This tool enables effective observation of the circuit s inputs and outputs. In our testing, we connected the device to 19 data inputs. Each of the four operations simulated in Quartus were then tested on the Logic Analyzer. The output waveforms of addition, subtraction, AND, and OR can be seen Figures 8-11 (see attached), respectively.
4 Results The use of a 4x4 register wired in combination with a 4-bit latch allows for effective input signals for the operands of the ALU. Utilization of a 4 x 2:1 MUX was a necessary implementation for the ALU in order to store the calculated data output in the register. Additionally, the use of seven segment displays allowed the user to easily see the hexadecimal value stored within the register as well as the hexadecimal output of the ALU. The use of LEDs for the output of the counter also allow the user to see which register has been selected. Our completed circuit design can be seen in Figure 12 below. Using this completed ALU protoboard implementation, we were able to implement a 4-bit multiplication operation using the pseudocode shown in Figure 13 (see attached). This pseudocode is used to find the first partial product (a3b0 a2b0 a1b0 a0b0) of the multiplication of operands A (a3a2a1a0) & B (b3b2b1b0). This multiplication was then analyzed using the Logic Analyzer to verify its operation. The multiplication waveform can be seen in Figure 14 (see attached). Figure 12 ALU Protoboard Implementation
5 Conclusion The design implementation of the 4-bit ALU from Figure 2 proved to be a successful design. This protoboard circuit works as a fully-functional ALU capable of performing all of the operations required from a CPU. The LogicPort Logic Analyzer output waveforms from Figures 8-11 shows the user correctly utilizing the ALU to perform both arithmetic and logical operations (addition, subtraction, AND, OR). Without a multiplication operation integrated within the ALU, utilization of the pseudocode shown in Figure 13 using AND, OR, shift, & addition operations can be used to calculate partial products to store within registers to calculate a final 4-bit hexadecimal product. The ALU design and implementation was a practical application to understanding how the CPUs of computers utilize ALUs to provide the operations necessary to function properly. References 1. ECE 0501 Digital Systems Laboratory Custom Course Materials. Laboratory Notebook. University of Pittsburgh.
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