INTEL Architectures GOPALAKRISHNAN IYER FALL 2009 ELEC : Computer Architecture and Design

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Ann Wilkins
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1 INTEL Architectures GOPALAKRISHNAN IYER FALL 2009 ELEC : Computer Architecture and Design

2 Silicon Technology Moore s law Moore's Law describes a long-term trend in the history of computing hardware, in which the number of transistors that can be placed inexpensively on an integrated circuit has doubled approximately every two years.

3 Intel processors: in Chronological order

4 Intel processors: in Chronological order

5 Intel processors: in Chronological order

6 8086: The building block The x86 architecture is a variable instruction length, CISC design with emphasis on backward compatibility More than 100 instructions in the instruction set architecture The largest size for integer arithmetic and addressing offsets is 16,32 or 64 bits depending on architecture generation. 1 st x86 based processor in Mhz clock rates : MIPS

7 Functional block diagram of 8086 architecture

8 Basics of x86 architecture bit registers, 16-bit external data bus, 20 bit addressing, giving 1 MB address space. Register structure: Accumulator, Base, Counter, Data (General Purpose registers) Code, Stack, Data, Extra (Segment registers) Source Index, Destination Index, Instruction Pointer (Pointer registers) Stack Pointer, Base Pointer (Pointer registers) Flag register: Consists of status flag bits which vary with architecture generation. Common ones include Carry, Parity, Auxiliary, Zero, Sign, Interrupt. Memory is segmented into Code, Stack, Data and Extra with address calculation using the base addresses and offset for each segment.

9 Basics contd Multi-byte values in Little-endian format i.e least significant byte first 7 different addressing modes for register and memory operations Stack used for push and pop operations. Stack operates on LIFO (last in first out) principle Instruction queue to pre-fetch instructions from the memory

10 IA-32 and Intel 64 Intel Architecture(32-bit) : It is generically called x86, x86-32 or i386. It is Intel s commercially most successful processor yet. It is a 32-bit extension, first implemented in the Intel 80386, of the earlier 16-bit Intel 8086, and processors This architecture defines the instruction set for the family of microprocessors installed in the vast majority of personal computers in the world. The success of x86 is due to full backward compatibility and the architecture has also been extended to 64-bits, without breaking compatibility. This extension is called Intel 64 by Intel (referred to generically as x86-64 or x64). The IA-32 instruction set is a CISC architecture, though such classifications have become less meaningful with advances in microprocessor design.

11 IA-32 and Intel 64 Intel 64 is a 64-bit architecture by Intel. Has completely different instruction set and uses a VLIW (very long instruction word) design. IA-64 is the architecture used by the Itanium line of processors. Itanium initially also included hardware-support for IA-32 emulation. The IA-64 features : Sixteen times the number of general purpose registers (128) Sixteen times the number of floating point registers (128) Register rotation mechanism to keep values in registers over function calls

Intel s only RISC processor Intel i960 32bit Intel's i960 (or 80960) was a RISC-based microprocessor design that became popular during the early 1990s as an embedded microcontroller, becoming a

12 Intel s only RISC processor Intel i960 32bit Intel's i960 (or 80960) was a RISC-based microprocessor design that became popular during the early 1990s as an embedded microcontroller, becoming a best-selling CPU in that field. Memory system was 33-bit wide for a 32-bit word. 1 bit was used for protected memory. It had no memory segmentation to allow faster access. Used windowed register concept for procedure calls.

13 Some current Intel architectures Architectures by Intel are the IA-32 and Intel 64 till date Other variations of the x86 architecture are NetBurst Micro-architecture also called or the P7 Hyper pipelined technology i.e a 20-stage pipeline Rapid execution engine: ALU operates at twice the clock frequency of 7.6 GHz if CPU clock is at 3.8 Ghz Execution trace cache : Uses L1 cache to store decoded micro-operations to enable faster execution without fetch and decode by the processor. Problems : Severe heat dissipation due to high clock speeds. Hence architecture abandoned. Intel Micro-architecture also called Nehalem (Intel 64 based) Provides two logical processors per core (hyper-threading) Dedicated power management units

14 References ut+ln_history (Intel developers manual for 32 and 64 bit processors) diagram_enotes.pdf

15 THANK YOU

Real instruction set architectures. Part 2: a representative sample

Real instruction set architectures Part 2: a representative sample Some historical architectures VAX: Digital s line of midsize computers, dominant in academia in the 70s and 80s Characteristics: Variable-length