32-bit Embedded Core Peripheral. Cache Memory. and Bus Interface Unit

Transcription

1 Features 8 KB Memory Size (Optional 2 KB, 4 KB, 16 KB and 32 KB) Four-way Parallel Associative Cache Memory and Four-word Burst External Access on Miss Write-back Algorithm Enhanced External Bus Access ARM740-compatible Configuration and MPU Structure Memory Protection Unit (MPU) with Eight Programmable Areas Description The cache memory and bus interface unit extends the capabilities of the ARM7TDMI processor by adding to it an 8 KB, four-way, parallel associative cache memory, a memory protection unit and an AMBA ASB bus interface unit. The ARM7TDMI processor, together with the cache memory unit, is software- and hardware-compatible with the ARM740T processor. The cache memory unit, which does not require the use of tri-state buses, decodes the ARM7TDMI co-processor interface and extends the instruction set of the original ARM7TDMI. The cache memory unit is designed specifically for ASIC development. Figure 1. Block Diagram R ARM Interface AMBA ASB Interface 32-bit Embedded Core Peripheral Cache Memory and Bus Interface Unit Co-processor Interface ARM7TDMI CPU Control Address Data Cache Memory and Bus Interface Unit ASB Control ASB BA ASB D To System Rev. 1

2 Signal Description Table 1. ARM Interface Name Type Description A<31:0> I ARM7TDMI address bus. Addresses must become valid during phase 2 of the cycle preceding that to which they refer (APE = 1). ABORT O Abort signal for the ARM7TDMI. It signals that the requested access is not allowed. CPA O ARM7TDMI co-processor interface (co-processor absent) CPB O ARM7TDMI co-processor interface (co-processor busy) DO<31:0> O Data bus to ARM7TDMI DI<31:0> I Data bus from ARM7TDMI LOCK I Lock signal from ARM7TDMI. The processor is performing a locked memory access. MAS<1:0> I Memory access size MCLK O Clock signal for the ARM7TDMI ncpi I ARM7TDMI co-processor interface nmreq I Valid memory access nopc I ARM7TDMI co-processor interface (opcode fetch) nreset O Reset signal for the ARM7TDMI nrw I Not read/write access cycle ntrans I Not memory translate. When low, the processor is in user mode, and no co-processor instructions are supported. nwait I Wait cycle for the ARM7TDMI TBIT I ARM7TDMI is executing in Thumb mode. No co-processor instructions are supported. Table 2. AMBA ASB Interface Name Type Description AREQ O ASB bus request AGNT I ASB bus grant BA<31:0> O ASB address bus BCLK I/O ASB clock BDO<31:0> O ASB data bus output BDI<31:0> I ASB data bus input BERROR I Error response. A transfer error is indicated by a selected bus slave. BLAST I Last response. This signal is driven by the selected bus slave to indicate that the current transfer should be the last of a burst request. 2 Cache Memory

3 Cache Memory Table 2. AMBA ASB Interface (Continued) Name Type Description BLOK O Locked transfer. This signal indicates that the current transfer and the next transfer are to be indivisible and no other bus master should be given access to the bus. BnRES I Bus reset signal BPROT<1:0> O Protection control (opcode-data fetch, user-privileged mode) BSIZE<1:0> O Bus size. Indicates the size of the transfer (byte, half-word, word). BTRAN<1:0> O Transfer type. Address-only, non-sequential, sequential. BWAIT I Wait response. The bus slave indicates if the current transfer may complete. BWRITE O Write/read transfer AMBA ASB Interface The ASB bus interface is defined by ARM Ltd. in its AMBA Specification (Rev. 2.0). The cache memory unit IP follows this specification apart from one restriction: No retract or last response cycles are supported. The cache memory unit provides an interface that is uni-directional and fully synchronous with the falling edge of BCLK. The conversion to a full ASB interface with tri-state buses is easy, requiring only a few additional tri-state buffers at the outputs. For a description of the differences between multiplexer bus and tri-state bus implementation, refer to the application note on AMBA interconnection schemes provided by ARM. No test support is provided through the ASB, so the cache must be tested by using conventional scan paths and memory BIST. Configuration Configuration and operation of the cache memory unit is controlled via co-processor 15 (CP15). Co-processor instructions are used to manipulate a number of on-chip registers, which control the configuration of the following: the cache the protection unit a number of other configuration options To ensure backwards compatibility of future CPUs, all reserved or unused bits in registers and co-processor instructions should be programmed to 0. Invalid registers must not be read/written. Note that the areas filled in with in the register diagrams are reserved and should be programmed 0 for future compatibility. 3

4 Internal Coprocessor Instructions On-chip configuration registers may be read using MRC instructions and written using MCR instructions. However, these operations are only allowed in non-user modes, and the undefined instruction trap is taken if access is attempted in user mode. Format of Internal Co-processor Instructions MRC and MCR COND n CRn Rd CRm Bits COND: ARM condition codes Bit 20 n 1 = MRC register read 0 = MCR register write Bits CRn: CP15 Source/Destination Register This field is normally used to determine which configuration register is being accessed. Bits Rd: ARM Register Bits 3..0 CRm: CP15 Operand Register 4 Cache Memory

5 Cache Memory Registers The configuration registers are accessed by CPRT instructions to CP15, with the processor in privileged mode. Only some of the CRn registers, however, are valid: An attempt to access an invalid register results in neither the access nor an undefined instruction trap being obtained and therefore should never be made. An attempt to access any of the registers [8:15] results in the undefined instruction trap. Table 3. System Control Registers Register Register Reads Register Writes 0 ID Register Reserved 1 Control Control 2 Cacheable Cacheable 3 Reserved Reserved 4 Reserved Reserved 5 Protection Protection 6 Memory area definition Memory area definition 7 Reserved Flush unlocked cache banks 8-15 Reserved Reserved Register 0: ID Register Register Name: ID Register Access Type: Read-only Register 0 is a read-only identity register that returns the ID code for this IP. Table 4. Cache Variant ID Code 2 Kb 0xFF1C740x 4 Kb 0xFF2C740x 8 Kb 0xFF3C740x 16 Kb 0xFF4C740x Note: The variable x represents the version number. 5

6 Register 1: Control Register Register Name: Control Register Access Type: Read/write Register 1 contains the control bits. All bits in this register are forced low by reset Bank F Lock S B W C M Bits Bank: Cache Bank Select Register This field controls the cache. See Partially Locked Operation on page 11. Bit 27 F: Load Mode This bit controls the cache. See Partially Locked Operation on page 11. Bits Lock: Lock Cache Lockdown Control Register This field controls the cache. See Partially Locked Operation on page 11. Bit 24 S: Split Instruction Data Mode This bit controls the operating mode of the cache. See Split-instruction Data Operation on page 12. Bit 7 B: Big-/Little-endian 0 = Little-endian operation 1 = Big-endian operation Bit 3 W: Reserved Bit 2 C: Cache Enable/Disable 0 = Cache disabled 1 = Cache enabled Bit 0 M: Protection Unit Enable/Disable 0 = On-chip protection unit disabled 1 = On-chip protection unit enabled 6 Cache Memory

7 Cache Memory Register 2: Cacheable Register Register Name: Cacheable Register Access Type: Read/write Register 2 contains the current values of the cacheable bit. See Protection Unit Registers on page 14 for a description of the operation of the Protection Unit Register 3: Reserved This register is reserved. Register 4: Reserved This register is reserved. Register 5: Protection Register Register Name: Protection Register Access Type: Read/write Register 5 contains the access permissions for the eight areas of memory. The access permission bits are defined in the Protection Register on page

8 Register 6: Memory Area Definition Register Register Name: Memory Area Definition Register Access Type: Read/write Register 6 is actually eight physical registers that are referenced by the CRm field of a CPRT instruction. Each register defines a memory area. A complete description of these registers is given in Area Registers on page Base[31:12] Size[4:0] E When programming the Memory Area Register, the appropriate region is selected using the CRm parameter in the MCR or MRC instruction. Register 7: IDC Flush Register Register Name: IDC Flush Register Access Type: Write-only Register 7 is a write-only register. The data written to this register is discarded and all unlocked banks of the cache are flushed. Registers (8:15): Reserved Accessing any of these registers causes the undefined instruction trap to be taken. 8 Cache Memory

9 Cache Memory Cache Memory Unit Read-lock-write Reset The cache memory unit incorporates either an 8K or 4K general-purpose cache. Both variants are functionally equivalent. The cache memory: is physically addressed is four-way parallel associative is write-back has four words and a valid flag per line uses a random replacement algorithm is filled line by line Three operating modes are provided so that the cache can be adapted to the application: Mixed-instruction data mode Partially locked mode Split-instruction data mode The cache memory unit control register is used to enable/disable and configure the cache. Cache operation can also be controlled by the cacheable function of the protection unit. The protection unit must always be enabled if the cache is enabled. Otherwise, behavior is undefined. Both functions may be enabled simultaneously with a single write to the control register. The cache memory uses a random replacement algorithm. The various operating modes all use random allocation. In every case, the options only affect cache replacements. The complete cache is always searched for an address, and if the address is found, the data is used or updated. This ensures that the cache is internally consistent and coherent with external memory. The read-lock-write instruction is treated by the IDC as a special case. Externally the two phases are flagged as indivisible by asserting the BLOK signal. The read phase always forces a read of external memory, regardless of whether the data is contained in the cache. The write phase is treated as a normal write operation and if the data is already in the cache, the cache will be updated. The IDC is automatically disabled and flushed on BnRES. Once enabled, cacheable read accesses place lines in the cache. 9

10 Figure 2. Cache Memory Block Diagram MPU Cacheable ASB Address Address Tag Memory Data Memory Data path ASB Interface Miss Data Control ARM Interface Access Control AMBA ASB Interface ASB Control ASB Data 10 Cache Memory

11 Cache Memory Control Registers The cache is controlled by the following bits in the control register. Table 5. Control Register Bit Description Bit Name Bank[1:0] C F Lock[1:0] S Description These bits select the bank to be loaded when the F bit is set. Note: The cache banks are always locked starting from bank 0, so the order of loading should be 0, 1, 2. Although bank 3 can be loaded, there is no mechanism for locking all four cache banks. Cache Enable Bit. The cache is filled when a cacheable (instruction or data) fetch is performed. The cache is loaded by a line fetch of four words. This bit forces all line fetches to apply to the bank selected by Bank[1:0]. When this bit is set, all instruction fetches are forced to be uncacheable data fetches and are still subject to the cacheable mapping in the protection unit. These bits are used to set the number of banks locked. When in split-instruction data mode, they are also used to program the split. Table 5 shows the effect of using the Lock[1:0] bit to lock cache banks. This is the split-instruction data bit. When this bit is set, the cache is configured according to the value of the Lock[1:0] bits. It is illegal to have F and S set simultaneously. The effects of the Lock[1:0] bits when in splitinstruction data mode is shown in Table 7. For a full description of the configuration register, see See Register 1: Control Register on page 6. Table 6. Cache Banks Locked by Lock[1:0] Lock[1:0] Bank 3 Bank 2 Bank 1 Bank 0 Description 00 Cache Cache Cache Cache No Banks Locked 01 Cache Cache Cache Locked 1 Bank Locked 10 Cache Cache Locked Locked 2 Banks Locked 11 Cache Locked Locked Locked 3 Banks Locked Operating Modes Mixed-instruction Data Operation Partially Locked Operation The following operating modes are provided so that the cache can be adapted to the application: Mixed-instruction data Partially locked Split-instruction data This is the standard operating mode for the cache. In this mode, the cache functions as a standard mixed-instruction and data cache. Lines fetched into the cache are placed at random into one of the cache banks. In this mode, critical code and data can be locked into the cache to ensure high performance. To lock code or data into the cache: 1. Select the bank to be loaded using the Bank[1:0] register and set the F bit to 1. Cache banks are always locked starting from bank 0, hence should be loaded and locked in the order 0, 1, Perform a cache flush operation. This is necessary to ensure that the required instructions and data are loaded into the selected cache bank. If this is not performed, they may be elsewhere in the cache and therefore not loaded into the selected bank. 3. Load the instructions or data to be locked into the cache using either LDM or LDR instructions, one per line. While in load mode, all instruction fetches are uncacheable. 11

12 4. Set the F bit to zero. 5. Set the number of banks to be locked into the Lock[1:0] register. 6. Once the lock register is set, the replacement algorithm is prevented from making replacements in the locked banks. This results in reducing the associativity of the cache to the number of banks remaining as cache. Split-instruction Data Operation Another option allows the cache memory unit to be operated in split-instruction data mode. This forces instructions and data to be cached in separate banks of the cache and is used to improve performance where a small code set is processing a large data set. The split nature of the cache means that data does not replace the cached instructions. The allocation of the banks of the cache is shown in Table 7. Table 7. Bank Allocation in Split-instruction Data Mode Lock[1:0] Bank 3 Bank 2 Bank 1 Bank 0 Description 00 Reserved 01 Data Data Data Instruction 1 Bank Instruction, 3 Banks Data 10 Data Data Instruction Instruction 2 Banks Instruction, 2 Banks Data 11 Data Instruction Instruction Instruction 3 Banks Instruction, 1 Bank Data It is not necessary to flush the cache before enabling the split-instruction data mode since the complete cache is searched, regardless of the split selected. 1. Set the S bit. 2. Select the required split using the Lock[1:0] register. If required, this mechanism can be used to make a snapshot of the contents of the instruction banks and to lock them into the cache. The required sequence of operations is as follows: 1. Set the S bit to 1 and select the required split using the Lock[1:0] register. 2. Flush the cache to ensure that the code is loaded into the instruction banks. 3. Execute the required code fragment. 4. Set the S bit to 0, leaving the same value in the Lock[1:0] register. In all cases, when operating in split-instruction data mode, the associativity of each section of the cache is equal to the number of banks allocated to it. Notes: 1. It is illegal to simultaneously have the S bit and the F bit set. 2. It is illegal to have the S bit set with a value of 00 in the Lock[1:0] register. 12 Cache Memory

13 Cache Memory Cache Operation The cache is always searched regardless of whether it is enabled. If an address hits, then the data will be read or written. So when the cache is disabled it should also be flushed. A summary of cache operations is found in Table 8. Table 8. Cache Operations Cacheable Reads Uncacheable Reads Writes A line fetch of four words is performed when a cache-miss occurs in a cacheable area of memory. This is placed in the cache according to the current mode of operation. An external memory access is performed and the cache is not written. All writes update the data in the cache if present and are written through to the main memory. Cacheable Bit Software IDC Flush The appropriate cacheable bit in the cacheable register is used by the protection unit to determine whether data being read may be placed in the IDC and used for subsequent read operations. To improve system performance, main memory is generally marked as cacheable and I/O space as non-cacheable to stop the data from being stored in the cache memory unit. For example, if the processor is polling a hardware flag in the I/O space, it is important that the processor is forced to read data from the external peripheral and not a copy of the initial data held in the cache. See Memory Protection Unit on page 14 for more details. All unlocked banks of the cache may be marked as invalid by writing to the cache memory unit s IDC Flush Register (Register 7). See Register 7: IDC Flush Register on page 8. The cache is flushed immediately as the register is written, but note that the following two instruction fetches may come from the cache before the register is written. 13

14 Memory Protection Unit By maintaining a description of the properties of memory areas in the memory map, the memory protection unit has two primary functions: Control of the cache and write buffer Control of memory access permissions The MPU provides individual control for eight areas of memory numbered 0 to 7. For each area, the following registers can be programmed: Cacheable Basic Protection Size Base Address In this way, the memory architecture of the system can be described in an easily programmable but flexible manner. Protection Unit Registers Several registers are provided by the cache memory unit to control the operation of the protection unit. The format of these registers is shown in Table 3, System Control Registers, on page 5. Control Register For a complete description of the control co-processor, see Configuration on page 3. Register Name: Control Register Access Type: Read/write The configuration register contains the protection enable bit M. On reset, this bit is set to zero, disabling the protection mechanisms and allowing full access to all of the memory. All accesses are then uncacheable and unbufferable M Note that other bits in the configuration register are also used for other functions. For a full description of the configuration register, see Register 1: Control Register on page Cache Memory

15 Cache Memory Cacheable Register This register is used to set the cacheable bit for each of the eight areas of memory The cacheable bit determines if a line fetch should be performed for an access to a given area of memory. The cache is always searched regardless of the state of this bit, and if the required address is found, the copy of the data in the cache will be used. On reset, all areas are marked as uncacheable. Main memory is typically marked as cacheable to provide maximum performance, while peripherals are marked as uncacheable. Protection Register This register controls the access permissions for the eight areas of memory Access permissions for each area of memory are controlled by the value in the protection register. The control accesses are shown in Table 9. Table 9. Access Permission Value Supervisor User 00 No access No access 01 Read/write No access 10 Read/write Read-only 11 Read/write Read/write 15

16 Area Registers The area registers are used to control the parameters of the memory areas controlled by the protection unit. These registers differ from the other CP15 registers with respect to the way memory areas are addressed. Instead of separate bit-fields being used for each region of memory, one register is used for each area indexed by the co-processor operand parameter in the instruction. The number of the memory area to be accessed should be placed in the CP15 operand field of the instruction. See Internal Co-processor Instructions on page COND n CRn Rd CRm where: Bits COND: ARM Condition Code Bit 20 n: 1 = MRC register read 0 = MCR register write Bits CRn: CP15 Source/Destination Register This field is equal to six for the area register. Bits Rd: ARM Register Bits 3..0 CRm: CP15 Operand Register This field is set to the area to be accessed. 16 Cache Memory

17 Cache Memory Each area register uses three fields to describe the location of the area of memory: enable bit E size of the area base address of the area Base[31:12] Size[4:0] E The enable bit E determines if a given area is active. If this bit is set to zero, the area is disabled. The value in Size[4:0] determines the size of a given area of memory, as shown in Table 10. Table 10. Area Sizes Size[4:0] Area Size[4:0] Area 0b Kb 0b Mb 0b Kb 0b Mb 0b Kb 0b Mb 0b Kb 0b Mb 0b Kb 0b Mb 0b Kb 0b Mb 0b Kb 0b Mb 0b Kb 0b Gb 0b Mb 0b Gb 0b Mb 0b Gb 0b Mb Base Address The base address of each area must be aligned with respect to the size of that area. For example, if a region size is set to 16K, then 0x8000 is a legal address for the region to start, but 0x5000 is not legal. The finest resolution that can be used to set the location of a section is 4K, as determined by the setting for the smallest region. If this requirement is not met, the behavior of the protection unit is undefined. 17

18 Accessing the Area Register Protection Unit Operation This register is accessed using MCR and MRC instructions as follows: To write the descriptor for an area of memory: MCR p15, 0, Rd, c6, CRm, 0 where: - CRm is the area of memory to be defined - Rd is the ARM register containing the value to be written into the area register To read back the descriptor: MRC p15, 0, Rd, c6, CRm, 0 where: - CRm is the area of memory to be read - Rd is the ARM register where the descriptor is placed The protection unit compares the address generated by the ARM with the parameters of the eight memory areas. This produces one of three results as shown in Table 11. Table 11. Protection Unit Operation No area hits One area hit Multiple areas hit The access is aborted The properties of this area are applied to the access The properties of the highest priority area are applied to the access. The protection unit operation is illustrated in Figure 3. Figure 3. Protection Unit Operation 4GB Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 Access to Area 5 Address Space Access to Area 0 (Background Permissions) 0 Access to,area 4 (Highest Priority Area) 18 Cache Memory

19 Cache Memory Memory Area Properties Each area of memory is defined in terms of the following properties: base address size access permissions bufferable bit cacheable bit An area s base address must be a multiple of its size. When an address matches multiple areas of memory, the properties of the highest priority area of memory are used. Area priorities are fixed as follows: area 7 has the highest priority area 0 has the lowest priority The bufferable and cacheable bits for the selected area of memory are used to determine if the cache and write buffer should be used (if enabled). Table 12. Cacheable and Bufferable Properties Property Bufferable Cacheable Effect if Set If the access is a write, the write buffer will be used. If the access is a read, a cache line fill will be performed if the required word is not in the cache. Access Permissions Protection Failures and External Accesses Reset Overlapping Memory Regions Access permission bits are checked against access type. Details of decoding are found in Table 9, Access Permission, on page 15. If access is permitted, the ARM continues. If access is prohibited, the ARM is aborted and there is no access on the external bus. If an access violation is detected by the protection unit, access is then inhibited to the external memory. External aborts, however, do not necessarily inhibit the external access, as described in External Aborts on page 20. An internally aborting access may cause the address on the external address bus to change, even though the external bus cycle has been cancelled. No memory access is performed to this address. The protection unit is disabled on BnRES. Before it is enabled, all the protection unit registers must be programmed. If this is not respected, unpredictable behavior will result. When mapping logical memory regions into physical memory devices, overlapping regions can be used to allow greater flexibility. For example, consider the case where the system has 4K of supervisor code and 28K of user code, both of which must be mapped into a 32K RAM. If overlapping memory is not supported, four regions would have to be used to achieve this: one 4K region for the supervisor code one 32K region one 16K region one 4K region for the user code 19

20 If the supervisor and user code regions can be overlapped, this can be achieved using only two regions: one 4K region for the supervisor code one 32K region for the user code Thus in Figure 4, by way of example, the supervisor code could be placed in Region 2, and the user code in Region 1. This would ensure that the supervisor mapping takes precedence over the less strict user mapping. Figure 4. Use of Overlapping Memory Regions Supervisor Only Full Access 1 Four Regions Required Two Regions Required Undefined Address Space External Aborts Restrictions Cacheable Reads (Line Fetches) The default protection for otherwise unmapped memory can be programmed by using the mechanism for overlapping segments. If the memory regions do not completely fill the 4 GB of address space of the ARM7TDMI, there are holes in the address map. By configuring Region 0 (the lowest priority region) to be 4 GB in size, the user can program what happens if an access becomes a hole. For example, the attributes could be set to full access or no access. Alternatively, the user may choose to ignore the holes, and any access to an area of memory not described by the protection unit results in an abort. In addition to the aborts generated by the protection unit, the cache memory unit has an external abort input BERROR that may be used to flag an error on an external memory access. However, not all accesses can be aborted in this way, so this input must be used with great care. The following accesses may be aborted and restarted safely: reads unbuffered writes read-lock-write sequence If any of these are aborted, the external access ceases on the next cycle. In the case of a read-lock-write sequence in which the read aborts, the write does not occur. A line fetch may be safely aborted on any word in the transfer: If an abort occurs during the line fetch, the cache is purged, so it does not contain invalid data. If the abort happens on a word that has been requested by the cache memory unit, it is aborted. Otherwise, the cache line is purged but program flow is not interrupted. The line is therefore purged under all circumstances. 20 Cache Memory

21 Cache Memory Performance and Waveforms Performance Waveforms Performance is expressed in terms of the number of clock cycles per hit access or miss access. Number of clock cycles per hit access: Read access: 1 cycle (0 wait states) Write access: 2 cycles (1 wait state) Number of clock cycles per miss access: Miss-on-read access without line replacement: 5 cycles + (access time for 4-word read burst from external memory) Miss-on-write access without line replacement: 6 cycles + (access time for 4-word read burst from external memory) Miss (read or write) and line replacement: 6 cycles + (access time for 4-word read burst from external memory) + (access time for 4- word write burst to external memory) For non-cacheable accesses, there is no penalty due to cache insertion. It is possible to work at zero wait states in read and write. This depends only on required external wait states. In order to improve visibility on waveforms, a zero-wait-states external memory is used in the examples that follow. Waveform Signals Table 13. External Memory Bus (AMBA ASB) xxx.cpu1.mclk xxx.cache.ba xxx.cache.bdi xxx.cache.bdo xxx.cache.btran xxx.cache.bwrite Main clock CPU bus and BCLK Address bus to external memory Data bus from external memory Data bus to external memory Transfer type Write signal Table 14. ARM Side Bus xxx.cpu1.a xxx.cpu1.d xxx.cpu1.nrw xxx.cpu1.nwait xxx.cpu1.nmreq xxx.cpu1.seq Address bus to cache Data bus to/from cache Write to cache Wait from cache Memory request to cache Sequential address to cache 21

22 Table 15. Internal Cache Memories xxx.core.tagmem.miss xxx.core.datmem.add xxx.core.datem.din xxx.core datem.dout xxx.core datmem.we xxx.core.control.cacheable Miss signal (active high) Internal data memory address Data-to-data memory Data-from-data memory Write enables to data memories (4 ways) Cacheable signal (active high) 22 Cache Memory

23 TEST_CACHE.cpu1.MCLK TEST_CACHE.cache.BA TEST_CACHE.cache.BDI TEST_CACHE.cache.BDO TEST_CACHE.cache.BTRAN TEST_CACHE.cache.BWRITE TEST_CACHE.cpu1.A c e59f51a Figure 5. Miss-on-read Access TEST_CACHE.cpu1.D TEST_CACHE.cpu1.nRW TEST_CACHE.cpu1.nWAIT TEST_CACHE.cpu1.nMREQ e59f51a TEST_CACHE.cpu1.SEQ cache.core.tagmem.miss MISS ON READ ACCESS cache.core.datmem.add c cache.core.datem.din cache.core.datem.dout cache.core.datmemwe[3] cache.core.datmemwe[2] cache.core.datmemwe[1] cache.core.datmemwe[0] cache.core.control.cacheable time (ps) e59f51a Cache Memory

24 24 Cache Memory TEST_CACHE.cpu1.MCLK TEST_CACHE.cache.BA TEST_CACHE.cache.BDI TEST_CACHE.cache.BDO TEST_CACHE.cache.BTRAN TEST_CACHE.cache.BWRITE TEST_CACHE.cpu1.A TEST_CACHE.cpu1.D TEST_CACHE.cpu1.nRW TEST_CACHE.cpu1.nWAIT TEST_CACHE.cpu1.nMREQ TEST_CACHE.cpu1.SEQ cache.core.tagmem.miss cache.core.datmem.add cache.core.datem.din cache.core.datem.dout cache.core.datmemwe[3] cache.core.datmemwe[2] cache.core.datmemwe[1] e088800a e088800a c c aaaaaaaa aaaaaaaa MISS ON READ ACCESS AND DIRTY LINE REPLACEMENT (WRITE BACK) aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa c c 000 aaaaaaaa aaaaaaaa aaaaaaaa e088800a aaaaaaaa aaaaaaaa Figure 6. Miss-on-read Access and Dirty Line Replacement (Write-back) cache.core.datmemwe[0] cache.core.control.cacheable time (ps)

25 TEST_CACHE.cpu1.MCLK TEST_CACHE.cache.BA TEST_CACHE.cache.BDI TEST_CACHE.cache.BDO TEST_CACHE.cache.BTRAN TEST_CACHE.cache.BWRITE TEST_CACHE.cpu1.A TEST_CACHE.cpu1.D TEST_CACHE.cpu1.nRW TEST_CACHE.cpu1.nWAIT TEST_CACHE.cpu1.nMREQ TEST_CACHE.cpu1.SEQ e e c e3a e c e786c008 e786c008 e3a e aaaaaaaa Figure 7. Write-and-read Hit Cacheable Accesses cache.core.tagmem.miss cache.core.datmem.add c cache.core.datem.din aaaaaaaa aaaaaaaa 25 cache.core.datem.dout cache.core.datmemwe[3] cache.core.datmemwe[2] cache.core.datmemwe[1] cache.core.datmemwe[0] cache.core.control.cacheable time (ps) e WRITE AND READ HIT CACHEABLE ACCESSES e786c008 e3a e Cache Memory

26 26 Cache Memory TEST_CACHE.cpu1.MCLK TEST_CACHE.cache.BA TEST_CACHE.cache.BDI TEST_CACHE.cache.BDO TEST_CACHE.cache.BTRAN TEST_CACHE.cache.BWRITE fc c aaaaaaaa aaaaaaaa Figure 8. Miss-on-write Access TEST_CACHE.cpu1.A fc TEST_CACHE.cpu1.D TEST_CACHE.cpu1.nRW TEST_CACHE.cpu1.nWAIT TEST_CACHE.cpu1.nMREQ TEST_CACHE.cpu1.SEQ cache.core.tagmem.miss cache.core.datmem.add 1fc c cache.core.datem.din cache.core.datem.dout cache.core.datmemwe[3] cache.core.datmemwe[2] cache.core.datmemwe[1] cache.core.datmemwe[0] cache.core.control.cacheable aaaaaaaa aaaaaaaa MISS ON WRITE ACCESS time (ps)

27 27 TEST_CACHE.cpu1.MCLK TEST_CACHE.cache.BA TEST_CACHE.cache.BDI TEST_CACHE.cache.BDO TEST_CACHE.cache.BTRAN TEST_CACHE.cache.BWRITE TEST_CACHE.cpu1.A TEST_CACHE.cpu1.D TEST_CACHE.cpu1.nRW TEST_CACHE.cpu1.nWAIT TEST_CACHE.cpu1.nMREQ TEST_CACHE.cpu1.SEQ cache.core.tagmem.miss cache.core.datmem.add cache.core.datem.din cache.core.datem.dout cache.core.datmemwe[3] cache.core.datmemwe[2] cache.core.datmemwe[1] cache.core.datmemwe[0] cache.core.control.cacheable time (ps) d dc e cc d d bafffffb e59f9054 ee019f11 e e088800a e NON CACHEABLE ACCESSES WITH EXTERNAL 0 WAIT STATES MEMORY d dc e cc d d bafffffb e59f9054 ee019f11 e e088800a e d8 1dc 1e0 1cc 1d0 1d Figure 9. Non-cacheable Accesses with External Zero-wait-states Memory Cache Memory

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