S1R72V17 CPU Connection Guide

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1 S1R72V17 CPU Connection Guide Rev. 1.0

2 NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of Economy, Trade and Industry or other approval from another government agency. SEIKO EPSON CORPORATION 2008, All rights reserved.

3 Scope This document applies to the S1R72V17 USB2.0 host/device controller LSI.

4 Table of Contents 1. Introduction Overview Related Documents Connection Example with Standard CPU Endian Settings for 16-bit Bus Width Connection Connection to Big-endian CPU Connection to Little-endian CPU CPUIF Verification Procedure Connection Example with FreeScale imx Connection Example imx21 Bus Cycle Setting Example Checking S1R72V17 AC Spec and imx21 Bus Cycle S1R72V17 CPU Connection Guide EPSON i

5 1. Introduction 1. Introduction 1.1 Overview This document contains information required for actual use of the S1R72V17 by the customer, focusing on the details necessary to connect the S1R72V17 to the control CPU. This document describes typical connection methods. No guarantees are made regarding the suitability of these methods. The connection methods must be modified to suit specific customer system configurations. The contents of this document are subject to change without notice. 1.2 Related Documents S1R72V17 Technical Manual (Hardware Specifications) S1R72V17 CPU Connection Guide EPSON 1

6 2. Connection Example with Standard CPU 2. Connection Example with Standard CPU This section illustrates a typical connection with a standard CPU. 1) 16-bit bus, Strobe mode connection example Set CPU_Config register (0x075h address) BusMode bit to 0 and Bus8x16 bit to 0. 16bit Strobe mode 1.65 V to 3.6 V CPU S1R72V17 IOVDD CVDD Address[8:1] CA[8:1] XBEL(CA[0]) DATA[15:0] CD[15:0] XCS XCS XRD XRD XWRH XWRH(XBEH) XWRL XWRL(XWR) XDREQ XDREQ *1 <When DMA is not used> XDACK XDACK *2 *1: Open XINT XINT *2: Fixed at High or Low Fig bit bus, Strobe mode connection example 2 EPSON S1R72V17 CPU Connection Guide

7 2. Connection Example with Standard CPU 2) 16-bit bus, BE mode connection example Set CPU_Config register (0x075h address) BusMode bit to 1 and Bus8x16 bit to 0. 16bit BE mode 1.65 V to 3.6 V CPU S1R72V17 IOVDD Address[8:1] XBEL DATA[15:0] XCS XRD XBEH XWR CVDD CA[8:1] XBEL(CA[0]) CD[15:0] XCS XRD XWRH(XBEH) XWRL(XWR) XDREQ XDREQ *1 XDACK XDACK *2 XINT XINT <When DMA is not used> *1: Open *2: Fixed at High or Low 3) 8-bit bus mode connection example Fig bit bus, BE mode connection example Set CPU_Config register (0x075h address) BusMode bit to 0 and Bus8x16 bit to 1. 8bit mode 1.65 V to 3.6 V CPU S1R72V17 IOVDD Address[8:1] Address[0] CVDD CA[8:1] XBEL(CA[0]) CD[15:8] DATA[7:0] CD[7:0] XCS XCS XRD XRD XWRH(XBEH) XWR XWRL(XWR) XDREQ XDREQ *1 <When DMA is not used> XDACK XDACK *2 *1: Open XINT XINT *2: Fixed at High or Low Fig bit bus mode connection example S1R72V17 CPU Connection Guide EPSON 3

8 3. Endian Settings for 16-bit Bus Width Connection 3. Endian Settings for 16-bit Bus Width Connection This section describes endian settings when connecting to a CPU with a 16-bit bus width. The discussion of the S1R72V17 registers divides them into the following three types. For register details, refer to the S1R72V17 Technical Manual. 1) Word register: Registers with _H/_L/_HH/_HL/_LH/_LL at the end of the register name 2) Byte register: Registers not corresponding to Word or FIFO registers 3) FIFO register: RAM_Rd_00 to _1F/RAM_WrDoor_0,1/FIFO_Rd_0,1/FIFO_Wr_0,1/ FIFO_ByteRd registers 3.1 Connection to Big-endian CPU Access is normally in the mode with 0 set in the CPU_Config register (0x075h address) CPU_Endian bit. 1) Access to Word register The S1R72V17 connects the D[15:8] bus to the first byte of the Word register and the D[7:0] bus to the last byte of the Word register. The example below illustrates the writing and reading of 0x1234h data to/from the Word register. Writing: Reading: The data (12h) in the CPU memory even-number address is saved to the first byte of the S1R72V17 Word register. The first byte data (12h) of the S1R72V17 Word register is saved to the even-number address in CPU memory. CPU Data 12h 34h Even-number address Odd-number address Data in CPU memory Higher byte [15:8] Lower byte [7:0] 12h 34h CPU register D[15:8] D[7:0] CPU data bus D[15:0] bus connected unchanged S1R72V17 D[15:8] D[7:0] V17 data bus 12h 34h V17 Word register Higher byte [15:8] Lower byte [7:0] _H, _HH, _LH registers _L, _HL, _LL registers Fig. 3-1 Access to Word registers (big-endian CPU) 4 EPSON S1R72V17 CPU Connection Guide

9 3. Endian Settings for 16-bit Bus Width Connection 2) Access to Byte register The S1R72V17 connects the D[15:8] bus to the even-number address register and the D[7:0] bus to the odd-number address register when the CPU_Endian bit is set to 0. The example below illustrates the writing and reading of F1h to/from the Byte register even-number address register and of F2h to/from the Byte register odd-number address register. Writing: Reading: The data (F1h) in the CPU memory even-number address is saved to the S1R72V17 even-number address register. The S1R72V17 even-number address register data (F1h) is saved to the even-number address in CPU memory. CPU Data F1h F2h Even-number address Odd-number address Data in CPU memory Higher byte [15:8] Lower byte [7:0] F1h F2h CPU register D[15:8] D[7:0] CPU data bus D[15:0] bus connected unchanged S1R72V17 D[15:8] D[7:0] V17 data bus F2h F1h V17 Byte register Odd-number address Even-number address register register Fig. 3-2 Access to Byte registers (big-endian CPU) S1R72V17 CPU Connection Guide EPSON 5

10 3. Endian Settings for 16-bit Bus Width Connection 3) Access to FIFO register The S1R72V17 connects the D[15:8] bus to the even-number address register and the D[7:0] bus to the odd-number address register when the CPU_Endian bit is set to 0. The example below illustrates transmission from the USB bus in the sequence C1h/C2h and receiving in the sequence C1h/C2h. Writing: Reading: The data (C1h) in the CPU memory even-number address is sent from the USB bus as the first data. The first data received from the USB bus (C1h) is saved to the even-number address in CPU memory. CPU Data C1h C2h Even-number address Odd-number address Data in CPU memory Higher byte [15:8] Lower byte [7:0] C1h C2h CPU register D[15:8] D[7:0] CPU data bus D[15:0] bus connected unchanged S1R72V17 D[15:8] D[7:0] V17 data bus C2h C1h V17 Byte register Odd-number address Even-number address register register Data[15:8] Data[7:0] V17 FIFO data (2) C2h (1) C1h Sent via USB bus in order (1), (2). (4) (3) Fig. 3-3 Access to FIFO registers (big-endian CPU) 6 EPSON S1R72V17 CPU Connection Guide

11 3. Endian Settings for 16-bit Bus Width Connection 3.2 Connection to Little-endian CPU Access is normally in the mode with 1 set in the CPU_Config register (0x075h address) CPU_Endian bit. 1) Access to Word register The S1R72V17 connects the D[15:8] bus to the first byte of the Word register and the D[7:0] bus to the last byte of the Word register. The example below illustrates the writing and reading of 0x1234h data to/from the Word register. Writing: Reading: The data (34h) in the CPU memory even-number address is saved to the last byte of the S1R72V17 Word register. The last byte data (34h) of the S1R72V17 Word register is saved to the even-number address in CPU memory. CPU Data 34h 12h Even-number address Odd-number address Data in CPU memory Higher byte [15:8] Lower byte [7:0] 12h 34h CPU register D[15:8] D[7:0] CPU data bus D[15:0] bus connected unchanged S1R72V17 D[15:8] D[7:0] V17 data bus 12h 34h V17 Word register Higher byte [15:8] Lower byte [7:0] _H, _HH, _LH registers _L, _HL, _LL registers Fig. 3-4 Access to Word registers (little-endian CPU) S1R72V17 CPU Connection Guide EPSON 7

12 3. Endian Settings for 16-bit Bus Width Connection 2) Access to Byte register The S1R72V17 connects the D[7:0] bus to the even-number address register and the D[15:8] bus to the odd-number address register when the CPU_Endian bit is set to 1. The example below illustrates the writing and reading of F1h to/from the Byte register even-number address register and of F2h to/from the Byte register odd-number address register. Writing: Reading: The data (F1h) in the CPU memory even-number address is saved to the S1R72V17 even-number address register. The S1R72V17 even-number address register data (F1h) is saved to the even-number address in CPU memory. CPU Data F1h F2h Even-number address Odd-number address Data in CPU memory Higher byte [15:8] Lower byte [7:0] F2h F1h CPU register D[15:8] D[7:0] CPU data bus D[15:0] bus connected unchanged S1R72V17 D[15:8] D[7:0] V17 data bus F2h F1h V17 Byte register Odd-number address Even-number address register register Fig. 3-5 Access to Byte registers (little-endian CPU) 8 EPSON S1R72V17 CPU Connection Guide

13 3. Endian Settings for 16-bit Bus Width Connection 3) Access to FIFO register The S1R72V17 connects the D[7:0] bus to the even-number address register and the D[15:8] bus to the odd-number address register when the CPU_Endian bit is set to 1. The example below illustrates transmission from the USB bus in the sequence C1h/C2h and receiving in the sequence C1h/C2h. Writing: Reading: The data (C1h) in the CPU memory even-number address is sent from the USB bus as the first data. The first data received from the USB bus (C1h) is saved to the even-number address in CPU memory. CPU Data C1h C2h Even-number address Odd-number address Data in CPU memory Higher byte [15:8] Lower byte [7:0] C2h C1h CPU register D[15:8] D[7:0] CPU data bus D[15:0] bus connected unchanged S1R72V17 D[15:8] D[7:0] V17 data bus C2h C1h V17 Byte register Odd-number address Even-number address register register Data[15:8] Data[7:0] V17 FIFO data (2) C2h (1) C1h Sent via USB bus in order (1), (2). (4) (3) Fig. 3-6 Access to FIFO registers (little-endian CPU) S1R72V17 CPU Connection Guide EPSON 9

14 4. CPUIF Verification Procedure 4. CPUIF Verification Procedure The procedure shown here checks whether the S1R72V17 is correctly connected to the CPU. Follow the procedure given below, using ICE on the CPU used to control this LSI. <Connection test start (HW reset cancel)> 1) Recovery processing from CPU_Cut state Dummy read PM_Control register (0x012 address) 2) Endian setting initialization Dummy read CPU_ChgEndian register (0x077h address) 3) CPU operating mode setting Set CPU_Endian, BusMode, Bus8x16 to the CPU_Config register Little-endian CPU: 0x74h address Big-endian CPU: 0x75h address 4) Endian setting enabling Dummy read CPU_ChgEndian register (0x077h address) 5) Asynchronous register access test (Word register) Read/write test to/from WakeupTim_H,L registers (0x014h address) 6) Clock input setting Write clock setting value to ClkSelect register (0x73h address) 7) Clock input setting protect Write 0x00 to ModeProtect register (0x071 address) 8) MTM reset Write 0x00 to ChipReset register (0x011 address) 9) Oscillation start time setting Write oscillation start time to WakeupTim_H,L registers (0x014 address) 10) Internal clock feed setting Write 0x40 to PM_Control register (0x012 address) 7 11) Internal MTMリセット clock setting confirmation Read MainIntStat register (0x000 address) to check that FinishedPM bit (bit 0) is set to 1. 12) Synchronous register access test (Word register) Read/write test to/from AREA0StartAdrs_L,H registers (0x080 address) 13) Synchronous register access test (Byte register) Read/write test to/from D_EPaIntEnb register (0x0C6 address) and D_EPbIntEnb register (0x0C7 address) <Connection test end> Fig. 4-1 CPU-IF verification procedure 10 EPSON S1R72V17 CPU Connection Guide

15 4. CPUIF Verification Procedure 1) Recovery processing from CPU_Cut state Dummy read the PM_Control register (0x012h address). The S1R72V17 switches to CPU_Cut state after resetting has been cancelled. This dummy read operation ends the CPU_Cut state and switches to Sleep. In the Sleep state, reading/writing is possible to/from all asynchronous registers. 2) Endian setting initialization Dummy read the CPU_ChgEndian register (0x077h address). Setting the ChipReset register (0x011h address) AllReset bit to 1 enables the reset CPU_Config register CPU_Endian setting after this register has been dummy read when the S1R72V17 has been reset. 3) CPU operating mode setting Write the usage mode settings to the CPU_Config register CPU_Endian, BusMode, and Bus8x16 bits. Little-endian CPU: 0x74h address Big-endian CPU: 0x75h address This register address is assigned to the 0x075h address. Since the S1R72V17 operates in the default big-endian state until this setting is changed, the 0x074h address should be accessed to access a little-endian CPU. Table 4-1 CPU_Config register settings Bus mode CPU endian Setting 16-bit Strobe mode Little Endian 0x04 Big Endian 0x00 16-bit BE mode Little Endian 0x06 Big Endian 0x02 8-bit mode - 0x01 4) Endian setting enabling Dummy read the CPU_ChgEndian register (0x77h address). Reading this register enables the CPU_Endian bit set in 3). 5) Asynchronous register access test (Word register) Read/write test to/from the WakeupTim_L,H registers (0x014 address). This register can be read/written in the Sleep state. All bits are enabled. Read/write testing this register checks whether the CPU data bus is correctly connected. If this read/write operation is not performed correctly, check the physical connection with the CPU. S1R72V17 CPU Connection Guide EPSON 11

16 4. CPUIF Verification Procedure 6) Clock input setting Write the clock input setting value to the ClkSelect register (0x73h address). This sets the clock input method and frequency used for the S1R72V17. The settings are shown in Table 4-2. Table 4-2 ClkSelect register settings Clock input method Clock frequency External oscillator External clock source 12 MHz 0x00 0x80 24 MHz 0x01 0x81 48 MHz Not available 0x83 7) Clock input setting protect Write 0x00 to the ModeProtect register (0x071 address). Writing a value other than 0x56 to this register enables write protection for the ClkSelect register. 8) MTM reset Write 0x00 to the ChipReset register (0x011 address). Clearing the bit7 ResetMTM bit to 0 clears the USB Transceiver Macro reset and enables oscillation of the PLL contained in the S1R72V17. 9) Oscillation start time setting Write the oscillation start time to the WakeupTim_H,L registers (0x014 address). With external clock source: Write 0x0010. Note that the external clock source oscillation must have stabilized before this occurs. With external oscillator: The standard time is usually within the clock frequency ±10%, but this will vary greatly, depending on the selected oscillator, circuit board, and external components. Write 0x2500 here to check the connection. 10) Internal clock feed setting Write 0x40 to the PM_Control register (0x012 address). Setting the bit6 GoActive bit to 1 starts the internal clock operation (starts OSC and PLL) and starts the clock feed to the internal circuit. 12 EPSON S1R72V17 CPU Connection Guide

17 4. CPUIF Verification Procedure 11) Internal clock feed confirmation Read the MainIntStat register (0x000 address) to confirm that the FinishedPM bit (bit 0) has been set to 1. If this bit is not set, it is likely that the clock is not fed from the external clock when the external clock source is selected and that the oscillator is not oscillating correctly when the external oscillator is selected. In this case, the 0x008 address (MainIntEnb register) bit 0 (EnFinishedPM bit) should be set to 1. This asserts the XINT output pin to Low. Subsequently clearing the bit to 0 negates the XINT output pin to High. This operation should be used to confirm that an interrupt occurs in the CPU. Writing 1 to the MainIntStat register (0x000 address) bit 0 (FinishedPM bit) clears this status. Read the MainIntStat register (0x000 address) bit 0 (FinishedPM bit) again to confirm that it has been cleared to 0. 12) Synchronous register access test (Word register) Read/write test to/from the AREA0StartAdrs_L,H registers (0x080 address). These registers can be read/written in the Active state. The first 3 bits (bits [15:13]) and the last 2 bits (bits [1:0]) cannot be written to. They will always read 0. 13) Synchronous register access test (Byte register) Read/write test to/from the D_EPaIntEnb register (0x0C6 address) and D_EPbIntEnb registers (0x0C7 address). These registers can be read/written in the Active state. The first bit (bit [7]) for the D_EPaIntEnb and D_EPbIntEnb registers cannot be written to and always reads 0. <This ends the connection test.> S1R72V17 CPU Connection Guide EPSON 13

18 5. Connection Example with FreeScale imx21 5. Connection Example with FreeScale imx Connection Example This section illustrates an example of a connection between the proven CPU-IF on the S1R72V17 and the imx21. The connection uses the S1R72V17 16-bit BE mode bus mode. Typ: 1.8V imx21(mc9328mx21) NVDD1 to 6 A[8:1] D[15:0] CS1 OE/PC_IOWR EB3/DQM3/PC_IORD EB2/DQM3/PC_REG RW/PC_WE CSPI1_RDY LD16 LD17 S1R72V17 CVDD CA[8:1] CD[15:0] XCS XRD XBEL(CA[0]) XWRH(XBEH) XWRL(XWR) XDREQ XDACK XINT Fig. 5-1 Connection example with imx21 1) CPU-IF power supply voltage In this connection example, the CPU-IF supply voltage is Typ 1.8 V. imx21 IO supply voltage (NVDD1 to 6): 1.7 V to 3.3 V S1R72V17 CPU-IF supply voltage (CVDD): 1.65 V to 3.6 V 14 EPSON S1R72V17 CPU Connection Guide

19 5. Connection Example with FreeScale imx21 2) imx21 shared pin settings The imx21 shared pins are set as shown below in this connection example. Table 5-1 imx21 shared pin settings imx21 pin name imx21 pin function NVDD1 to NVDD6 NVDD1 to NVDD6 A[8:1] A[8:1] D[15:0] D[15:0] CS1 CS1 OE/PC_IOWR OE EB3/DQM3/PC_IORD EB3 EB2/DQM2/PC_REG EB2 RW/PC_WE RW CSPI1_RDY EXT_DMAREQ LD16 EXT_DMAGRANT LD17 PA23(GPIO used as XINT) S1R72V17 CPU Connection Guide EPSON 15

20 5. Connection Example with FreeScale imx imx21 Bus Cycle Setting Example imx21 clock settings The imx21 clock settings are set as shown below in this connection example. System clock: 264 MHz CPU-IF bus clock (HCLK): 88 MHz (system clock 3 divisions) Bus cycle settings CS1U register (0xDF address) Setting: 0x0402_ SP WP DCT RWA PSZ PME SYNC RWN CNC WSC EW WWS EDC CS1L register (0xDF00100C address) Setting: 0x4200_0D OEA OEN WEA WEN CSA EBC DSZ CSN PSR CRE WRAPCSEN Setting descriptions Register Setting Description RWA 4'b0100 RW output assert timing (2HCLK) SYNC 1'b0 Synchronous transfer mode (disabled) RWN 4'b0010 RW output negate timing (1HCLK) WSC 6'b Access cycle (8HCLK) WWS 3'b000 Wait cycle for write (0HCLK) OEA 4'b0100 OE output assert timing (2HCLK) OEN 4'b0010 OE output negate timing (1HCLK) WEA 4'b0000 EBx output assert timing (0HCLK) WEN 4'b0000 EBx output negate timing (0HCLK) CSA 4'b0000 CS1 output assert timing (0HCLK) EBC 1'b1 EB3, 2 output mode for read (disabled) DSZ 3'b101 Data bus size (using 16 bits [15:0]) CSN 4'b0000 CS1 output assert timing (0HCLK) CSEN 1'b1 CS1 enable (enabled) Fig. 5-2 Bus cycle setting registers 16 EPSON S1R72V17 CPU Connection Guide

21 5. Connection Example with FreeScale imx21 Bus cycle waveform <Read cycle> Bus cycle Read access WSC (8HCLK) HCLK bus clock A[8:1] (O) A0 CS1 (O) CSA (0HCLK) CSN (0HCLK) OE (O) <Write cycle> OEA (2HCLK) OEN (1HCLK) Bus cycle Write access WSC (8HCLK) HCLK bus clock A[8:1] (O) A0 CS1 (O) CSA (0HCLK) CSN (0HCLK) RW (O) EB3,2 (O) RWA (2HCLK) WEA (0HCLK) RWN (1HCLK) WEN (0HCLK) Fig. 5-3 imx21 bus cycle waveform S1R72V17 CPU Connection Guide EPSON 17

22 5. Connection Example with FreeScale imx Checking S1R72V17 AC Spec and imx21 Bus Cycle The table below compares S1R72V17 AC specification values to imx21 bus cycle settings. For more information on S1R72V17 AC specification, refer to CPU/DMA IF Access Timing ( Basic Cycle) in the S1R72V17 Technical Manual. Table 5-2 AC Specification Comparison S1R72V17 CPU/DMA IF access timing imx21 setting Code Item min max Cycles unit imx21 setting register tcas Address setup time 6-2 HCLK RWA, OEA tcah Address hold time (from strobe negation) 6-1 HCLK RWN, OEN tsah Address hold time (from strobe assertion) 55-6 HCLK WSC-(RWA, OEA) tccs XCS setup time 6-2 HCLK RWA, OEA tcch XCS hold time 6-1 HCLK RWN, OEN trcy Read cycle 80-8 HCLK WSC tras Read strobe assert time 40-5 HCLK WSC-(OEA+OEN) trng Read strobe negate time 25-3 HCLK OEA+OEN trbd Read data output start time trdf Read data confirmation time HCLK WSC-(OEA+OEN) trdh Read data hold time trbh Read data output delay time twcy Write cycle 80-8 HCLK WSC twas Write strobe assert time 40-5 HCLK WSC-(RWA+RWN) twng Write strobe negate time 25-3 HCLK RWA+RWN twbs Write byte enable setup time 6-2 HCLK RWA twbh Write byte enable hold time 6-1 HCLK RWN twds Write data setup time HCLK RWA - 0.5HCLK (data output start) twdh Write data hold time 0-1 HCLK RWN tdrn XDREQ negate delay time tdaa XDREQ setup time tdan XDREQ hold time ( C L =30pf ) 1HCLK=11.36ns (88MHz) 18 EPSON S1R72V17 CPU Connection Guide

23 Revision History Revision History Revision details Date Rev. Page Type Details 06/06/ All New Newly created

24 International Sales Operations AMERICA EPSON ELECTRONICS AMERICA, INC. HEADQUARTERS 2580 Orchard Parkway San Jose, CA 95131,USA Phone: FAX: SALES OFFICES Northeast 301 Edgewater Place, Suite 210 Wakefield, MA 01880, U.S.A. Phone: FAX: EUROPE EPSON EUROPE ELECTRONICS GmbH HEADQUARTERS Riesstrasse 15 Muenchen Bayern, GERMANY Phone: FAX: ASIA EPSON (CHINA) CO., LTD. 7F, Jinbao Bldg.,No.89 Jinbao St.,Dongcheng District, Beijing , China Phone: FAX: SHANGHAI BRANCH 7F, Block B, Hi-Tech Bldg., 900, Yishan Road, Shanghai , CHINA Phone: FAX: EPSON HONG KONG LTD. 20/F., Harbour Centre, 25 Harbour Road Wanchai, Hong Kong Phone: FAX: Telex: EPSCO HX EPSON (CHINA) CO., LTD. SHENZHEN BRANCH 12/F, Dawning Mansion, Keji South 12th Road, Hi- Tech Park, Shenzhen Phone: FAX: EPSON TAIWAN TECHNOLOGY & TRADING LTD. 14F, No. 7, Song Ren Road, Taipei 110 Phone: FAX: EPSON SINGAPORE PTE., LTD. 1 HarbourFront Place, #03-02 HarbourFront Tower One, Singapore Phone: FAX: SEIKO EPSON CORPORATION KOREA OFFICE 50F, KLI 63 Bldg., 60 Yoido-dong Youngdeungpo-Ku, Seoul, , KOREA Phone: FAX: GUMI OFFICE 2F, Grand B/D, Songjeong-dong, Gumi-City, KOREA Phone: FAX: SEIKO EPSON CORPORATION SEMICONDUCTOR OPERATIONS DIVISION IC Sales Dept. IC International Sales Group 421-8, Hino, Hino-shi, Tokyo , JAPAN Phone: FAX: Document Code: First Issue June 2008 in JAPAN C

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