ET355 Microprocessors Friday 6:00 pm 10:20 pm

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1 ITT Technical Institute ET355 Microprocessors Friday 6:00 pm 10:20 pm Unit 3 Chapter 4, pp Chapter 5, pp

2 Unit 3 Objectives Lecture: Review I/O Ports and Flags of 805x Microprocessor Review Addressing Modes of 805x Microprocessor Review Programming Examples for I/O modes Review Cautions of I/O configurations on Trainer Board Lab:. Reinforce Lecture Topics through Practical Experience. Assignment: Reinforce both Lecture & Lab Topics through Practical Experience.

3 Unit 3 Agenda Lecture: Chapter 4, pp Chapter 5, pp Lab: Refer to ET355 Agenda and Assignment document provided by your instructor or obtained on Your instructor must sign-off lab and you must submit with Lab Questions answered. Assignment: Refer to ET355 Agenda and Assignment document provided by your instructor or obtained on

4 Unit 3: Chapter 4, Section 4.2 Recapping lecture from last week. I/O Ports and Bit-Addressability: Sometimes we need to access only 1 or 2 bits of the port instead of the entire 8 bits. We can access either the entire 8 bits or any single bit without altering the rest. SETB X.Y SETB P1.5 sets high bit 5 of port 1

5 Unit 3: Chapter 4, Section 4.2 Table 4-3: Single-Bit Addressability of Ports

6 Unit 3: Chapter 4, Section 4.2 Table 4 4 Single-Bit Instructions See Example 4.2 on Page 101: Notice that unused portions of ports 1 and 2 are undisturbed.

7 Unit 3: Chapter 4, Section 4.2 Checking an Input bit Practical Solution of Example 4-4 (page 103) Also Example 4-5 (page 103) See Example 4.3 on Page 102: Notice that they use the JNB and JB operands. JNB and JB can be used for any bits of I/O ports 0, 1, 2, or 3, however, most of port 3 is used for interrupts and serial communication signals, and typically not used for any I/O (discussed in Chapters 10 & 11)

8 Unit 3: Chapter 4, Section 4.2 Reading a single bit into the carry flag We use the Carry flag to save or examine the status of a single bit of the port See Example 4.6 and 4-7 on page 104

9 Unit 3: Chapter 4, Section 4.2 Reading Input pins vs. port latch In reading a port, some instructions read the status of port pins while others read the status of an internal port latch. Therefore, when reading a port, there are two possibilities: 1. Read the status of the input pins 2. Read the internal latch of the output port Table 4 5 Instructions For Reading an Input Port

10 Unit 3: Chapter 4, Section 4.2 Reading latch for output port

11 Unit 3: Chapter 4, Section 4.2 CAUTION We strongly recommend that you study Section C.2 (Appendix C) if you are connecting any external hardware to your 8051 system. Failure to use the right instruction or the right connection to port pins can damage the ports of your 8051 system. Page 106

12 BREAK COME BACK TO CHAPTER 5

13 Unit 3: Chapter 5, Section 5.1 Immediate and Register Addressing Mode Immediate Addressing Mode In this addressing mode, the source operand is a constant. MOV A, #25H ; load 25H into A MOV R4 #62 ; load the decimal value 62 into R4 MOV B, #40H ; load #40H onto B MOV DPTR, #4521H ; DPTR = 4521H (value cannot exceed 16 bits) MOV DPL, #21H MOV DPH, #45H

14 Unit 3: Chapter 5, Section 5.1 Register Addressing Mode Register addressing mode involves the use of registers to hold data to be manipulated. MOV A, R0 ; load contents of R0 into A MOV R2, A ; load contents of A into R2 ADD A, R5 ; add the contents of R5 to A MOV R4, R7 ; invalid ; not allowed to move data between Rn s

15 Unit 3: Chapter 5, Section 5.2 Accessing Memory Using Various Addressing Modes Direct Addressing Mode The RAM has been assigned addresses 00 7FH. MOV R0, 40H ; save the contents loc 40H in R0 MOV A, 56H ; save the contents A in RAM loc 56H MOV R4, 7FH ; move the contents of RAM loc 7FH to R4 Hence, there is no # sign to designate a constant

16 Unit 3: Chapter 5, Section 5.2 Special Function Registers (SFR) A, B, PSW, DPTR. MOV 0E0H, #55 ; is the same as MOV A, #55 ; load 55H into the ACC Refer to Table 5-1 pg 114 for addresses of SFR s

17 Unit 3: Chapter 5, Section 5.2 Stack and Direct Addressing Mode Must use only direct addressing mode PUSH A ; invalid PUSH 0E0H ; this is ok PUSH R3 ; invalid PUSH 03 ; this is ok

18 Unit 3: Chapter 5, Section 5.2 Register Indirect Addressing Mode Register is used as a pointer to the data go to the register to get the address MOV B ; move the contents of RAM location whose ; address is held by R0 into A ; move the contents B to the RAM address ; held by R1 See Example 5-3, pg 116

19 Unit 3: Chapter 5, Section 5.2 Indexed Addressing Mode Indexed addressing mode is widely used in accessing data elements of look-up tables entries in the program ROM space of the MOVC (move code) instruction instead of MOV (move) MOVC ; move the contents of RAM location whose ; address is held by R0 into A B ; move the contents B to the RAM address ; held by R1 See Example 5-6, pg 118

20 Unit 3: Chapter 5, Section 5.2 Advantages and Limitation of Register Indirect Addressing Mode in the 8051 Read on your own these are limitations (pages 117) We will review this next week. Case in point are within Example 5-6

21 Unit 3: Chapter 5, Section 5.3 Bit Addressing for I/O and RAM Of the 128-byte internal RAM of the 8051, only 16 bytes are bit-addressable; the rest must be accessed in byte format. Note the addresses (20H 2FH)

22 Unit 3: Chapter 5, Section 5.3 Bit Addressing for I/O & RAM As we discussed in Chapter 4, the 8051 has four 8-bit I/O ports; P0, P1, P2, & P3. We can access either the entire 8 bits or any single bit without altering the rest. Use SETB X.Y where X is the port number (0, 1, 2, 3) and Y is the bit number (0-7) Refer to page 124, Figure 5-2 as shown.

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