Programmable Logic Devices

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1 Programmable Logic Devices Luis Entrena, Celia López, Mario García, Enrique San Millán Universidad Carlos III de Madrid

2 Outline Tecnologies for implementing programmable circuits Simple Programmable Logic Devices Complex Programmable Logic Devices: CPLD FPGA Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid,

3 Digital Circuit Implementation Dicrete logic Application Specific Integrated Circuits (ASIC) Programmable Logic Devices (PLD) Simple PROM: Programmable Read Only Memory PLA: Programmable Logic Array PAL: Programmable Array Logic GAL: Generic Array Logic Complex CPLD: Complex Programmable Logic Device FPGA: Field Programmable Gate Array Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid,

4 Tecnologies Floating gate MOS transistor (EPROM-FLASH) When transistor gate is overvoltaged, the switch is permanently open or closed, behaving as programmable connection Static RAM (SRAM) Memory can be used as combinational logic. LUTs (Look-Up Tables): 4, 5, 6 inputs. Antifuse When fused, an antifuse produces a short-circuit. Fuses offer lower resistance than diodes used in classic PLDs, and thus better performance Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid,

5 Simple Programmable Circuits PLDs (Programmable Logic Devices) Inputs+ Inverters AND Matrix OR Matrix Flip-flops (optional) Inverters+ Outputs Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid,

6 Programmable matrixes AND matrix with fixed OR Function X=A*B+A*NOT(B)+NOT(A)*NOT(B) A B A B Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid,

7 Programmable matrixes AND matrix OR matrix Types of PLD Matriz AND Matriz OR PROM Fixed Programmable PLA Programmable Programable PAL Programmable Fixed GAL Programmable Fixed PLA Simplified notation for connections Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid,

8 Kinds of PLDs PROM PAL Fixed AND matrix (address decoder) Programmable OR matrix (data) Programmable AND matrix Fixed OR matrix Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid,

9 Output blocks Combinational input-output Registered output SP CLK AR SP CLK AR D Q Q Programmable polarity output inputs outputs PAL 16 R 8 output type Name convention L: active Low H: active High P: programmable polarity R: registered Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid,

10 GAL (Generic Array Logic) PAL-like architecture, but with programmable output functions. OLMC: Output Logic Macrocell SP CLK AR Registered configuration D Q Q SP CLK AR Combinational configuration 10

11 Complex Programmable Logic Devices CPLD: Complex Programmable Logic Devices FPGA: Field Programmable Gate Array Different from simple PLDs Complex arquitecture Higher amount of logic resources CPLD & FPGA manufacturers Xilinx Altera Actel Atmel Lattice Cypress Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid,

12 CPLD: architecture Altera MAX 7000 Global signals LAB, Logic Array Blocks 1 LAB = 16 macrocells PIA, Programmable Interconnect Array Input/Output blocks Figure extracted from MAX 7000 Programmable Logic Device Family Data Sheet, version 6.6, Altera Corporation, june Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid,

13 CPLD: macrocell Altera MAX 7000 AND matrix OR matrix Global signals Programmable flip-flop Global signals Local signals Global clear Global clocks I/O pin Product selection matrix Vcc PRN D/T Q E CLRN 13 Global interconnect Local interconnect Flip-Flop input select Clock and enable select Clear select Output select

14 CPLD: interconnection matrix Global Interconnection Matrix (PIA) To logic blocks PIA inputs I/O pins LAB outputs PIA outputs LAB inputs Interconnection matrix signals Programmable switches Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid,

15 CPLD: characteristic briefing PAL structure, with registers and interconnection logic Medium capacity (up to 25,000 equivalent gates) Medium/high speed High power comsumpsion EPROM technology (reprogrammable, non volatile) Cheap Size limited by interconnection matrix ISP (In-System Programming). JTAG. Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid,

16 FPGAs Field Programmable Gate Arrays Designed to overcome CPLD size limitations, using advanced architectures High variety of logic resources Combinacional logic Sequencial logic RAM memory Clock managers Global signals Multipliers Manufacturers Xilinx Altera Actel Atmel Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid,

17 FPGA: basic logic cell A B C D Combinational Function D Q 0 1 Combinacional function + flipflop Other possibilites: 2 CF + 1 FF 2 CF + 2 FF Combinational Function: LUT (Look-Up Table): SRAM, volatile Aditional functionality: Carry logic 6 and 8 input CF Several clock and reset signals Different flip-flop configuration: level (latch), rising, edge, falling edge Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid,

18 FPGA: interconections Logic Cell Programmable interconnections Local: Plenty and fast Connect near cells Global Connect distant cells Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid,

19 General architecture FPGA (Xilinx) I/O blocks Basic elements Logic blocks I/O blocks Programmable interconnection matrixes I/O blocks Logic Blocks RAM Logic Blocks RAM Multipliers RAM Logic Blocks RAM Logic Blocks I/O blocks Advanced elements RAM memory Clock managers Multipliers I/O blocks Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid,

20 Bibliography Manufacturer webs Xilinx: Altera: Actel: Lattice: Digital Systems Fundamenta. Thomas L. Floyd. Pearson Prentice Hall Digital Systems: principles and applications, Tocci, Ronald J. Pearson Prentice Hall Dispositivos lógicos programables (PLD): diseño práctico de aplicaciones. García Iglesias, José Manuel. RaMa Luis Entrena, Celia López, Mario García, Enrique San Millán. Universidad Carlos III de Madrid,

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