Ettus Research Update

Transcription

1 Ettus Research Update Matt Ettus Ettus Research GRCon13

2 Outline 1 Introduction 2 Recent New Products 3 Third Generation

3 Introduction Who am I? Core GNU Radio contributor since 2001 Designed USRP TM in 2003 Founded Ettus Research in 2004 Ettus Research Formed to support and commercialize the USRP Acquired by National Instruments in 2010 Employs 6+ GNU Radio contributors full time Support 5+ other GNU Radio contributors Dedicated to Free Software and building the GNU Radio community Committed to our Vision of building low-cost, easy to use software radios

4 Outline 1 Introduction 2 Recent New Products 3 Third Generation

5 CBX 1.2 GHz to 6 GHz transceiver Low noise, very high dynamic range mW output power Full duplex

6 OctoClock & OctoClock-G 8-Way clock reference and time distribution 10 MHz and PPS to 8 USRPs External reference or Internal GPSDO (OctoClock-G) 1U Rackmount enclosure Ideal for Massive MIMO applications

7 B200 & B210 Low cost all-in-one solution 70 MHz to 6 GHz integrated RF Partnered with Analog Devices 2x2 MIMO (B210) Spartan 6 FPGA B200 LX75 B210 LX150 USB 3.0 interface, bus-powered 56 MHz of RF BW Full Duplex operation mW output power Optional GPS-locked oscillator (GPSDO) support B210 includes MICTOR and JTAG connectors for FPGA development

8 B210

9 Outline 1 Introduction 2 Recent New Products 3 Third Generation

10 USRP Gen 1 and 2 Gen 1 (USRP1) Got samples in and out of a computer Low cost MIMO Narrowband RF modules Gen 2 (USRP2, N2xx, B1xx, E1xx) Support for complex protocols and TDMA, precise timing Wideband RF modules High performance and bandwidth Gigabit Ethernet

11 Third Generation of USRP Easy integration of multiple processing paradigms, especially large FPGA fabric Very large bandwidth (56 to 160 MHz), very wide frequency coverage Massive MIMO scalability Three family members to start High integration and ease of use, extremely low cost B200/B210 Low power, handheld MIMO E300 High capability and extreme performance and expandability X300/X310 RF Network on Chip Architecture Common FPGA design allows for portable IP development UHD will expose more FPGA capabilities to the user, including partial reconfiguration Enable easy FPGA programming without hand written Verilog

12 X300 and X MHz RF Bandwidth 200 MS/s 14-bit ADCs, 800 MS/s 16-bit DACs Dual 10GbE with SFP+ ports SFP+ ports will also do 1 GbE and CPRI PCIe x4 (over cable) Large Kintex 7 FPGA 840/1540 DSP units (X300/X310) 1 GB onboard DDR3 Built-in GPS Disciplined OCXO, or use with external references 2x2 MIMO w/beamforming out of the box Expandable to arbitrary width MIMO Uses standard Ettus Research high dynamic range RF boards covering DC to 6 GHz

13 X300 Stream 300+ MHz of RF BW each way in 10 GbE mode, 200+ MHz in PCIe mode Very low latency, <10 us round-trip Should be good enough for ac LabVIEW FPGA capable Auxiliary digital IO for control of external amps, switches, etc. Half-width single rack unit enclosure 4x4 MIMO in 1 RU

14 X300

15 X300

16 X300 Inside

17 E300 Xilinx Zynq FPGA/Processor Dual Core ARM Cortex A9 at 800 MHz Large Programmable Logic Area 1 GB DDR3 DRAM for processor, separate 512 MB for Logic Integrated RF 70 MHz to 6 GHz integrated RF 2x2 MIMO, Full Duplex 56 MHz RF BW Full coverage RF Filterbanks Gigabit Ethernet, USB 2.0 Host GPS Synchronization Stereo audio in/out 10-axis IMU (Accelerometers, gyros, magnetometers, altimeter)

18 E300 Features Small handheld enclosure, 60mm by 120mm by 27mm Cellphone sized, but thicker Battery powered Runs a full Linux distribution maintained by key members of embedded Linux community Strong SW Ecosystem UHD Device GNU Radio support LabVIEW and LabVIEW FPGA support Develop on desktop, deploy on embedded device

19 E300 Front View

20 E300 Back View

21 E300 PCB

22 E300 Many uses Small, portable, low cost spectrum monitor Small UAVs Handheld universal communicator Wireless sensor nodes Portable signal analysis and test equipment Expandable via USB Flash drives, WiFi, Bluetooth, LTE modems, display, keyboard, etc.

23 USRP FPGA Capability Gen 1 Gen 2 Gen 3 E300 Gen 3 X310 FPGA Cyclone I Spartan 3 Zynq Kintex 7 Logic Cells 12K 53K 85K 406K Memory 26KB 252KB 560KB 3180KB Multipliers NONE! Clock Rate 64 MHz 100 MHz 200 MHz 250 MHz Total RF BW 8 MHz 50 MHz 128 MHz 640 MHz Free space none ~50% ~75% 85+%

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