Memory and Programmable Logic

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1 Digital Circuit Design and Language Memory and Programmable Logic Chang, Ik Joon Kyunghee University

2 Memory Classification based on functionality ROM : Read-Only Memory RWM : Read-Write Memory RWM NVRWM ROM Random Access Memory (RAM) Non-Random Access SRAM DRAM FIFO LIFO Register CAM EPROM EEPROM FLASH PROM

3 Memory Hierarchy Register in CPU L1 / L2 Cache : SRAM Mass Storage: HDD, Non-volatile memory

4 How to Make Programmable Logic? Fuse / Anti-Fuse SRAM-based Wiring Flash-based Wiring

5 Memory Classification based on functionality ROM : Read-Only Memory RWM : Read-Write Memory RWM NVRWM ROM Random Access Memory (RAM) Non-Random Access SRAM DRAM FIFO LIFO Register CAM EPROM EEPROM FLASH PROM

6 Storage Cell (SRAM vs. DRAM) 6T SRAM 1T DRAM SRAM : Large Size, but fast speed (compared to DRAM), no refresh operation DRAM: Small Size, but low speed (compared to SRAM), refresh operation is indispensable WL: Word-line, BL: Bit-line

7 Random Access Memory: Architecture M bits M bits N Words S 0 S 1 S 2 Word 0 Word 1 Word 2 S N-2 S N-1 Word N-2 Word N-1 Storage cell A 0 A 1 K = log 2 N S 0 Word 0 Word 1 Word 2 A K Word N-2 Word N-1 Storage cell Input-Output (M bits) Input-Output (M bits) We need a row decoder to reduce # of address pin But, Height >> Width

8 Random Access Memory: Architecture (Cont.) Row Decoder + Column Decoder

9 Random Access Memory: Hierarchical Architecture Block 0 Block i Block P 2 1 Row address Column address Block address Control circuitry Block selector Global amplifier/driver Global data bus I/O Hierarchical architecture reduces wiring Only one block is activated low power dissipation

10 Random Access Memory: read and write operation Write operation 1.Transfer the binary address of the desired word to the address lines. 2.Transfer the data bits that must be stored in memory to the data input lines. 3.Activate the write input Read operation 1.Transfer the binary address of the desired word to the address lines. 2. Activate the read input. Timing Diagram

Address bus RAS Random Access Memory: Address Multiplexing Row Address Column Address CAS RAS-CAS timing DRAM: Timing Multiplexed Addressing Address Bus Address

11 Address bus RAS Random Access Memory: Address Multiplexing Row Address Column Address CAS RAS-CAS timing DRAM: Timing Multiplexed Addressing Address Bus Address Address transition initiates memory operation SRAM: Timing Self-timed Address Multiplexing in 64K DRAM To reduce # of address pin, DRAM uses timing multiplexed addressing

12 Memory Yield and Reliability Degradation In scaled technologies, it is challenging to deliver good yield and reliability in memory

13 What Degrades Yield and Reliability? (PVT Variation)

14 What Degrades Yield and Reliability? (Many Noise Source) BL 9 BL BL BL 99 C cross SA Coupling Noise (Cross-talk) Soft-Error Noise

15 Solution: Redundancy Row / Column replacement improves memory yield

Solution: Hamming Code Parity Generation Rule Ex) 8-bit data = 11000100 Bit position 1 2 3 4 5 6 7 8 9 10 11 12 P 1 P 2 1 P 4 1 0 0 P 8 0 1 0 0 P 1 =XOR of bits(3,5,7,9,11)=0, P 2 =XOR of

16 Solution: Hamming Code Parity Generation Rule Ex) 8-bit data = Bit position P 1 P 2 1 P P P 1 =XOR of bits(3,5,7,9,11)=0, P 2 =XOR of bits(3,6,7,10,11)=0 P 4 =XOR of bits(5,6,7,12)=1, P 8 =XOR of bits(9,10,11,12)=1 C 1 =XOR of bits (1,3,5,7,9,11) C 2 =XOR of bits (2,3,6,7,10,11) C 4 =XOR of bits (4,5,6,7,12) C 8 =XOR of bits (8,9,10,11,12)

17 Bit position Solution: Hamming Code (Cont.) No Error Error in bit 1 Error in bit 5 Error in bit 6 Error in bit 1, 5 No Error Error in bit 1 Error in bit 5 Error in bit 6 Error in bit 1, 5 C 8 C 4 C 2 C Error Detect (O), Correction (O) Error Detect (O), Correction (O) Error Detect (O), Correction (O) Error Detect (X), Correction (X) Hamming Code enables single-bit error detection and correction

18 Solution: SECDED (Single Error Cor., Double Error Det.) Bit position P 13 P 13 = XOR of bits (1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12) C 1 =XOR of bits (1,3,5,7,9,11) C 2 =XOR of bits (2,3,6,7,10,11) C 4 =XOR of bits (4,5,6,7,12) C 8 =XOR of bits (8,9,10,11,12) C = C 8 +C 4 +C 2 +C 1, P = XOR of bits (1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13) If C=0 and P=0, No error occurred If C=1 and P=1, A single error occurred, which can be corrected If C=1 and P=0, A double error occurred, which is detected but cannot be corrected If C=0 and P=1 An error occurred in the P13 bit

19 Memory Classification based on functionality ROM : Read-Only Memory RWM : Read-Write Memory RWM NVRWM ROM Random Access Memory (RAM) Non-Random Access SRAM DRAM FIFO LIFO Register CAM EPROM EEPROM FLASH PROM

20 ROM (Read-Only Memory) k = 5, n = 8

21 Programming Rom According to Table 1 0

22 Read-Only Memory Cells BL BL BL 1 WL WL V DD WL BL BL BL 0 WL WL WL GND Diode ROM MOS ROM 1 MOS ROM 2

23 Read-Only Memory: MOS-NOR ROM V DD Pull-up devices WL[0] WL [1] GND WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3]

24 Read-Only Memory: Mask Programming Cell (9.5λ x 7λ) Programming using the Active Layer Only Polysilicon Metal1 GND Line Metal1 on Diffusion Vender should prepare customized mask (expensive)

25 Read-Only Memory: Contact Programming (PROM) Cell (11λ x 7λ) Programmming using the Contact Layer Only Inact fuse will be removed by high field Polysilicon Metal1 GND Line Metal1 on Diffusion

26 Memory Classification based on functionality ROM : Read-Only Memory RWM : Read-Write Memory RWM NVRWM ROM Random Access Memory (RAM) Non-Random Access SRAM DRAM FIFO LIFO Register CAM EPROM EEPROM FLASH PROM

27 Flash Memory Source Floating gate Gate Drain D t ox G n + Substrate p t ox n +_ S 20 V Device cross-section 0 V Schematic symbol 5 V 10 V 5 V 20 V -5 V 0 V V 5 V S D S D S D Tunneling injection 27 Removing programming voltage leaves charge trapped Programming results in higher V T.

28 Programmable Logic Device (PLD)

29 Programmable Logic Array Programmable AND array Programmable OR array F1=AB + AC + A BC F2= (AC + BC)

30 Programmable Array Logic PAL-With a fixed OR array and a programmable AND array. Not as flexible as the PLA (Only the AND gate are programmable.)

31 Programmable Array Logic: Example wabcd (,,, ) = (2,12,13) xabcd (,,, ) = (7,8,9,10,11,12,12,14,15) yabcd (,,, ) = (0, 2, 3, 4, 5, 6, 7,8,10,11,15) z( ABCD,,, ) = (1, 2,8,12,13,) K-Map w = ABC ' + A' B ' CD ' x = A + BCD y = A' B + CD + B ' D ' z = ABC ' + A' B ' CD ' + AC ' D ' + A' B ' C ' D = w+ ACD ' ' + ABCD ' ' '

32 Programmable Array Logic: Example (Cont.)

33 Sequential Programmable Devices Sequential (or simple) Programmable Logic Device (SPLD) Complex Programmable Logic Device (CPLD) Field Programmable Gate Array (FPGA) + Unlike combinational PLD s, includes both gates and flipflops

34 Sequential Programmable Logic Device Sequential Programmable Logic Device (SPLD) Basic Macro-cell Logic of SPLD

35 Complex Programmable Logic Device Multiple PLD s are interconnected through a programmable switch matrix

36 Field Programmable Gate Array Look up table A truth table stored in SRAM, which provides the combinational circuit functions Multiplexers / Gates / Flip-flops Example: Xilinx, Altera

37 Xilinx Spartan : Basic Architecture The loop up table of CLB can be utilized as block memory

38 Xilinx Spartan : Programmable Interconnect Point PIP = transmission gate whose is controlled by SRAM cell

39 Xilinx Spartan : I/O Blocks (IOB) IOB s are bi-directional The output buffer should be implemented as tri-gates

40 Xilinx Spartan : Distributed RAM Single-Port RAM CLB is able to form single-port / dual-port RAM dual-port RAM

41 Xilinx Spartan ΙΙ Architecture

42 Xilinx FPGA

Memory and Programmable Logic

Memory and Programmable Logic Memory units allow us to store and/or retrieve information Essentially look-up tables Good for storing data, not for function implementation Programmable logic device (PLD),