RISC Processors and Parallel Processing. Section and 3.3.6

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1 RISC Processors and Parallel Processing Section and 3.3.6

2 The Control Unit When a program is being executed it is actually the CPU receiving and executing a sequence of machine code instructions. Here lies the responsibility of the Control Unit to make sure that each instruction is handled properly. There are two methods that the CU can make sure of this

3 The Hardwired Solution One method is to have the control unit constructed as a logic circuit. This is also known as the hardwired solution. In this method the machine code instructions are directly handled by the hardware.

4 The microprogramming approach An alternative to the hardwired approach involves a ROM component that contains a series of micro instructions which is responsible for handling the control unit These microinstructions or microprogramming is also referred to as firmware. However, the choice of either methods largely depends on the type of processor.

5 The Architecture of a Processor The 'architecture' of a processor can be defined in a number of ways. And it involves the following: The instruction set The instruction format The addressing modes The registers accessible by instructions

6 The choice of instruction set is main reason behind choosing a particular architecture. One approach places emphasis on the Hardware The one places emphasis on the Software

7 The CISC Approach Complex Instruction Set Computers This is the path that major chip makers have taken for decades. The philosophy is that the chip maker provides customers (programmers) with a rich set of fairly high level instructions with which to write code. e.g. Intel, Motorola But in order to do so, they have design some very complex hardware to decode and run that complex single instruction. For example, there might be a machine code instruction that can multiply floating point numbers in one line : MULT a,b

8 Complex hardware is not relevant to the programmer of course. However there are only a limited amount of logic gates on a chip and if the decoder takes so much room the number of registers inside the CPU is reduced, which forces more data to move about in memory.

9 The MULT Command A CISC processor would come prepared with a specific instruction (we'll call it "MULT"). When executed, this instruction loads the two values into separate registers, multiplies the operands in the execution unit, and then stores the product in the appropriate register. Thus, the entire task of multiplying two numbers can be completed with one instruction: MULT 2:3, 5:2 MULT is what is known as a "complex instruction. It closely resembles a command in a higher level language

10 Advantages of CISC One of the primary advantages of this system is that the compiler has to do very little work to translate a high-level language statement into assembly. Because the length of the code is relatively short, very little RAM is required to store instructions. The emphasis is put on building complex instructions directly into the hardware.

11 The RISC Approach Reduced Instruction Set Computer A relatively simple CPU decoder with many registers at the expense of having to write more lines of code to do the same thing. The RISC approach has some significant advantages however. For example an instruction only takes a single cycle to complete compared to the multi-cycle CISC approach.

12 CISC MULT a,b RISC LOAD a from memory into register1 LOAD b from memory into a register2 PROD Register1, Register2 (multiply) STORE Answer back into memory This means more memory is needed to store the instructions, but they may actually run faster overall because each one only takes a single cycle. Furthermore, there is less movement in and out of main memory as there are more registers to hold temporary data.

13 The downside is that the complier must convert a high level language instruction into many lines of machine code.

15 Pipelining One of the major driving forces for creating RISC processors was the opportunity they would provide for efficient pipelining. Pipelining is a form of parallelism applied specifically to instruction execution.

16 The underlying principle of pipelining is that the fetch - decode-execute cycle which is in face divided into the following stages. instruction fetch (IF) instruction decode (ID) operand fetch (OF) instruction execute (IE) result write back (WB)

17 For pipelining to be implemented, the construction of the processor must have five independent units, with each handling one of the five stages identified. This explains the need for a RISC processor to have many register sets; each processor unit must have access to its own set of registers.

18 Initially only the first stage of the first instruction has entered the pipeline. At clock cycle 6 the first instruction has left the pipeline, the last stage of instruction 2 is being handled and instruction 6 has just entered. It can be seen that once under way the pipeline is handling five stages of five individual instructions. In particular, at each clock cycle the complete processing of one instruction has finished. Without the pipeline the processing time would be five times long.

19 Parallel Processing Systems One computer can have multiple processors running in parallel. SISD (Single Instruction Single Data stream) SIMD (Single Instruction Multiple Data stream) MISD (Multiple Instruction Single Data stream) MIMD (Multiple Instruction Multiple Data stream).

20 SISD (Single Instruction Single Data stream) It is the typical arrangement found in early personal computers. There is a single processor so no processor parallelism. The single data stream just means one memory i.e. Pipeline

21 SIMD (Single Instruction Multiple Data stream) It describes how an array or vector processor works. The multiple processors each have their own memory. One instruction is input and each processor executes this instruction using data available in its dedicated memory. Array Processing:- Single instruction issued by control unit and applied to a number of data sets If data sets rely on each other then parallel processing cannot be applied. If A has to be processed before B then A and B cannot be processed in parallel.

22 MISD (Multiple Instruction Single Data stream) This isn't implemented in commercial products.

23 MIMD (Multiple Instruction Multiple Data stream) These are modern personal computers which are of the symmetric multiprocessor type using identical processors. In this case, each processor executes a different individual instruction. The multiple data stream can be provided by a single memory suitably partitioned. Each processor might have a dedicated cache memory.

25 Parallel computer systems Examples of one type of multicomputer system are cal led massively parallel computers. These are the systems used by large organisations for computations involving highly complex mathematical processing. They are the latest in an evolution of what have traditionally been called 'supercomputers'. The major difference in architecture is that instead of having a bus structure to support multiple processors there is a network infrastructure to support multiple computer units. The programs running on the different computers can communicate by passing messages using the network.

26 An alternative type of multicomputer system is cluster computing, where a very large number of PCs are networked.

5 Computer Organization

5 Computer Organization 5.1 Foundations of Computer Science ã Cengage Learning Objectives After studying this chapter, the student should be able to: q List the three subsystems of a computer. q Describe