Revision: August 31, E Main Suite D Pullman, WA (509) Voice and Fax

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Exercise 7: Combinational rithmetic Circuits Revision: ugust 3, 29 25 E Main uite D Pullman, W 9963 (59) 334 636 Voice and Fax TUDENT I am submitting my own work, and I understand penalties will be

1 Exercise 7: Combinational rithmetic Circuits Revision: ugust 3, E Main uite D Pullman, W 9963 (59) Voice and Fax TUDENT I am submitting my own work, and I understand penalties will be assessed if I submit work for credit that is not my own. Print Name ign Name Estimated Work Hours ID Number Date Overall Weight GRDER # Points core Total core Weeks late djusted core djusted core: Deduct 2% from score for each week late Problem. ketch a block diagram for a magnitude comparator bit-slice circuit. Create K-maps to define the bit-slice circuit, and use them to find optimal logic equations. ketch the circuit. Contains material Digilent, Inc. 9 pages

2 Exercise #7: Combinational rithmetic Circuits Problem 2. Modify the block diagram and circuit of problem by removing the logic gates and signals that form the EQ output. ketch a circuit diagram for a 4-bit comparator that uses the modified bit slice blocks, and add a single gate to form the EQ output from the LT and GT outputs from the M (most significant bit). Comment on the differences in the new circuit (i.e., which circuit is more efficient? Which is easier to design and implement? Which might run faster? nything else?) Could you make the bit-slice modules even more efficient by leaving in the EQ logic and removing some other logic? Explain. Problem 3. Complete truth tables and K-maps for H and F circuits, using XOR patterns where appropriate. Loop minimum OP equations, and sketch the circuits (assume all inputs and outputs are active high). Half dder Cout = Cout = Cout

3 Exercise #7: Combinational rithmetic Circuits Full dder Cin Cout = Cout = Cout Problem 4. ketch a circuit for a full adder using two halfadder blocks and an OR gate. Problem 5. Complete the truth table and K-maps for a CL adder bit-slice module, and sketch a minimal OP circuit (be sure to use XOR s where appropriate!). Cin G P = G = G P = P

4 Exercise #7: Combinational rithmetic Circuits Problem 6. ketch a Carry-Propagate-Generate circuit that can form the carry-ins for a 4-bit CL. Problem 7. Design a full-subtractor bit-slice circuit. Label the inputs,, and in, and label the outputs D and out. tart by completing the subtraction examples, then complete the truth table and K-maps, and then sketch the circuit in D out in D = in out = D out

5 Exercise #7: Combinational rithmetic Circuits Problem 8: Complete the number conversions indicated. Note that all binary numbers are two s complement representations. -9 = = = - = Problem 9: Complete the four 2 s compliment arithmetic problems below, showing both the decimal and binary numbers in each case Is the above answer correct in 8 bits? Explain. Problem : ketch a circuit to convert a 4-bit binary number to its 2 s complement representation. (Hint: can you use only 3 XOR/XNOR gates and 2 ND or OR gates?).

6 Exercise #7: Combinational rithmetic Circuits Problem : Explain how the circuit structures of a ripple-carry adder circuit configured as a 2 s compliment subtractor and a ripple-borrow subtractor perform identical functions. Cin in D in D Cout out out Full dder Full ubtractor Full dder configured for subtract Problem 2: Examine several examples of addition overflow and subtraction underflow, and sketch a circuit below that can output a whenever an addition or subtraction result is incorrect due to underflow or overflow. (Hint: compare the carry in and carry out signals of the most-significant bit).

7 Exercise #7: Combinational rithmetic Circuits Problem 3. Fill in the squares below to show all signal values when and are multiplied. 2 3 P 3 P 22 P 3 P 2 P 2 P 2 P P 2 P P P P P P P P 2 P 2 P 3 P 3 P 23 P 32 P 3 P 3 P 2 P 2 P 22 P P 3 P 3 P 23 P 33 P R 7 R 6 R 5 R 4 R 3 R 2 R R Problem 4. ketch a block diagram for a 4-bit LU built from bit-slice LU circuits that can implement the functions shown in the table. Label all signals, and recall that inputs to the bit slices must come from the and input busses as well as from neighboring bit slices (and outputs must drive the F output bus as well as neighboring bit slices). To design the signals that communicate information between slices, you must understand the LU operations and the implications for information transfer (e.g., does the operation PLU require that information be transferred between slices? If so, what? Does the operation OR require that information be transferred?). Operation Code LU function PLU PLU MINU MINU XOR OR ND

8 Exercise #7: Combinational rithmetic Circuits Problem 5. In the LU example in the module it was stated that an 8: mux could be use for the F output and a 4: mux could be used for the Cout output. ketch the mux-based circuit. Problem 6. Transfer the LU operation table from the module has been reproduced below, but opcode 3 has been redefined as decrement. Complete the F and Cout table entries to define the decrement logic functions. Op Code Function F Cout PLU xor xor Cin ( and ) or (Cin and ( xor )) PLU xor Cin and Cin MINU xor xor Cin ( and ) or (Cin and ( xor ) ) MINU XOR xor OR or ND and

9 Exercise #7: Combinational rithmetic Circuits Problem 7. Write VHDL statements to define the LU's operation.

Real Digital Problem Set #6

Real Digital Problem Set #6 Real igital Problem et #6. (2 points) ketch a block diagram for a magnitude comparator bit-slice circuit. Create K-maps to define the bit-slice circuit, and use them to find optimal logic equations. ketch