COSC 243. Computer Architecture 1. COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 1
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1 COSC 243 Computer Architecture 1 COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 1
2 Overview Last Lecture Flip flops This Lecture Computers Next Lecture Instruction sets and addressing modes COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 2
3 emultiplexor Address Input A1 A0 Y3 Y2 Y1 Y0 Output A1 A0 Output Location 0 0 Y0 0 1 Y1 1 0 Y2 1 1 Y3 COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 3
4 Tristate Buffer Three states: High, Low, high-impedance The output is either the input () or high-impedance E Y Y Input () Output (Y) 0 0 Z E 1 0 Z Output Enable (E) COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 4
5 Flip Flop Input Output Write Enable (clock) >C COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 5
6 Memory (Write) Address A1 A0 ata 1 0 Y3 >C >C emux Y2 >C >C Write Enable Y1 >C >C Y0 >C >C COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 6
7 Memory (Read) ata 10 Address A1 A0 Y3 >C >C emux Y2 >C >C Output Enable Y1 >C >C Y0 >C >C COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 7
8 Memory (Read / Write) Address (A) ata In () Control (OE / WE) Memory ata Out () COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 8
9 Bus The wide arrows represent several wires We re going to call these arrows buses The computer has: A data bus and (previous slide) multiplexed together An address bus Which memory cells to use A control bus Output enable and write enable (previous slide) + others COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 9
10 Bus Used to communicate between parts of the computer Only one transmitter at a time Only the addressed device can respond Because the tristate buffers disconnect the other devices 2 levels of busses Internal to chip External between chips COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 10
11 Memory Flip flops are grouped into bytes (or larger) Each byte has a unique address To write Present the address and the data Tell chip to write To read Present the address Tell the chip to read Look at the data Memory size is dependant on address bus width 2 n bytes for n-lines on the address bus 2 8 =256B, 2 16 =64KB, 2 32 =4GB, 2 64 =16EB COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 11
12 AN E1 1 E0 0 ata In (E) ata In () Output Enable Output Enable 1 0 ata Out () COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 12
13 A (Plus) E Input Output E C C Half Adder Input Output E C 0 E C 0 C Full Adder COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture C
14 A (Plus) ata In (E) ata In () E1 1 E0 0 C1 1-bit Full Adder C0 1-bit Half Adder Output Enable + Output Enable 1 0 Ripple Carry Adder ata Out () COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 14
15 Load ata In () 1 0 Output Enable Output Enable Load 1 0 ata Out () COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 15
16 Arithmetic Logic Unit (ALU) ata In () ata In (E) + Load ata Out () COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 16
17 Arithmetic Logic Unit (ALU) Performs arithmetic operations addition, subtraction, etc. Performs logical operations AN, OR, SHIFT, etc. Subunits Adder (and subtraction) Logical tests (if, >0, <0, =0, <=0, etc.) Logical operations (AN, OR, XOR, etc.) Shifting Comparison (done by subtraction) Multiplication and division COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 17
18 Control Unit ata In () ata In (E) OE OE + OE Load Command X1 X0 ata Out () High emux Y3 Y2 Y1 Y0 Instruction X1 X0 COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 18
19 Control Unit Coordinates the operation of the computer Generates control signals Connect registers to the bus Control the function of the ALU Provides timing signals to the system The actions of the control unit are associated with the decoding and execution of instructions See fetch and execute cycles, later COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 19
20 Registers ata In () ata In (E) OE OE + OE Load Command X1 X0 OE Register WE ata Out () Clock emux Y3 Y2 Y1 Y0 Instruction X1 X0 COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 20
21 Registers Registers are memory cells with names Hold data, instructions, or other items Various sizes (typically: 8, 16, 32, or 64 bits) Program counter (PC) and memory address registers must be same width as address bus Registers which hold data must be same width as memory words The accumulator is a special register Source of one of the operands estination of the result COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 21
22 Registers The Status Flags is a special register Individual bits store information about results of operations Result is zero Carry Overflow Result is negative COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 22
23 CPU ata In () ata In (E) ata Out () Load OE OE OE + OE Load Command X1 X0 OE Register WE ata Out () Clock emux Y3 Y2 Y1 Y0 Instruction X1 X0 COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 23
24 Computer! Address (A) Output Enable Write Enable Memory ata Out () ata In () ata Out () ata In () CPU Control Bus Command (X) Instruction X1 X0 A1 A0 COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 24
25 Instructions Instructions are bit patterns Can be split into a number of fields One field specifies the operation to be executed Other fields specify the address in memory (or registers) of operands and where to place the result COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 25
26 Stored Program Computer Address (A) Output Enable Write Enable Memory ata In () ata Out () ata Out () ata In () CPU PC IR Control Bus Command (X) Instruction X1 X0 A1 A0 COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 26
27 Von Neumann Architecture Three key concepts: ata and instructions are stored in a single read-write memory Contents of memory are addressable by location, without regard to the type of data contained Execution occurs in a sequential fashion, unless explicitly altered, from one instruction to the next Programs and ata are the same thing And so its possible to write source code (data) and compile them into executables (programs) that can be loaded as data and then executed as programs COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 27
28 MOS Technology 6502 CPU COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 28
29 6502 Transistors CPU Year Transistors ,510 8-Core Xeon ,300,000, core AM Epyc ,200,000, COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 29
30 Central Processing Unit COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 30
31 Central Processing Unit Arithmetic and Logic Unit Complementor Shifter Status Flags Accumulator Arithmetic and Boolean Logic Internal CPU Bus Addressable0 Addressablen Program Counter Stack Pointer IR MAR MBR Registers Control Unit Control Paths Address Bus ata Bus Control Bus Internal Structure of a CPU COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 31
32 Bus COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 32
33 Bus COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 33
34 6502 Block iagrams COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 34
35 6502 Pinout COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 35
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