SYLLABUS. osmania university CHAPTER - 1 : REGISTER TRANSFER LANGUAGE AND MICRO OPERATION CHAPTER - 2 : BASIC COMPUTER
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1 Contents i SYLLABUS osmania university UNIT - I CHAPTER - 1 : REGISTER TRANSFER LANGUAGE AND MICRO OPERATION Difference between Computer Organization and Architecture, RTL Notation, Common Bus System using Multiplexer and Tri-state Buffers. Micro-operations : Data Transfer, Arithmetic, Logical and Shift. CHAPTER - 2 : BASIC COMPUTER ORGANIZATION AND DESIGN Computer Registers, Instruction and Interrupt Cycle and Design of Basic Computer, Instruction Formats and Addressing Modes. UNIT - II CHAPTER - 3 : COMPUTER ARITHMETIC Fixed and Floating Point Numbers : Adders : Binary Adder, BCD Adder, Carry Look Ahead Adder, Twos Complement Adder/Subtractor, Multiplication : Booth s Algorithms, its HDL Description and Array Multiplier. Division : Restoring and Non-restoring Algorithms and their HDL Descriptions and Barrel Shifter. UNIT - III CHAPTER - 4 : CONTROL UNIT DESIGN Significance of Control Unit, Hardwired Control Unit Design Approach (Classical and One-Hot Methods), Case Studies : CPU, Micro-programmed Control Unit Approach : Basic Concept, Micro-program Sequencer.
2 ii Contents UNIT - IV CHAPTER - 5 : INPUT OUTPUT AND MEMORY ORGANIZATION Input-output Interface, Modes of Transfer : Programmed I/O, Interrupt I/O and DMA, Priority Interrupt, Input-output Processor (IOP) : CPU-IOP Communication. CHAPTER - 6 : MEMORY ORGANIZATION Memory Hierarchy, Main Memory : ROM, MROM, EPROM, EEROM, Flash Memory, RAM Types, Associative Memory (CAM), Cache Memory, Address Mapping Techniques, Replacement Policies, Virtual Memory. UNIT - V CHAPTER - 7 : ADVANCES ANCES IN COMPUTER ORGANIZATION RISC, CISC, Parallel Processing : Pipeline-Arithmetic and Instruction, Pipeline Conflicts, Flyn s Classification, VLIW Architecture. Processor Performance Enhancement Strategies : Overlap, Scalar, Super-Scalar, Super-Pipeline, Instruction Level Parallelism (ILP).
3 Contents iii computer organization and architecture FOR b.e. (o.u) Iii year i semester (ELECTRONICS AND COMMUNICATION ENGINEERING) CONTENTS UNIT - I [CH. H. - 1] ] [REGISTER TRANSFER LANGUAGE AND MICRO OPERATION] INTRODUCTION Computer Organization Computer Architecture Difference between Computer Organization and Architecture EVOL OLUTION AND COMPUTER GENERATIONS First Generation Computers ( ) Second Generation Computers ( ) Third Generation Computers ( ) Fourth Generation Computers ( ) Fifth Generation Computers (1985 Till Date) DATA A REPRESENTATION TION Number Systems Decimal Number System Binary Number System Octal Number System Hexadecimal Number System
4 iv Contents Conversion of Radix r System to Decimal System Conversion of Decimal System to Radix-r System Octal and Hexadecimal Numbers Binary to Octal Conversion Binary to Hexadecimal Conversion Octal to Binary Conversion Octal to Hexadecimal Conversion Hexadecimal to Binary Conversion Hexadecimal to Octal Conversion Decimal Representation Complements (REGISTER TRANSFER LANGUAGE) RTL Register Transfer Logic Statements for Branching REGISTER TRANSFER Block Diagram for Registers Implementation of Register Transfer COMMON BUS SYSTEM Common Bus System using Multiplexer Common Bus System Using Triri-State (Three-State Buffer) Memory Transfer MICROOPERATIONS Data Transfer Register Transfer Microoperations Bus and Memory Transfer ransfer Arithmetic Micro Operation Binary Subtractor Binary Adder/Subtractor Arithmetic Circuit
5 Contents v Logic Micro Operations Special Symbols List of Logic Microoperations Hardware Implementation of Logic Microoperations Applications of Logic Microoperations Shift Micro Operations Hardware Implementation Short Questions and Answers Expected University Questions with Solutions UNIT - I [CH. - 2] ] [BASIC COMPUTER ORGANIZATION AND DESIGN] INTRODUCTION INSTRUCTION CODES Stored Program Organization Direct and Indirect Address COMPUTER INSTRUCTIONS Common Bus System COMPUTER INSTRUCTIONS INSTRUCTION CYCLE Fetch and Decode Determine the Type of Instruction INPUT,, OUTPUT AND INTERRUPT Input-Output Configuration Input-Output Instructions Program Interrupt Interrupt Cycle DESIGN OF BASIC COMPUTER Control Logic Gates Control of Registers and Memory
6 vi Contents Control of Single Flip-Flops Control of Common Bus INSTRUCTION FORMATS Four Types of Address Instructions RISC Instructions ADDRESSING MODES Implied or Implicit Mode Immediate Mode Register Direct Mode Register Indirect Mode Direct Address Mode Indirect Address Mode Displacement Addressing Relative Addressing Base Register Addressing Indexed Addressing Autoincrement or Autodecrement Addressing Stack Addressing Numerical Example to Illustrate Addressing Modes Comparison of Addressing Modes Short Questions and Answers Expected University Questions with Solutions UNIT - II [CH. - 3] ] [COMPUTER ARITHMETIC] INTRODUCTION FIXED POINT REPRESENTATION TION OF NUMBERS Integer Representation Signed Magnitude Representation Signed-1 s Complement Representation Signed-2 s Complement Representation
7 Contents vii Arithmetic Addition Arithmetic Subtraction Arithmetic Overflow Decimal Fixed Point Representation FLOATING POINT REPRESENTATION TION OF NUMBERS Floating Point Representation of Decimal Number Floating Point Representation of Binary Numbers Floating Point Representation with IEEE Standards Single Precision (32-Bit) Format Double Precision (64-bit) Format Range and Precision BINARY ADDER BCD ADDER BCD Subtraction s Complement s Complement Subtraction s Complement Subtraction CARRY LOOK AHEAD ADDER TWO S S COMPLEMENT OF ADDER AND SUBTRACT CTOR OR MULTIPLICA TIPLICATION TION Booth s s Multiplication Algorithm (2 s Complement Data) ARRAY Y MULTIPLIER TIPLIER DIVISION Restoring Division Nonresotring Division Comparison between Restoring and Non-restoring Division Algorithm BARREL SHIFTER Short Questions and Answers Expected University Questions with Solutions
8 viii Contents UNIT - III [CH. H. - 4] ] [CONTROL UNIT DESIGN] TERMINOLOGY SIGNIFICANCE OF CONTROL UNIT HARDWIRED CONTROL UNIT DESIGN APPROACH State Table Method (or) Classical Method Greatest Common (GCD) Processor One Hot Method CASE STUDY : CPU CASE STUDY : MICRO-PROGRAMMED CONTROL UNIT APPROACH Basic Concepts Control Unit Organisation Advantages of Microprogrammed Control Disadvantages of Microprogrammed Control Alternative to Increase Speed in Microprogramming Microinstruction Sequencing Microinstruction Addressing and Timing CASE STUDY : MICRO-PROGRAM SEQUENCER Short Questions and Answers Expected University Questions with Solutions UNIT - IV [CH. - 5] ] [INPUT OUTPUT AND MEMORY ORGANIZATION] INTRODUCTION INPUT-OUTPUT INTERFACE CE I/O Bus and Interface Modules I/O versus Memory Bus Isolated versus Memory-Mapped I/O Example of I/O Interface
9 Contents ix 5.3 MODES OF TRANSFER Programmed I/O Interrupt Driven I/O Direct Memory Access (or) DMA Example of Data Transfer in Programmed I/O PRIORITY INTERRUPT Daisy Chaining Priority Parallel Priority Interrupt INPUT-OUTPUT PROCESSOR (IOP) I/O Processing CPU-IOP Communication IBM 370 I/O Channel Intel 8089 IOP Short Questions and Answers Expected University Questions with Solutions UNIT - IV [CH. - 6] ] [MEMORY ORGANIZATION] INTRODUCTION BASIC CONCEPTS MEMORY HIERARCHY MAIN MEMORY ROM ROM and Its Organisation PROM (Programmable Read Only Memory) EPROM (Erasable Programmable Read Only Memory) EEPROM (Electrical Erasable Programmable Read Only Memory) FLASH MEMORY RAM AND ITS TYPES
10 x Contents Static RAM TTL RAM Cell MOS Static RAM Cell Organisation using Single Decoder Organisation using Two Dimensional Decoding Dynamic RAM Write Operation Read Operation Refresh Operation DRAM Memory Organisation Comparison between SRAM and DRAM ASSOCIATIVE MEMORY Hardware Organization Match Logic Read and Write Logic Read Operation Write Operation CACHE MEMORY Mapping Functions Direct Mapping Associative Mapping Set Associative Mapping Writing Info Cache Cache Initialization REPLACEMENT POLICIES VIRTUAL MEMORY Short Questions and Answers Expected University Questions with Solutions
11 Contents xi UNIT - V [CH. H. - 7] ] [ADVANCES IN COMPUTER ORGANIZATION] CISC AND RISC Characteristics/Features of CISC Characteristics/Features of RISC Comparison of RISC and CISC Architecture Overlapped Register Windows PARALLEL PROCESSING Flynn s Classification PIPELINE Arithmetic Pipeline Instruction Pipeline Four Segment Instruction Pipeline Instruction Pipeline Conflicts VLIW ARCHITECTURE PROCESSOR PERFORMANCE ENHANCEMENT STRATEGIES TEGIES Overlap Scalar SUPER-SCALAR Requirements and Essential Components Multipipeline Scheduling In-Order Issue with In-Order Completion In-Order Issue with Out-of-Order Completion Out-of-Order Issue with Out-of-Order Completion Superscalar Performance erformance Superscalar IBM RISC/System (RS) Intel
12 xii Contents Motorola Superscalar MIPS R Superscalar PA-RISC SUPER PIPELINE Superpipeline Performance erformance Super Pipelined Super Scalar Processor Superpipelined Superscalar Performance DEC ALPHA 21 X 64 Superpipeline Superscalar Processors INSTRUCTION LEVEL PARALLELISM (ILP) Dependences between Instructions Data Dependences Name Dependences Control Dependences Data Hazards Read After Write (RAW) Hazard Write rite-after After-Write rite (WAW) W) Hazard Write-After-Read (WAR) Hazard Short Questions and Answers Expected University Questions with Solutions
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