Atlys (Xilinx Spartan-6 LX45)

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1 Boards & FPGA Systems and and Robotics how to use them 1

2 Atlys (Xilinx Spartan-6 LX45) Medium capacity Video in/out (both DVI) Audio AC97 codec 220 US$ (academic) Gbit Ethernet 128Mbyte DDR2 memory USB ports for COM and config. Free CAD tools (webpack) be careful with the u-usb connections (a bit fragile) 2

3 Atlys Stereo Camera Module Two independent Aptina MT9D112 2-Mpixel CMOS sensors 1600x1200 maximum resolution at 15 FPS 10-bit raw color depth 100 US$ 3

4 ZedBoard (Xilinx Zynq) Dual-core ARM Cortex A9 Memory: 512 MB DDR3 256 Mb Quad-SPI Flash 4 GB SD card USB-JTAG Programming 10/100/1000 Ethernet USB OTG 2.0 USB-UART HDMI, 8-bit VGA 128 x 32 OLED Free programming tools 320 US$ (academic)

5 ZYBO (Xilinx Zynq) (available mid. Feb.) Dual-core ARM Cortex A9 Smaller FPGA than on ZedBoard Raspberry Pi form factor (Ideal for robotics) 512 MB DDR3 128 Mb Quad-SPI Flash 4 usd card USB-JTAG Programming HDMI (input or output) Free programming tools 125 US$ (academic) 5

6 XUPV (Xilinx Virtex-5) A bit old, but large capacity 30-day trial license or University license server 800 US$ (academic) 2200 US$ ordinary! Lots of peripherals 6

7 What you should know about FPGA Boards All boards have their own issues Xilinx boards do often not come with nice reference designs (more a construction kit rather than an out-of-the box solution) Go for one that is popular (large user community) A larger FPGA is not a better FPGA à longer tool run-times (large designs need hours to compile and place&route, some even a week!) à think what you need (today and tomorrow) Good alternative: Altera Altera typically has better tools and boards (and value) also large user community. There are more FPGA vendors: Lattice, Actel (very low power) 7

8 Design Tools Xilinx Download Website: You have to register (Xilinx is not spamming you) Latest versions seam to be stable (don t change a working tool-chain; also tools have thier issues) Xilinx ISE: traditional RTL (register transfer level) design tool) Vivado: C-to-gates (High-Level-Synthesis) Includes simulator Windows and Linux available (Windows runs a bit smoother) 8

9 Design Tools: Licensing Free Webpack version (supports Spartan-6 (Atlys) and Zynq) see following link for supported devices. Alternatively: 30 day trial or University license server (use VPN from home): Windows: set set Linux export export 9

10 Design Tools: Install License If you use the 30 day trial, start the following for installing the license: Use Load License by browsing to the license file you have to get from Xilinx. You get this here: (needs the registration you used for downloading the tool) 10

11 Design Tools: Starting ISE I use the following batch-file to set the environment for different ISE versions: set XILINX=C:\Xilinx\%1\ISE_DS\ISE set PATH=%XILINX%\bin\nt; set LM_LICENSE_FILE=2100@cadmaster.cs.man.ac.uk set XILINXD_LICENSE_FILE=2100@cadmaster.cs.man.ac.uk If you store this in setise.bat, you can set the environment for ISE 14.4 with setise 14.4 you then start ise from the command line: ise Use File à Open Project for opening the provided project for your board 11

12 Design Tools: Compiling a Project Open your project (see last slide) and apply (from the text menu) the command: Project à Cleanup Project Files Select in the design Hierarchy your top-level module (which has the interface to the outside world). After this, double click on Generate Programming File in the Process window. This calls all processes and the result is a configuration bitfile (static.bit) Processes can be triggered one after the other A double-click in the Hierarchy opens the corresponding source file 12

13 Bitstream Download to the Board For Atlys, start the Adept tool from Digilent: If your Atlys board is connected, It should get detected by Adept and you will be able to browse to your bitfile and program the board. You can download Adept (for Windows and Linux) here: 13

14 Bitstream Download to the Board For the ZedBoard start IPACT: The tools comes with ISE, but is quite cumbersome to use. Say No to the following: (if you are asked) You want to create a new project 14

15 Bitstream Download to the Board If this dialog comes, select create new project: If this dialog comes, select yes to create a new project Select JTAG configuration: 15

16 Bitstream Download to the Board Use Bypass for the first file (we are not using the ARM core): 16

17 Bitstream Download to the Board For the second file, browse to your configuration bitstream: 17

18 Bitstream Download to the Board Use Cancel for the Programming Properties: Use right mouse button on the tight FPGA icon and select Program This should download the bitstream to the FPGA The analog VGA output is showing a simple Mandelbrot set demo 18

19 Skin-Color Detection Example skin color detection Algorithm: Message: >20 instr. per pixel >1 50 MHz pixel clock >2 100 MHz pixel clock >>200 GOPS device potential (Xilinx Spartan-6 LX45 ~50 USD) All video processing modules are partial! 19

20 Skin-Color Detection Hardware design languages (HDL): Verilog and VHDL Algorithm: 20

21 FPGA and Steppermotors Example: Microstepping for stepper motors using PWM (pulse-width modulation) 21

22 FPGA and Robotics Example: Microstepping for stepper motors using PWM 22

23 FPGA and Robotics Example: machine vision Object detection Feature extraction Position tracking 3D Motion capturing Human-machine interfaces Observation Cameras are cheap but incredible powerful sensors 23

24 CPU Design Implementation of your own MIPS CPU 24

25 PR example: Custom instructions Fine-grained communication architecture for flexible instruction placement OP_A instruction result register file OP_B conf. instr. conf. instr. OP_A OP_B instruction register file Identical routing for OPs and results in each slot Both operands are available in each slot (end point & middle access) Commutative instructions (e.g., A > B) Implementation alternative Bitstream manipulation B A 25

26 PR example: Custom instructions instruction slices slots bitstream latency (max/av) 64-bit XOR gate 19 (40%) KB 7.04 / 5.95 ns CCITT CRC 33 (34%) KB 5.32 / 3.98 ns sat. add/sub 70 (73%) KB 9.89 / 7.81 ns barrel shifter 90 (94%) KB / 7.88 ns '1'-bit counter 214 (89%) KB / 8.25 ns mask & permute 16 (33%) KB 5.94 / 4.05 ns Direct connection (no proxy logic ) Swapping of instructions: Dedicated load commands Triggered by a trap handler 26

27 Any Questions? 27

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