Intel I/O Processor Chipset with Intel XScale Microarchitecture

Transcription

1 Intel I/O Processor Chipset with Intel XScale Microarchitecture Initialization Considerations White Paper July 2001 Order Number:

2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel I/O Processor Chipset with Intel XScale Microarchitecture may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling or by visiting Intel's website at Copyright Intel Corporation, 2001 AlertVIEW, i960, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, Commerce Cart, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, GatherRound, i386, i486, icat, icomp, Insight960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel ChatPad, Intel Create&Share, Intel Dot.Station, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetStructure, Intel Play, Intel Play logo, Intel Pocket Concert, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel WebOutfitter, Intel Xeon, Intel XScale, Itanium, JobAnalyst, LANDesk, LanRover, MCS, MMX, MMX logo, NetPort, NetportExpress, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare, RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In, TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other brands and names are the property of their respective owners. Initialization Considerations White Paper

3 Contents 1.0 Summary References Related Documents...6 Figures Tables None Listed In This Document 1 Partial Changes from Intel i960 RM/RN I/O Processor to Intel I/O Processor...5 Initialization Considerations White Paper 3

4 This Page Intentionally Left Blank 4 Initialization Considerations White Paper

5 1.0 Summary This paper describes some of the changes that have been made on the Intel I/O processor chipset with Intel XScale microarchitecture (80310) (ARM architecture compliant) relative to the Intel i960 RM/RN I/O processor (i960 RM/RN or 80960RM/RN). These changes when not taken into considerations may cause the to malfunction. For a complete list of changes made to the please refer to the Migrating from Intel 80960RM/RN I/O Processor to Intel I/O Processor Chipset with Intel XScale Microarchitecture Application Note (273419). These changes may have an impact for those trying to port an existing 80960RM/RN initialization code to the Flash Chip Enable Signals The Intel I/O companion chip (80312) provides two chip enable signals (RCE1# and RCE0#). On the 80960RM/RN RCE0# is used to access Flash (boot device) since the 80960RM/RN processor vectors to address 0xFEFFFF30 after reset. When using the 80310, RCE1# must be used to access Flash since the Intel processor (80200) vectors to address 0x after reset. Table 1. Flash Bank Registers after Reset Register Name Address Reset Value FEBR0 - Flash Bank Base Address Register 0 154CH FE80H FEBR1 - Flash Bank Base Address Register H H FBSR0 - Flash Bank Size Register H 8H FBSR1 - Flash Bank Size Register H 8H FWSR0 - Flash Wait States Register 0 155CH 77H FWSR0 - Flash Wait States Register H 77H 3.0 Intel I/O Companion Chip Memory-Mapped Registers (MMRs) The MMRs are located between address 1000H-2000H. Since Flash must reside starting at address H, this means the Flash device overlaps onto the MMR space. Care must be taken when designing the firmware for that resides in the Flash. The firmware must not be mapped in the address range H. Initialization Considerations White Paper 5

6 4.0 Intel Processor Core Clock The Intel core and bus run on independent clock sources. For example, the core clock can be sourced from an oscillator whereas the bus clock is driven by the Although the core and bus run asynchronously, the ratio of the clock speeds has to be at least 3:1 for core versus bus speed. Since the drives a 100 MHz clock, the core must be made to run at a minimum of 300 MHz. When a 66 MHz oscillator is used to drive the core clock, the PLLCFG signal of the must be pulled high. This yields a core speed of 400 MHz which a 4:1 ratio. Table 2. Intel Processor Core Clock Setup PLLCFG Signal Multiplier Core Speed (MHz) Pulled Low x3 200 Pulled High x ATU Outbound Direct Addressing Window The ATU (Address Translation Unit) Outbound Direct Addressing Window is located between address 2000H H. This window clearly overlaps the Flash address space. The direct addressing window is disabled after reset. Therefore, the direct addressing window should not be in the way, and access within 0x2-8000H is claimed by the Flash device. When the application needs to use the direct addressing window and the Flash. The Flash device can be relocated by changing the base address in the FEBR1 register. This is assuming execution is transferred to SDRAM at this point. By relocating the Flash device, the user has to ensure that the exception vectors are also mapped properly. For example, the vectors are originally located starting at physical address H. Therefore by relocating the Flash, these vectors would not be present at physical address H any longer. The also provides an option of relocating the exception vectors to FFFFH. The user can map SDRAM in the upper part of the address space and have the vectors relocated in SDRAM at address FFFFH. Flash can also be relocated in the upper part of memory in such a way that address FFFFH would access Flash. Note that once the Memory Management Unit (MMU) is turned on, the fetches the vectors using virtual address (H CH) or (FFFF - FFFF001CH). This means that the vectors can be located anywhere in physically as long as the MMU is setup to properly translate the virtual address to the physical address. 6 Initialization Considerations White Paper

7 6.0 Programming Flash via the ATU Figure 1. A convenient way of programming Flash is by using the host processor to access the Flash via the ATU. This is normally done by placing the in mode 0. See the table below for various modes. Although the default inbound ATU window size is 16 MBytes, the first 4 KBytes are reserved for the Messaging Unit (MU). The first 4 Kbyte of PCI addresses are not translated, they access MU registers directly. Also the Flash Bank Base Address Register 1 (FEBR1) defaults to H after reset. Therefore, by simply programming the Primary Inbound ATU Translate Value Register (PIATVR) with H would not work because the first 4 KBytes of the Flash is not accessible because the MU is in the way. The MMRs (1000H H) also overlaps the Flash. The following example explains how the various registers can be setup to be able to access the entire Flash. Here are the assumptions: 8 MBytes Flash device ATU window size 16 MBytes Program the PIATVR register with A000H. This value can be anywhere in the address spaceaslongasitisempty. Program the FEBR1 register with A080H, the granularity of the Flash device. For example, the Flash is mapped in the second 8 MBytes of the ATU window. By setting up the Flash in the second 8 Mbytes of the ATU window bypasses the MU registers. ATU Window Layout for Accessing Flash PIATVR A000_H A000 H A000_0FFF ATU Window MU FEBR1 A080_H 16 MBytes A07F_FFFF A080_ Flash 8MBytes A0FF_FFFF Initialization Considerations White Paper 7

8 Table 3. Intel I/O Companion Chip Initialization Modes Initialization Mode RST_MODE# RETRY Primary PCI Interface Action Intel Core Action Next Step Mode 0 (Recommended for Motherboard Usage Only) 0 0 Accepts Transactions Held in Reset Host processor must clear the Core Processor Reset bit in the EBCR to allow the Core Processor to execute the initialization code. Mode 1 (Not Recommended) 0 1 Intel does not recommend the useofmode1. Mode 2 (Not Recommended) 1 0 Intel does not recommend the useofmode2. Mode 3 (default) 1 1 Retries all Configuration Cycle Transactions Initializes/ Executes Intel I/O Processor Initialization Code The Core Processor must clear the Configuration Cycle Retry bit in the EBCR to allow the Primary PCI Interface to accept configuration transactions. 8 Initialization Considerations White Paper

9 Table 4. Partial Changes from Intel i960 RM/RN I/O Processor to Intel I/O Processor Chipset Register Name Address Description RFR - Refresh Frequency Register SDCR.2 - SDRAM Control Register SBR0[2:0] - SDRAM Boundary Register SBR1[2:0] - SDRAM Boundary Register PIRSR[3:0] - PCI Interrupt Routing Select Register ECCR.3 - ECC Control Register 1568H 1504H 150CH 1510H 1050H 1534H The default value has changed from 300H on the 80960RM/RN to 000h on the A value other then 000H must be programmed into this register to cause refresh cycles. Onthe80960RM/RNthisbitcanbeusedtodeterminetheSDRAM data bus width. 0= 32bits 1= 64bits On the Intel I/O Processor (80303), this bit is a reserved bit because only 72-bit (ECC always on) data bus width is supported. When this bit is read it may return a '0'. On the 80960RM/RN, bits SBR0[5:0] are used to program the upper boundary of SDRAM bank 0. On the 80303, bits SBR0[2:0] are now reserved. Instead, bits SBR0[7:3] are used to program the upper limit. When this register is not properly programmed, the Memory Controller Unit (MCU) does not respond to read and write requests. On the 80960RM/RN, bits SBR1[5:0] are used to program the upper boundary of SDRAM bank 0. On the 80303, bits SBR1[2:0] are now reserved. Instead, bits SBR1[7:3] are used to program the upper limit. When this register is not properly programmed, the Memory Controller Unit (MCU) does not respond to read and write requests. On the 80960RM/RN, after reset the secondary PCI interrupts (S_INTx#) are routed to the core. On the 80303, after reset the secondary PCI interrupts (S_INTx#) are routed to the primary PCI interrupts (P_INTx#). The user must ensure the secondary interrupts are steered correctly. On the 80960RM/RN, this bit can be used to turn ECC either on or off. On the this bit is reserved since ECC is always turned on. The user must make sure that the SDRAM entries are initialized by writing 64-bit words using stl instruction. This generates and write the correct ECC code into the SDRAM entries. Initialization Considerations White Paper 9

10 7.0 References 7.1 Related Documents Migrating from Intel 80960RM/RN I/O Processor to Intel I/O Processor Chipset with Intel XScale Microarchitecture Application Note (273419). 10 Initialization Considerations White Paper