MICROPROCESSOR Architecture, Programming and Interfacing SUNIL MATHUR. Assistant Professor Maharaja Agrasen Institute of Technology Delhi

Size: px

Start display at page:

Download "MICROPROCESSOR Architecture, Programming and Interfacing SUNIL MATHUR. Assistant Professor Maharaja Agrasen Institute of Technology Delhi"

Maximilian Harper
5 years ago
Views:

2 MICROPROCESSOR 8086 Architecture, Programming and Interfacing SUNIL MATHUR Assistant Professor Maharaja Agrasen Institute of Technology Delhi New Delhi

3 MICROPROCESSOR 8086: Architecture, Programming and Interfacing Sunil Mathur 2011 by PHI Learning Private Limited, New Delhi. All rights reserved. No part of this book may be reproduced in any form, by mimeograph or any other means, without permission in writing from the publisher. ISBN The export rights of this book are vested solely with the publisher. Published by Asoke K. Ghosh, PHI Learning Private Limited, M-97, Connaught Circus, New Delhi and Printed by Rajkamal Electric Press, Plot No. 2, Phase IV, HSIDC, Kundli , Sonepat, Haryana.

4 To My Students

5 Contents Preface Acknowledgements xix xxiii PART I 1. Architecture and Organization of Microprocessors and Microcomputers Introduction Computer Languages Low-level Language Machine Language Assembly Language High-level Language Microprocessor Arithmetic and Logic Unit Register Unit Control Unit Microprocessor Operations Microprocessor Initiated Operations Internal Data Operations Peripheral or Externally Initiated Operations Functional Description Internal Architecture of Register Unit Control Unit Arithmetic Logic Unit System Bus of v

6 vi Contents Pin Description Group 1: Power Supply and Frequency Signals Group 2: Higher Order Address Bus A 8 A Group 3: Multiplexed Address/Data Bus AD 0 AD Group 4: Control and Status Signals Group 5: Serial IO Signal Group 6: Externally or Peripheral Initiated Signals Microprocessor System How a Program is Executed 19 Exercises 20 Multiple Choice Questions 20 Descriptive Questions Introduction to Introduction The 8086 Microprocessor Bus Interface Unit (BIU) Execution Unit Pin Configuration of Pin Details of 8086 Common to Both Minimum and Maximum Mode Pin Details of 8086 (Minimum Mode) Pin Details of 8086 S (Maximum Mode) Memory Organization of Microprocessor Exercises 43 Multiple Choice Questions 43 Descriptive Questions Based System Introduction Minimum Mode Configuration Demultiplexing of the Multiplexed Buses Transceiver Generation of Control Signals Clock Generator 8284 and Driver Interfacing of Memory in Minimum Mode Maximum Mode Configuration of Bus Controller Memory Interface of a Maximum-Mode 8086 System Bus Cycles of Minimum Mode Bus Cycles Maximum Mode Bus Cycles of 8086 System Bus Request and Bus Grant Timings in Minimum and Maximum Mode Systems 69

7 Contents vii Exercises 70 Multiple Choice Questions 70 Descriptive Questions Instructions Set of Introduction Addressing Modes of Data Addressing Modes Address Addressing Modes Instruction Format Instruction Templates Instruction Set of Data Transfer Instructions Arithmetic Instructions Logical Instructions Shift and Rotate Instructions String Instructions Adjustment Instructions Flag Related Instructions Control Transfer Instructions Processor-control Instructions 121 Exercises 128 Multiple Choice Questions 128 Descriptive Questions Assembler Directives Introduction Assembly Language Assembly Language Program Development Tools Editor Assembler Linker Loader Debugger TASM Assembler MASM Assembler Assembler Directives Data Defining Assembler Directives Segment Defining Directives Combining Segments Managing Large Programs Processor Directives Initialization of Program Memory Models 158 Exercises 159 Multiple Choice Questions 159 Descriptive Questions 162

8 viii Contents 6. Programming of Introduction Flowchart Guidelines for Drawing a Flowchart Advantages of Using Flowcharts Limitations of Using Flowcharts Programming Steps Solved Examples 167 Exercises 187 Multiple Choice Questions 187 Descriptive Questions Interrupts of Introduction Advantages of Interrupts Interrupt Systems Single Line or Single Level Interrupt System Multilevel or Multiline Interrupt System Classification of Interrupts Interrupts of Interrupt Pointer Table Dedicated Interrupts of Software Interrupts of Priority of Interrupts Programmable Interrupt Controller (PIC) 8259A Block Diagram and Functional Description of 8259A Pin Diagram and Pin Description Interrupt Sequence Programming of 8259A Initialization Initialization Control Words (ICWs) Operation Command Words (OCWs) Operating Modes of OCW Operatiang Modes of 8259A Automatic End of Interrupt (AEOI) Automatic Rotation Buffered Mode Cascade Mode End of Interrupt (EOI) Fully Nested Mode Special Fully Nested Mode Special Mask Mode Specific Rotation Mode Expansion Past 64 Interrupts Interfacing of 8259A within IO Mapped IO Method 222

9 Contents ix 7.13 Programming 8259A Software Design Problems 224 Exercises 230 Multiple Choice Questions 230 Descriptive Questions 234 PART II 8. Math Coprocessor Introduction Introduction to the Escape Instructions Host Response of Host Processor to Escape Instructions Coprocessor Response to Escape Instructions Queue Status Data Types of Real or Floating Point Data Formats Integer Data Format Packed BCD Format Pin Configuration of Block Diagram of Numeric Execution Unit Registers of Interfacing of 8087 with Instruction Set of Data Transfer Instructions Arithmetic Instructions Compare Instructions Transcendental Instructions (Trigonometric and Exponential Instructions) Load Constant Instructions Processor Control Instructions Programming Examples of Exercises 272 Multiple Choice Questions 272 Descriptive Questions Multiprocessing and Multiprogramming Introduction Multiprocessing and Multiprogramming Benefits of Multiprocessing Lock Facility based Multiprocessing Systems Coprocessor Configuration Escape (ESC) Instruction Coprocessor Configuration Operation 282

10 x Contents 9.5 Closely Coupled Configuration Loosely Coupled Configuration Bus Allocation Schemes Daisy Chaining Scheme of Bus Allocation Polling Scheme of Bus Allocation Independent Request Scheme of Bus Allocation 288 Exercises 289 Multiple Choice Questions 289 Descriptive Questions Serial and Parallel Data Transfer Introduction Parallel Transmission Microprocessor Controlled Data Transfer Programmed IO Interrupt Driven IO Direct Memory Access (DMA) Burst or Block Transfer DMA Cycle Steal or Single Byte Transfer DMA Serial Transmission Types of Communication Systems Simplex Duplex Serial Transmission Format Asynchronous Serial Data Transfer Synchronous Serial Data Transfer Baud Rate Data Communication Over Long Distances Software Based Serial I/O Serial I/O Transfer Using Parallel Port Universal Synchronous Asynchronous Receiver Transmitter (USART) Features of 8251 USART Pin Description of Block Diagram Description of Data Bus Buffer Read/Write Control Logic Transmitter Section Receiver Section Modem Control Control Word Mode Word Format Command Word Format Status Word Data Transfer Operations of Asynchronous Mode Transmission Asynchronous Mode Reception 320

978812034 0879 Author : MATHUR, SUNIL Type the URL :

11 Microprocessor 8086 : Architecture,Programming And Interfacing 25% OFF Publisher : PHI Learning ISBN : Author : MATHUR, SUNIL Type the URL : Get this ebook

MICROPROCESSOR 8085 AND ITS INTERFACING SUNIL MATHUR. Second Edition A 1 ALE AD 0 - AD 7. Latch. Keyboard data V CC 8 P A D D 0 7 STB STB G G A

Second Edition MICROPROCESSOR 8085 AND ITS INTERFACING ALE AD 0 - AD 7 LE Latch A 1 A 1 A 0 A 0 A 2 A7 D D 0 7 P A Keyboard data V CC 8 0 8 5 WR RD IO/M 1 2 G2B G G A A 3:8 B Decoder 5 C 3 Gnd IOR IOW