CSE 140: Logic Minimization Lecture
|
|
|
- Gregory Oliver
- 5 years ago
- Views:
Transcription
1 CSE 140: Logic Minimization Lecture
2 What is Logic Minimization? Input: A set of minterms corresponding to a function F Output: A minimal set of prime implicants that corresponds to function F Example: Input: F = abc' + ab'c' + a'bc' Output: F = ac' + bc'
3 Recall the Karnaugh Map Adjacent squares are hamming distance 1 away from each other. Enables you to visually circle the prime implicants and generate minimal cover. Example: wx\yz
4 Problem with Karnaugh Maps Difficult to trace hamming adjacencies with more than 4 variables. Need a way to automate Logic Minimization for a computer to do it.
5 Step 1: Prime Implicant Generation with Tabulation Method Conceptually: Expand minterms into larger implicants until you cannot continue expanding. Let's start with the first expansion step: Compare minterms pairwise and expand those that are hamming adjacent. For n minterms, this requires n^2 comparisons. Can we do better?
6 Observation: a minterm m that is hamming adjacent to minterm n will only differ by a single 1. Example: Minterm 001 and 011 are hamming adjacent and can be combined into 0-1. Only way for minterms to be hamming adjacent is if one has exactly one more 1 than the other. Idea: Partition the minterms into groups based on the number of 1's they contain
7 Example: Minterms 0001, 0101, 0110, 1000, 1100, 1101, 1110, 1111 Partition into groups Gi, where i is the number of 1's every element in the group contains G1: 0001, 1000 G2: 0101, 0110, 1100 G3: 1101, 1110 G4: 1111 Now we only need to combine elements from Gi with ones from Gi+1, reducing the number of comparisons from 64 to 14!
8 Definition: a k-subcube is an implicant with k dashes. For example, 11-0 is a 1-subcube. G1: 0001, 1000 G2: 0101, 0110, 1100 G3: 1101, 1110 G4: 1111 The above comprise the set of 0-subcubes, and we now need to combine them to generate 1- subcubes.
9 0-subcubes G1: 0001x, 1000 G2: 0101x, 0110, 1100 G3: 1101, 1110 G4: subcubes G1: 0-01, G2: G3: G4: N/A Can combine 0001 and 0101 to get and 0101 are thus covered (denoted with an x)
10 0-subcubes G1: 0001x, 1000 G2: 0101x, 0110, 1100 G3: 1101, 1110 G4: subcubes G1: 0-01, G2: G3: G4: N/A Can't combine 0001 with 0110 because they are not hamming adjacent
11 0-subcubes G1: 0001x, 1000 G2: 0101x, 0110, 1100 G3: 1101, 1110 G4: subcubes G1: 0-01, G2: G3: G4: N/A Can't combine 0001 with 1100
12 0-subcubes G1: 0001x, 1000 G2: 0101x, 0110, 1100 G3: 1101, 1110 G4: subcubes G1: 0-01, G2: G3: G4: N/A Can't combine 1000 with 0101
13 0-subcubes G1: 0001x, 1000 G2: 0101x, 0110, 1100 G3: 1101, 1110 G4: subcubes G1: 0-01, G2: G3: G4: N/A Can't combine 1000 with 0110
14 0-subcubes G1: 0001x, 1000x G2: 0101x, 0110, 1100x G3: 1101, 1110 G4: subcubes G1: 0-01, 1-00 G2: G3: G4: N/A Can combine 1000 with 1100 to get We can thus mark them as covered with an x.
15 0-subcubes G1: 0001x, 1000x G2: 0101x, 0110x, 1100x G3: 1101x, 1110x G4: 1111x 1-subcubes G1: 0-01, 1-00 G2: -101, -110, 110-, 11-0 G3: 11-1, 111- G4: N/A And so on.
16 1-subcubes G1: 0-01, 1-00 G2: -101, -110, 110-, 11-0 G3: 11-1, 111- G4: N/A Now we want to merge our 1-subcubes into 2- subcubes. We can do the same thing, but this time treating the '-' as essentially another symbol.
17 1-subcubes G1: 0-01, 1-00 G2: -101, -110, 110-, 11-0 G3: 11-1, 111- G4: N/A 2-subcubes G1: G2: G3: N/A 0-01 and -101 are more than Hamming-1 apart, so can't merge.
18 1-subcubes G1: 0-01, 1-00 G2: -101, -110, 110-, 11-0 G3: 11-1, 111- G4: N/A 2-subcubes G1: G2: G3: N/A 0-01 and -110 are more than Hamming-1 apart, so can't merge.
19 1-subcubes G1: 0-01, 1-00 G2: -101, -110, 110-, 11-0 G3: 11-1, 111- G4: N/A 2-subcubes G1: G2: G3: N/A 0-01 and 110- are more than Hamming-1 apart, so can't merge.
20 1-subcubes G1: 0-01, 1-00 G2: -101, -110, 110-, 11-0 G3: 11-1, 111- G4: N/A 2-subcubes G1: G2: G3: N/A 0-01 and 11-0 are more than Hamming-1 apart, so can't merge.
21 1-subcubes G1: 0-01, 1-00 G2: -101, -110, 110-, 11-0 G3: 11-1, 111- G4: N/A 2-subcubes G1: G2: G3: N/A 1-00 and -101 are more than Hamming-1 apart, so can't merge.
22 1-subcubes G1: 0-01, 1-00 G2: -101, -110, 110-, 11-0 G3: 11-1, 111- G4: N/A 2-subcubes G1: G2: G3: N/A 1-00 and -110 are more than Hamming-1 apart, so can't merge.
23 1-subcubes G1: 0-01, 1-00 G2: -101, -110, 110-, 11-0 G3: 11-1, 111- G4: N/A 2-subcubes G1: G2: G3: N/A 1-00 and 110- are more than Hamming-1 apart, so can't merge.
24 1-subcubes G1: 0-01, 1-00 G2: -101, -110, 110-, 11-0 G3: 11-1, 111- G4: N/A 2-subcubes G1: G2: G3: N/A 1-00 and 11-0 are more than Hamming-1 apart, so can't merge.
25 1-subcubes G1: 0-01, 1-00 G2: -101, -110, 110-, 11-0 G3: 11-1, 111- G4: N/A 2-subcubes G1: N/A G2: G3: N/A Can't merge any of G1 into G2!
26 1-subcubes G1: 0-01, 1-00 G2: -101, -110, 110-, 11-0 G3: 11-1, 111- G4: N/A 2-subcubes G1: N/A G2: G3: N/A -101 and 11-1 are more than hamming-1 away from each other, so can't merge
27 1-subcubes G1: 0-01, 1-00 G2: -101, -110, 110-, 11-0 G3: 11-1, 111- G4: N/A 2-subcubes G1: N/A G2: G3: N/A -110 and 11-1 are more than hamming-1 away from each other, so can't merge
28 1-subcubes G1: 0-01, 1-00 G2: -101, -110, 110-, 11-0 G3: 11-1, 111- G4: N/A 2-subcubes G1: N/A G2: G3: N/A 110- and 11-1 are more than hamming-1 away from each other, so can't merge
29 1-subcubes G1: 0-01, 1-00 G2: -101, -110, 110-, 11-0x G3: 11-1x, 111- G4: N/A 2-subcubes G1: N/A G2: 11-- G3: N/A 11-0 and 11-1 can combine to form 11--, so they can be merged and marked with an 'x' as covered
30 1-subcubes G1: 0-01, 1-00 G2: -101, -110, 110-x, 11-0x G3: 11-1x, 111-x G4: N/A 2-subcubes G1: N/A G2: 11-- G3: N/A And so on.
31 1-subcubes G1: 0-01, 1-00 G2: -101, -110, 110-x, 11-0x G3: 11-1x, 111-x G4: N/A 2-subcubes G1: N/A G2: 11-- G3: N/A We then take the remaining uncovered implicants as our prime implicants.
32 Prime implicants: 0-01 w'y'z 1-00 wy'z' -101 xy'z -110 xyz' 11-- wx Now need to minimize this.
33 Quine McCluskey Algorithm Idea: Create table with minterms and implicants. For example, with our prime implicants that we calculated: w'y'z 1 1 wy'z' 1 1 xy'z 1 1 xyz' 1 1 wx
34 Rule 1: Essential prime implicants must be used, so we can cross out their corresponding rows and columns since they will already be covered w'y'z 1 1 wy'z' 1 1 xy'z 1 1 xyz' 1 1 wx
35 Rule 2: If one row dominates another row, we can cross out the dominated row because whatever minterms the dominated row contains will already be covered P P2 1 1 P P4 1 1 P
36 Rule 3: If one column dominates another column, we can cross out the dominating column because whatever implicant covers the dominating minterm will cover the one it dominates as well P P2 1 1 P P4 1 1 P
37 Algorithm Apply the following rules until steady-state Rule 1: Remove essentials to put in our minimal cover and cross out their rows and columns. Rule 2: If a row dominates another row, cross out the dominated row. Rule 3: If a column dominates another column, cross out the dominating column.
38 With our example, we have 4 essentials that result in the entire table going away, so our minimal cover is w'y'z + wy'z' + xyz' + wx w'y'z 1 1 wy'z' 1 1 xy'z 1 1 xyz' 1 1 wx
39 Recall the Karnaugh Map Sanity Check Minimal cover is: w'y'z + wx + xyz' + xy'z' Same as before! wx\yz
40 What if we had the following prime implicants? P0 = x y P1 = y z P2 = xz P3 = xy P4 = yz P5 = x z
41 P0 1 1 P1 1 1 P2 1 1 P3 1 1 P4 1 1 P5 1 1 No row or column dominance! This is called a cyclic core. How do we identify the minimal cover?
42 Use Petrick s Method! List the implicants in product of sums form What does this mean?
43 P0 1 1 P1 1 1 P2 1 1 P3 1 1 P4 1 1 P5 1 1 To cover minterm 0, we can use P0 or P5
44 P0 1 1 P1 1 1 P2 1 1 P3 1 1 P4 1 1 P5 1 1 To cover minterm 0, we can use P0 or P5 P0 + P5
45 P0 1 1 P1 1 1 P2 1 1 P3 1 1 P4 1 1 P5 1 1 To cover minterm 1, we can use P0 or P1 (P0 + P5)(P0 + P1)
46 P0 1 1 P1 1 1 P2 1 1 P3 1 1 P4 1 1 P5 1 1 To cover minterm 2, we can use P4 or P5 (P0 + P5)(P0 + P1)(P4 + P5)
47 P0 1 1 P1 1 1 P2 1 1 P3 1 1 P4 1 1 P5 1 1 We do this for all covered minterms to finally get: (P0+P5)(P0+P1)(P4+P5) (P1+P2)(P3+P4) (P2+P3)
48 Now that we've formulated it as a product-ofsums, we can convert it to a sum-of-products: (P0+P5)(P0+P1)(P4+P5)(P1+P2)(P3+P4) (P2+P3) =
49 Now that we've formulated it as a product-ofsums, we can convert it to a sum-of-products: (P0+P5)(P0+P1)(P4+P5)(P1+P2)(P3+P4) (P2+P3) = (P0+P5P1)(P4+P5P3)(P2+P1P3) = (P0P4+P0P5P3+P1P4P5+P1P3P5)(P2+P1P3) = P0P2P4+P0P1P3P4+P0P2P3P5+P0P1P3P5+ P1P2P4P5+P1P3P4P5+P1P2P3P5+ P1P3P5
50 Now that we've formulated it as a product-ofsums, we can convert it to a sum-of-products: (P0+P5)(P0+P1)(P4+P5)(P1+P2)(P3+P4) (P2+P3) = (P0+P5P1)(P4+P5P3)(P2+P1P3) = (P0P4+P0P5P3+P1P4P5+P1P3P5)(P2+P1P3) = P0P2P4+P0P1P3P4+P0P2P3P5+P0P1P3P5+ P1P2P4P5+P1P3P4P5+P1P2P3P5+ P1P3P5
51 So, there are 2 possible minimum covers: P0, P2, P4 P1, P3, P5 Recall that: P0 = x y P1 = y z P2 = xz P3 = xy P4 = yz P5 = x z
52 So our minimal covers in sum of products form are: x y + xz + yz y z + xy + x z
53 Sanity Check: x\yz Minimal Cover: x y + xz + yz Same as what we got using Petrick s Method!
54 Sanity Check: x\yz Minimal Cover: y z + xy + x z Same as what we got using Petrick s Method!
55 Overall algorithm 1. Generate Prime Implicants using Tabulation Method 2. Map Prime Implicants to Quine McCluskey table and perform the pruning based on the row/column dominance and essential heuristics. 3. If cyclic core is reached, apply Petrick's Method.
Karnaugh Map (K-Map) Karnaugh Map. Karnaugh Map Examples. Ch. 2.4 Ch. 2.5 Simplification using K-map
Karnaugh Map (K-Map) Ch. 2.4 Ch. 2.5 Simplification using K-map A graphical map method to simplify Boolean function up to 6 variables A diagram made up of squares Each square represents one minterm (or
Contents. Chapter 3 Combinational Circuits Page 1 of 34
Chapter 3 Combinational Circuits Page of 34 Contents Contents... 3 Combinational Circuits... 2 3. Analysis of Combinational Circuits... 2 3.. Using a Truth Table... 2 3..2 Using a Boolean unction... 4
User s Manual. Ronwaldo A. Collado Diosdado Y. Tejoso Jr. CMSC 130 Logistic Design and Digital Computer Circuits Second Semester, A. Y.
The Quine-McCluskey Method, also known as the Tabulation Method is a specific step-by-step method that is ensured to generate a simplified standard-form expression for a function. Ronwaldo A. Collado Diosdado
Quine-McCluskey Algorithm
Quine-McCluskey Algorithm Useful for minimizing equations with more than 4 inputs. Like K-map, also uses combining theorem Allows for automation Chapter Edward McCluskey (99-06) Pioneer in Electrical
3.4 QUINE MCCLUSKEY METHOD 73. f(a, B, C, D, E)¼AC ĒþB CD þ BCDþĀBD.
3.4 QUINE MCCLUSKEY METHOD 73 FIGURE 3.22 f(a, B, C, D, E)¼B CD þ BCD. FIGURE 3.23 f(a, B, C, D, E)¼AC ĒþB CD þ BCDþĀBD. A¼1map are, 1, and 1, respectively, whereas the corresponding entries in the A¼0
A B AB CD Objectives:
Objectives:. Four variables maps. 2. Simplification using prime implicants. 3. "on t care" conditions. 4. Summary.. Four variables Karnaugh maps Minterms A A m m m3 m2 A B C m4 C A B C m2 m8 C C m5 C m3
Gate Level Minimization Map Method
Gate Level Minimization Map Method Complexity of hardware implementation is directly related to the complexity of the algebraic expression Truth table representation of a function is unique Algebraically
Introduction to Microprocessors and Digital Logic (ME262) Boolean Algebra and Logic Equations. Spring 2011
Introduction to Microprocessors and Digital (ME262) lgebra and Spring 2 Outline. lgebra 2. 3. Karnaugh Maps () 4. Two-variable 5. 6. 7. 2 lgebra s of Simplifying equations are defined in terms of inary
UNIT II. Circuit minimization
UNIT II Circuit minimization The complexity of the digital logic gates that implement a Boolean function is directly related to the complexity of the algebraic expression from which the function is implemented.
Introduction. The Quine-McCluskey Method Handout 5 January 24, CSEE E6861y Prof. Steven Nowick
CSEE E6861y Prof. Steven Nowick The Quine-McCluskey Method Handout 5 January 24, 2013 Introduction The Quine-McCluskey method is an exact algorithm which finds a minimum-cost sum-of-products implementation
Graduate Institute of Electronics Engineering, NTU. CH5 Karnaugh Maps. Lecturer: 吳安宇教授 Date:2006/10/20 ACCESS IC LAB
CH5 Karnaugh Maps Lecturer: 吳安宇教授 Date:2006/0/20 CCESS IC L Problems in lgebraic Simplification The procedures are difficult to apply in a systematic way. It is difficult to tell when you have arrived
Review: Standard forms of expressions
Karnaugh maps Last time we saw applications of Boolean logic to circuit design. The basic Boolean operations are AND, OR and NOT. These operations can be combined to form complex expressions, which can
Simplification of Boolean Functions
COM111 Introduction to Computer Engineering (Fall 2006-2007) NOTES 5 -- page 1 of 5 Introduction Simplification of Boolean Functions You already know one method for simplifying Boolean expressions: Boolean
Chapter 3 Simplification of Boolean functions
3.1 Introduction Chapter 3 Simplification of Boolean functions In this chapter, we are going to discuss several methods for simplifying the Boolean function. What is the need for simplifying the Boolean
ESOP CIRCUIT MINIMIZATION BASED ON THE FUNCTION ON-SET. Likai Chai
ESOP CIRCUIT MINIMIZATION BASED ON THE FUNCTION ON-SET By Likai Chai A Thesis Submitted to the Faculty of Mississippi State University in Partial Fulfillment of the Requirements for the Degree of Master
Chapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Overview Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard
ELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
Digital Logic Lecture 7 Gate Level Minimization
Digital Logic Lecture 7 Gate Level Minimization By Ghada Al-Mashaqbeh The Hashemite University Computer Engineering Department Outline Introduction. K-map principles. Simplification using K-maps. Don t-care
Giovanni De Micheli. Integrated Systems Centre EPF Lausanne
Two-level Logic Synthesis and Optimization Giovanni De Micheli Integrated Systems Centre EPF Lausanne This presentation can be used for non-commercial purposes as long as this note and the copyright footers
University of Technology
University of Technology Lecturer: Dr. Sinan Majid Course Title: microprocessors 4 th year Lecture 5 & 6 Minimization with Karnaugh Maps Karnaugh maps lternate way of representing oolean function ll rows
Gate-Level Minimization
MEC520 디지털공학 Gate-Level Minimization Jee-Hwan Ryu School of Mechanical Engineering Gate-Level Minimization-The Map Method Truth table is unique Many different algebraic expression Boolean expressions may
Simplification of Boolean Functions
Simplification of Boolean Functions Contents: Why simplification? The Map Method Two, Three, Four and Five variable Maps. Simplification of two, three, four and five variable Boolean function by Map method.
Gate Level Minimization
Gate Level Minimization By Dr. M. Hebaishy Digital Logic Design Ch- Simplifying Boolean Equations Example : Y = AB + AB Example 2: = B (A + A) T8 = B () T5 = B T Y = A(AB + ABC) = A (AB ( + C ) ) T8 =
Literal Cost F = BD + A B C + A C D F = BD + A B C + A BD + AB C F = (A + B)(A + D)(B + C + D )( B + C + D) L = 10
Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal approach to simplification that is performed using a specific procedure or algorithm
Switching Circuits & Logic Design
Switching Circuits & Logic Design Jie-Hong Roland Jiang 江介宏 Department of Electrical Engineering National Taiwan University Fall 23 5 Karnaugh Maps K-map Walks and Gray Codes http://asicdigitaldesign.wordpress.com/28/9/26/k-maps-walks-and-gray-codes/
Gate-Level Minimization. BME208 Logic Circuits Yalçın İŞLER
Gate-Level Minimization BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Complexity of Digital Circuits Directly related to the complexity of the algebraic expression we use to
Digital Logic Design. Outline
Digital Logic Design Gate-Level Minimization CSE32 Fall 2 Outline The Map Method 2,3,4 variable maps 5 and 6 variable maps (very briefly) Product of sums simplification Don t Care conditions NAND and NOR
ECE380 Digital Logic
ECE38 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum Product-of-Sums Forms, Incompletely Specified Functions Dr. D. J. Jackson Lecture 8- Terminology For
Chapter 3. Gate-Level Minimization. Outlines
Chapter 3 Gate-Level Minimization Introduction The Map Method Four-Variable Map Five-Variable Map Outlines Product of Sums Simplification Don t-care Conditions NAND and NOR Implementation Other Two-Level
Digital Design. Chapter 4. Principles Of. Simplification of Boolean Functions
Principles Of Digital Design Chapter 4 Simplification of Boolean Functions Karnaugh Maps Don t Care Conditions Technology Mapping Optimization, Conversions, Decomposing, Retiming Boolean Cubes for n =,
ENGIN 112 Intro to Electrical and Computer Engineering
ENGIN 2 Intro to Electrical and Computer Engineering Lecture 8 Minimization with Karnaugh Maps Overview K-maps: an alternate approach to representing oolean functions K-map representation can be used to
LOGIC CIRCUITS. Kirti P_Didital Design 1
LOGIC CIRCUITS Kirti P_Didital Design 1 Introduction The digital system consists of two types of circuits, namely (i) Combinational circuits and (ii) Sequential circuit A combinational circuit consists
Synthesis of 2-level Logic Heuristic Method. Two Approaches
Synthesis of 2-level Logic Heuristic Method Lecture 8 Exact Two Approaches Find all primes Find a complete sum Find a minimum cover (covering problem) Heuristic Take an initial cover of cubes Repeat Expand
Chapter 2 Combinational
Computer Engineering 1 (ECE290) Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization HOANG Trang 2008 Pearson Education, Inc. Overview Part 1 Gate Circuits and Boolean Equations Binary Logic
Gate-Level Minimization
Gate-Level Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2011 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method
CMPE223/CMSE222 Digital Logic
CMPE223/CMSE222 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum Product-of-Sums Forms, Incompletely Specified Functions Terminology For a given term, each
IT 201 Digital System Design Module II Notes
IT 201 Digital System Design Module II Notes BOOLEAN OPERATIONS AND EXPRESSIONS Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to represent a logical quantity.
B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN
B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is ----- Write the first 9 decimal digits in base 3. (c) What is meant by don
VLSI System Design Part II : Logic Synthesis (1) Oct Feb.2007
VLSI System Design Part II : Logic Synthesis (1) Oct.2006 - Feb.2007 Lecturer : Tsuyoshi Isshiki Dept. Communications and Integrated Systems, Tokyo Institute of Technology isshiki@vlsi.ss.titech.ac.jp
INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR Stamp / Signature of the Invigilator
INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR Stamp / Signature of the Invigilator EXAMINATION ( Mid Semester ) SEMESTER ( Spring ) Roll Number Section Name Subject Number C S 2 1 0 0 2 Subject Name Switching
Combinational Logic Circuits
Chapter 2 Combinational Logic Circuits J.J. Shann (Slightly trimmed by C.P. Chung) Chapter Overview 2-1 Binary Logic and Gates 2-2 Boolean Algebra 2-3 Standard Forms 2-4 Two-Level Circuit Optimization
CSE 140 Homework Three
CSE 140 Homework Three March 3, 2014 Only Problem Set Part B will be graded. Turn in only Problem Set Part B which will be due on March 14, 2014 (Friday) at 4:00pm. 1 Problem Set Part A Roth&Kinney, 6th
ECE 5745 Complex Digital ASIC Design Topic 12: Synthesis Algorithms
ECE 5745 Complex Digital ASIC Design Topic 12: Synthesis Algorithms Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece5745 RTL to
Synthesis 1. 1 Figures in this chapter taken from S. H. Gerez, Algorithms for VLSI Design Automation, Wiley, Typeset by FoilTEX 1
Synthesis 1 1 Figures in this chapter taken from S. H. Gerez, Algorithms for VLSI Design Automation, Wiley, 1998. Typeset by FoilTEX 1 Introduction Logic synthesis is automatic generation of circuitry
Combinational Logic Circuits Part III -Theoretical Foundations
Combinational Logic Circuits Part III -Theoretical Foundations Overview Simplifying Boolean Functions Algebraic Manipulation Karnaugh Map Manipulation (simplifying functions of 2, 3, 4 variables) Systematic
S1 Teknik Telekomunikasi Fakultas Teknik Elektro FEH2H3 2016/2017
S1 Teknik Telekomunikasi Fakultas Teknik Elektro FEH2H3 2016/2017 Karnaugh Map Karnaugh maps Last time we saw applications of Boolean logic to circuit design. The basic Boolean operations are AND, OR and
Gate-Level Minimization
Gate-Level Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method
Class Subject Code Subject Prepared By Lesson Plan for Time: Lesson. No 1.CONTENT LIST: Introduction to UnitI 2. SKILLS ADDRESSED: Listening I year, 02 sem CS6201 Digital Principles & System Design S.Seedhanadevi
2008 The McGraw-Hill Companies, Inc. All rights reserved.
28 The McGraw-Hill Companies, Inc. All rights reserved. 28 The McGraw-Hill Companies, Inc. All rights reserved. All or Nothing Gate Boolean Expression: A B = Y Truth Table (ee next slide) or AB = Y 28
DIGITAL CIRCUIT LOGIC UNIT 5: KARNAUGH MAPS (K-MAPS)
DIGITAL CIRCUIT LOGIC UNIT 5: KARNAUGH MAPS (K-MAPS) 1 Learning Objectives 1. Given a function (completely or incompletely specified) of three to five variables, plot it on a Karnaugh map. The function
CSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map
CSCI 22: Computer Architecture I Instructor: Pranava K. Jha Simplification of Boolean Functions using a Karnaugh Map Q.. Plot the following Boolean function on a Karnaugh map: f(a, b, c, d) = m(, 2, 4,
Get Free notes at Module-I One s Complement: Complement all the bits.i.e. makes all 1s as 0s and all 0s as 1s Two s Complement: One s complement+1 SIGNED BINARY NUMBERS Positive integers (including zero)
Combinatorial Algorithms. Unate Covering Binate Covering Graph Coloring Maximum Clique
Combinatorial Algorithms Unate Covering Binate Covering Graph Coloring Maximum Clique Example As an Example, let s consider the formula: F(x,y,z) = x y z + x yz + x yz + xyz + xy z The complete sum of
Chapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show
Gate-Level Minimization. section instructor: Ufuk Çelikcan
Gate-Level Minimization section instructor: Ufuk Çelikcan Compleity of Digital Circuits Directly related to the compleity of the algebraic epression we use to build the circuit. Truth table may lead to
ELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter
CHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey
CHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey 2. Introduction Logic gates are connected together to produce a specified output for certain specified combinations of input
Module -7. Karnaugh Maps
1 Module -7 Karnaugh Maps 1. Introduction 2. Canonical and Standard forms 2.1 Minterms 2.2 Maxterms 2.3 Canonical Sum of Product or Sum-of-Minterms (SOM) 2.4 Canonical product of sum or Product-of-Maxterms(POM)
Outcomes. Unit 9. Logic Function Synthesis KARNAUGH MAPS. Implementing Combinational Functions with Karnaugh Maps
.. Outcomes Unit I can use Karnaugh maps to synthesize combinational functions with several outputs I can determine the appropriate size and contents of a memory to implement any logic function (i.e. truth
Chapter 6. Logic Design Optimization Chapter 6
Chapter 6 Logic Design Optimization Chapter 6 Optimization The second part of our design process. Optimization criteria: Performance Size Power Two-level Optimization Manipulating a function until it is
NODIA AND COMPANY. GATE SOLVED PAPER Computer Science Engineering Digital Logic. Copyright By NODIA & COMPANY
No part of this publication may be reproduced or distributed in any form or any means, electronic, mechanical, photocopying, or otherwise without the prior permission of the author. GATE SOLVED PAPER Computer
Specifying logic functions
CSE4: Components and Design Techniques for Digital Systems Specifying logic functions Instructor: Mohsen Imani Slides from: Prof.Tajana Simunic and Dr.Pietro Mercati We have seen various concepts: Last
Unit 4: Formal Verification
Course contents Unit 4: Formal Verification Logic synthesis basics Binary-decision diagram (BDD) Verification Logic optimization Technology mapping Readings Chapter 11 Unit 4 1 Logic Synthesis & Verification
Combinational Logic & Circuits
Week-I Combinational Logic & Circuits Spring' 232 - Logic Design Page Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other
Lecture 4: Implementation AND, OR, NOT Gates and Complement
EE210: Switching Systems Lecture 4: Implementation AND, OR, NOT Gates and Complement Prof. YingLi Tian Feb. 13, 2018 Department of Electrical Engineering The City College of New York The City University
Combinational Logic Circuits
Chapter 3 Combinational Logic Circuits 12 Hours 24 Marks 3.1 Standard representation for logical functions Boolean expressions / logic expressions / logical functions are expressed in terms of logical
Two-Level Logic Optimization ( Introduction to Computer-Aided Design) School of EECS Seoul National University
Two-Level Logic Optimization (4541.554 Introduction to Computer-Aided Design) School of EECS Seoul National University Minimization of Two-Level Functions Goals: Minimize cover cardinality Minimize number
Combinational Circuits Digital Logic (Materials taken primarily from:
Combinational Circuits Digital Logic (Materials taken primarily from: http://www.facstaff.bucknell.edu/mastascu/elessonshtml/eeindex.html http://www.cs.princeton.edu/~cos126 ) Digital Systems What is a
ESE535: Electronic Design Automation. Today. EDA Use. Problem PLA. Programmable Logic Arrays (PLAs) Two-Level Logic Optimization
ESE535: Electronic Design Automation Day 18: March 25, 2013 Two-Level Logic-Synthesis Today Two-Level Logic Optimization Problem Behavioral (C, MATLAB, ) Arch. Select Schedule RTL FSM assign Definitions
Karnaugh Maps. Kiril Solovey. Tel-Aviv University, Israel. April 8, Kiril Solovey (TAU) Karnaugh Maps April 8, / 22
Karnaugh Maps Kiril Solovey Tel-Aviv University, Israel April 8, 2013 Kiril Solovey (TAU) Karnaugh Maps April 8, 2013 1 / 22 Reminder: Canonical Representation Sum of Products Function described for the
9/10/2016. ECE 120: Introduction to Computing. The Domain of a Boolean Function is a Hypercube. List All Implicants for One Variable A
University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing To Simplify, Write Function as a Sum of Prime Implicants One way to simplify a
QUESTION BANK FOR TEST
CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice
(Refer Slide Time 5:19)
Digital Circuits and Systems Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology, Madras Lecture - 7 Logic Minimization using Karnaugh Maps In the last lecture we introduced
ICS 252 Introduction to Computer Design
ICS 252 Introduction to Computer Design Lecture 10 Eli Bozorgzadeh Computer Science Department-UCI Reference Lecture note Ankur Srivastava http://www.enee.umd.edu/class/enee644/ Chapter 7(7.3,7.4) of the
2.1 Binary Logic and Gates
1 EED2003 Digital Design Presentation 2: Boolean Algebra Asst. Prof.Dr. Ahmet ÖZKURT Asst. Prof.Dr Hakkı T. YALAZAN Based on the Lecture Notes by Jaeyoung Choi choi@comp.ssu.ac.kr Fall 2000 2.1 Binary
Presented By :- Alok Kumar Lecturer in ECE C.R.Polytechnic, Rohtak
Presented By :- Alok Kumar Lecturer in ECE C.R.Polytechnic, Rohtak Content - Introduction -2 Feature -3 Feature of BJT -4 TTL -5 MOS -6 CMOS -7 K- Map - Introduction Logic IC ASIC: Application Specific
CS February 17
Discrete Mathematics CS 26 February 7 Equal Boolean Functions Two Boolean functions F and G of degree n are equal iff for all (x n,..x n ) B, F (x,..x n ) = G (x,..x n ) Example: F(x,y,z) = x(y+z), G(x,y,z)
Switching Theory And Logic Design UNIT-II GATE LEVEL MINIMIZATION
Switching Theory And Logic Design UNIT-II GATE LEVEL MINIMIZATION Two-variable k-map: A two-variable k-map can have 2 2 =4 possible combinations of the input variables A and B. Each of these combinations,
CS6201-DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PART-B UNIT-I BOOLEAN ALGEBRA AND LOGIC GATES.
CS6201-DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PART-B UNIT-I BOOLEAN ALGEBRA AND LOGIC GATES. 1) Simplify the boolean function using tabulation method. F = (0, 1, 2, 8, 10, 11, 14, 15) List all
Supplement to. Logic and Computer Design Fundamentals 4th Edition 1
Supplement to Logic and Computer esign Fundamentals 4th Edition MORE OPTIMIZTION Selected topics not covered in the fourth edition of Logic and Computer esign Fundamentals are provided here for optional
4 KARNAUGH MAP MINIMIZATION
4 KARNAUGH MAP MINIMIZATION A Karnaugh map provides a systematic method for simplifying Boolean expressions and, if properly used, will produce the simplest SOP or POS expression possible, known as the
www.vidyarthiplus.com Question Paper Code : 31298 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013. Third Semester Computer Science and Engineering CS 2202/CS 34/EC 1206 A/10144 CS 303/080230012--DIGITAL
Menu. Algebraic Simplification - Boolean Algebra EEL3701 EEL3701. MSOP, MPOS, Simplification
Menu Minterms & Maxterms SOP & POS MSOP & MPOS Simplification using the theorems/laws/axioms Look into my... 1 Definitions (Review) Algebraic Simplification - Boolean Algebra Minterms (written as m i ):
Experiment 3: Logic Simplification
Module: Logic Design Name:... University no:.. Group no:. Lab Partner Name: Mr. Mohamed El-Saied Experiment : Logic Simplification Objective: How to implement and verify the operation of the logical functions
ICS 252 Introduction to Computer Design
ICS 252 Introduction to Computer Design Logic Optimization Eli Bozorgzadeh Computer Science Department-UCI Hardware compilation flow HDL RTL Synthesis netlist Logic synthesis library netlist Physical design
CS8803: Advanced Digital Design for Embedded Hardware
CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883
Unit-IV Boolean Algebra
Unit-IV Boolean Algebra Boolean Algebra Chapter: 08 Truth table: Truth table is a table, which represents all the possible values of logical variables/statements along with all the possible results of
數位系統 Digital Systems 朝陽科技大學資工系. Speaker: Fuw-Yi Yang 楊伏夷. 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象, 視之不可見者曰夷
數位系統 Digital Systems Department of Computer Science and Information Engineering, Chaoyang University of Technology 朝陽科技大學資工系 Speaker: Fuw-Yi Yang 楊伏夷 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象,
10EC33: DIGITAL ELECTRONICS QUESTION BANK
10EC33: DIGITAL ELECTRONICS Faculty: Dr.Bajarangbali E Examination QuestionS QUESTION BANK 1. Discuss canonical & standard forms of Boolean functions with an example. 2. Convert the following Boolean function
TWO-LEVEL COMBINATIONAL LOGIC
TWO-LEVEL COMBINATIONAL LOGIC OVERVIEW Canonical forms To-level simplification Boolean cubes Karnaugh maps Quine-McClusky (Tabulation) Method Don't care terms Canonical and Standard Forms Minterms and
Points Addressed in this Lecture. Standard form of Boolean Expressions. Lecture 4: Logic Simplication & Karnaugh Map
Points Addressed in this Lecture Lecture 4: Logic Simplication & Karnaugh Map Professor Peter Cheung Department of EEE, Imperial College London Standard form of Boolean Expressions Sum-of-Products (SOP),
Slides for Lecture 15
Slides for Lecture 5 ENEL 353: Digital Circuits Fall 203 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary October, 203 ENEL 353 F3 Section
Incompletely Specified Functions with Don t Cares 2-Level Transformation Review Boolean Cube Karnaugh-Map Representation and Methods Examples
Lecture B: Logic Minimization Incompletely Specified Functions with Don t Cares 2-Level Transformation Review Boolean Cube Karnaugh-Map Representation and Methods Examples Incompletely specified functions
Date Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 04. Boolean Expression Simplification and Implementation
Name: Instructor: Engr. Date Performed: Marks Obtained: /10 Group Members (ID):. Checked By: Date: Experiment # 04 Boolean Expression Simplification and Implementation OBJECTIVES: To understand the utilization
5. Minimizing Circuits
5. MINIMIZING CIRCUITS 46 5. Minimizing Circuits 5.. Minimizing Circuits. A circuit is minimized if it is a sum-of-products that uses the least number of products of literals and each product contains
Standard Forms of Expression. Minterms and Maxterms
Standard Forms of Expression Minterms and Maxterms Standard forms of expressions We can write expressions in many ways, but some ways are more useful than others A sum of products (SOP) expression contains:
Department of Electrical and Computer Engineering University of Wisconsin - Madison. ECE/CS 352 Digital System Fundamentals.
Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE/C 352 Digital ystem Fundamentals Quiz #2 Thursday, March 7, 22, 7:15--8:3PM 1. (15 points) (a) (5 points) NAND, NOR
DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 2. LECTURE: LOGIC NETWORK MINIMIZATION 2016/2017
27.2.2. DIGITAL TECHNICS Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 2. LECTURE: LOGIC NETWORK MINIMIZATION 26/27 2. LECTURE: CONTENTS. Canonical forms of Boolean functions
GATE Exercises on Boolean Logic
GATE Exerces on Boolean Logic 1 Abstract Th problem set has questions related to Boolean logic and gates taken from GATE papers over the last twenty years. Teachers can use the problem set for courses
McGILL UNIVERSITY Electrical and Computer Engineering Department MIDTERM EXAM
McGILL UNIVERSITY Electrical and Computer Engineering Department ECSE-323 DIGITAL SYSTEM DESIGN MIDTERM EXAM Winter 2010 Question Maximum Points Points Attained 1 15 2 10 3 10 4 15 5 20 6 5 Total 75 Please