Lecture Topics. Announcements. Today: The MIPS ISA (P&H ) Next: continued. Milestone #1 (due 1/26) Milestone #2 (due 2/2)

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1 Lecture Topics Today: The MIPS ISA (P&H ) Next: continued 1 Announcements Milestone #1 (due 1/26) Milestone #2 (due 2/2) Milestone #3 (due 2/9) 2 1

2 Evolution of Computing Machinery To understand where we are today, it's necessary to look at the historical context Modern computing generations (approx): Vacuum Tube Computers ( ) Transistorized Computers ( ) Integrated Circuit Computers ( ) VLSI Computers (1975 -?) 3 1 st Generation: Vacuum Tubes Atanasoff Berry Computer ( ) John Atanasoff and Clifford Berry (Iowa State) Solved systems of linear equations 4 2

3 1 st Generation: Vacuum Tubes ENIAC: Electronic Numerical Integrator and Computer (1946) John Mauchly and J. Presper Eckert (U Penn) First general purpose computer 5 1 st Generation: Vacuum Tubes IBM 650 (1955) First mass produced computer 6 3

4 2 nd Generation: Transistors DEC PDP-1 DEC PDP-1 IBM 7094 and IBM 1401 Univac rd Generation: Integrated Circuits IBM 360 Cray-1 DEC PDP-8 and PDP-11 IBM 360 Cray-1 supercomputer 8 4

5 3 rd Generation: VLSI Intel 4004 Intel 8086 Very-large-scale integrated circuits (VLSI): more than 10,000 components per chip Intel 4004 (1971): 4-bit CPU (2300 transistors) Intel 8086 (1978): 16-bit CPU (29,000 trans) 9 CISC vs RISC Terms coined by Patterson in 1980 CISC (complex instruction set computer) RISC (reduced instruction set computer) Somewhat artificial distinction all computers since 1980s use elements of the RISC approach 10 5

6 CISC Approach One machine language instruction does a "complex" task (may access memory several times, as well as use ALU) MULT A, B (A and B are variables) Multiple clock ticks per instruction Object code modules small (few instructions) 11 RISC Approach One machine language instruction does a "simple" task LOAD R1, A LOAD R2, B MULT R3, R1, R2 STORE A, R3 One clock tick per instruction Object code modules larger 12 6

7 RISC Approach Only specific LOAD and STORE instructions access memory Limited number of operation codes ("reduced instruction set") Sequence of instructions for complex task Every instruction same number of bits Targeted for pipelining 13 Summary: CISC vs RISC CISC (complex instruction set computer) Intel x86, DEC VAX, IBM 360, RISC (reduced instruction set computer) MIPS, SPARC, DEC Alpha, IBM RS6000, 14 7

8 MIPS ISA The MIPS was originally developed by Hennessy's group at Stanford in the early 1980s, commercialized in 1985 Typical RISC microprocessor small number of instructions small number of registers (32) load-store architecture designed to be pipelined 15 MIPS R

9 MIPS R2000 Instruction encoding CPU instructions FPU instructions Co-processor inst 17 MIPS Instruction Formats Instructions are 32 bits 18 9

10 MIPS Registers All registers are 32 bits wide General purpose: 32 registers (0 31) Register 0 hard-wired to zero Special purpose: PC (program counter) HI, LO (multiplication and division) 19 MIPS Register Conventions 20 10

11 21 MIPS R-format Instructions op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Instruction fields op: operation code (opcode) rs: first source register number rt: second source register number rd: destination register number shamt: shift amount (or 00000) funct: function code (extends opcode) 22 11

12 MIPS R-format Example op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add $t0, $s1, $s2 special $s1 $s2 $t0 0 add = MIPS I-format Instructions op rs rt constant or offset 6 bits 5 bits 5 bits 16 bits Instruction fields op: operation code (opcode) rs: first source register number rt: destination or source register number constant: 2 15 to offset: added to base address in rs 24 12

13 MIPS I-format Example op rs rt constant or offset 6 bits 5 bits 5 bits 16 bits addi $t0, $s1, 255 addi $s1 $t0 constant or offset = FF MIPS J-format Instructions op target 6 bits 26 bits Instruction fields op: operation code (opcode) target: used to form branch address 26 13

14 Design Principles Simplicity favors regularity all instructions same size fields in same locations within instructions Smaller is faster only 32 registers only 6-bit opcodes 27 Design Principles Make the common case fast immediate values operands in registers Good design demands good compromises three different instruction formats immediate values limited in size 28 14

15 MIPS Assembly Language Example 29 MIPS Math Unit Handles addition, subtraction and bitwise operations: ADD, ADDU SUB, SUBU AND, OR, XOR, NOR SLT, SLTU ADDU, SUBU do not set the overflow flag SLT, SLTU produce 0 or

16 MIPS Shift Unit Handles shift operations: SLL SRL SRA No provision for rotates (but can be done with a series of instructions) 31 MIPS Multiply Circuit Handles unsigned and signed multiply Circuit has two special registers to hold the result: HI and LO Product must be moved from LO to general purpose register 32 16

17 AND Operations Useful to mask bits in a word Select some bits, clear others to 0 and $t0, $t1, $t2 $t2 $t1 $t OR Operations Useful to include bits in a word Set some bits to 1, leave others unchanged or $t0, $t1, $t2 $t2 $t1 $t

18 NOT Operations Useful to invert bits in a word Change 0 to 1, and 1 to 0 a NOR b == NOT ( a OR b ) nor $t0, $t1, $zero always zero $t1 $t Shift Operations Shift left logical Shift left and fill with 0 bits sll by i bits multiplies by 2 i Shift right logical Shift right and fill with 0 bits srl by i bits divides by 2 i (unsigned) Shift right arithmetic Shift right and fill with sign bit srl by i bits divides by 2 i (signed) 36 18

19 MIPSlite Simplified version of the MIPS Most features the same: 32 general purpose registers 32-bit instructions Missing some features: No floating point unit No coprocessors Limited instruction set 37 MIPSlite Instruction Set Subset of standard MIPS instructions Most ALU operations LW and SW only No multiply or divide Summary on course website:

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