DIGITA L LOGIC AND COMPUTER ORGA NIZATION
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2 DIGITA L LOGIC AND COMPUTER ORGA NIZATION V. RAJARAMAN Honorary Professor Supercomputer Education and Research Centre Indian Institute of Science, Bangalore T. RADHAKRISHNAN Professor of Computer Science and Software Engineering Concordia University Montreal, Canada Delhi
3 DIGITAL LOGIC AND COMPUTER ORGANIZATION V. Rajaraman and T. Radhakrishnan 2006 by PHI Learning Private Limited, Delhi. All rights reserved. No part of this book may be reproduced in any form, by mimeograph or any other means, without permission in writing from the publisher. ISBN The export rights of this book are vested solely with the publisher. Third Printing April, 2009 Published by Asoke K. Ghosh, PHI Learning Private Limited, Rimjhim House, 111 Patparganj Industrial Estate, Delhi and Printed by Rajkamal Electric Press, B-35/9, G.T. Karnal Road Industrial Area, Delhi
4 Contents Preface xi 1. Data Representation 1 30 Learning Goals Introduction Numbering Systems Decimal to Binary Conversion Binary Coded Decimal Numbers Weighted Codes Self-Complementing Codesm Cyclic Codes Error Detecting Codes Error Correcting Codes Hamming Code for Error Correction Alphanumeric Codes ASCII Code Indian Script Code for Information Interchange (ISCII) Representation of Multimedia Data Representation of Pictures Respresentation of Video Representation of Audio 24 Summary 26 Exercises Boolean Algebra and Logic Gates Learning Goals Introduction Postulates of Boolean Algebra 33 iii
5 iv Contents 2.3 Basic Theorems of Boolean Algebra Duality Principle Theorems Precedence of Operators Venn Diagram Boolean Functions and Truth Tables Canonical Forms for Boolean Functions Binary Operators and Logic Gates Simplifying Boolean Expressions Veitch-Karnaugh Map Method Four Variable Karnaugh Map Incompletely Specified Function Quine-McCluskey Procedure Conclusions 67 Summary 68 Exercises Combinatorial Switching Circuits Learning Goals Introduction Combinatorial Circuit Design Procedure Integrated NAND-NOR Gates CMOS Transistor Gates NAND-NOR Gates with CMOS Transistors Open Drain and Tri-state Gates Wired AND Gate Driving a Bus from Many Sources Tri-state Gates Realization of Boolean Expressions Using NAND/NOR Gates Combinatorial Circuits Commonly Used in Digital Systems Design of Combinatorial Circuits with Multiplexers Programmable Logic Devices Realization with FPLAs Realization with PALs 121 Summary 125 Exercises Sequential Switching Circuits Learning Goals Introduction A Basic Sequential Circuit Types of Sequential Circuits Flip-Flops Counters A Binary Counter Synchronous Binary Counter 148
6 Contents v 4.6 Modelling Sequential Circuits Finite State Machines Synthesis of Synchronous Binary Counters Modulo-5 Counter Modulo-10 Counter Generation of Control Signals Controlled Counter Synthesizing General Sequential Circuits Synthesizing a Moore Machine Synthesizing a Mealy Machine Shift Registers Modelling, Analysis and Design of Sequential Circuits Implementation of Sequential Circuits with MSIs 180 Summary 185 Exercises Arithmetic and Logic Unit Learning Goals Introduction Binary Addition Binary Subtraction Complement Representation of Numbers Addition/Subtraction of Numbers in 1 s Complement Notation Addition/Subtraction of Numbers in Two s Complement Notation Binary Multiplication Multiplication of Signed Numbers Binary Division Integer Representation Floating Point Representation of Numbers Binary Floating Point Numbers IEEE Standard Floating Point Representation Floating Point Addition/Subtraction Floating Point Multiplication Floating Point Division Floating Point Arithmetic Operations Logic Circuits for Addition/Subtraction Half- and Full-Adder Using Gates A Four-bit Adder MSI Arithmetic Logic Unit A Combinatorial Circuit for Multiplication 235 Summary 237 Exercises Application of Sequential Circuits Learning Goals Introduction Algorithmic State Machine 242
7 vi Contents 6.3 Algorithmic Representation of ASM Charts Designing Digital Systems Using ASM Chart Floating Point Adder 258 Summary 261 Exercises Computer Systems Multiple Views Learning Goals Introduction A Layered View of a Computer System Hardware Level Machine and Assembly Language Levels Higher Level Language Operating System Level Application Level: Loading a Machine Language Program Performance Measures 273 Summary 274 Exercises Basic Computer Organization Learning Goals Introduction Memory Organization of SMAC (S1) Instruction and Data Representation CPU Organization Input/Output for SMAC Programming SMAC with Instruction Set S Instruction Set S2 and SMAC Organization of SMAC Assembling the Program into Machine Language Format Simulation of SMAC Program Execution and Tracing Expanding the Instruction Set Further Vector Operations and Indexing Stacks Modular Organization and Developing Large Programs Enhanced Architecture SMAC Modifications in the Instruction Formats for SMAC Conclusions 313 Summary 314 Exercises Central Processing Unit Learning Goals Introduction Operation Code Encoding and Decoding 319
8 Contents vii 9.3 Instruction Set and Instruction Formats Instruction Set Instruction Format Addressing Modes Base Addressing Segment Addressing PC Relative Addressing Indirect Addressing How to Encode Various Addressing Modes Register Sets Clocks and Timing CPU Buses Dataflow, Data Paths and Microprogramming Control Flow Summary of CPU Organization 347 Summary 348 Exercises Memory Organization Learning Goals Introduction Memory Parameters Semiconductor Memory Cell Dynamic Memory Cell Static Memory Cell Writing Data in Memory Cell Reading the Contents of Cell IC Chips for Organization of RAMs D Organization of Semiconductor Memory D Organization of Memory Systems Dynamic Random Access Memory Error Detection and Correction in Memories Read Only Memory Dual-Ported RAM Enhancing Speed and Capacity of Memories Program Behaviour and Locality Principle A Two-Level Hierarchy of Memories Cache in Memory Organization Design and Performance of Cache Memory System Virtual Memory Another Level in Hierarchy Address Translation Page Replacement Page Fetching Page Size 393
9 viii Contents How to Make Address Translation Faster Page Table Size 395 Summary 396 Exercises Input-Output Devices Learning Goals Introduction Video Display Terminal Characteristics Cathode Ray Tube Display Colour Display Tube Raster-Scan Display Device Raster-Scan Display Processing Unit Flat Panel Display Principles of Operation of Liquid Crystal Displays Input Devices Hard Copy Output Units Inkjet Printer Laser Printers Line Printers Hard Disk Drives Redundant Array of Inexpensive Disks (RAID) Floppy Disk Drives Compact Disk Read Only Memory (CDROM) Digital Versatile Disk Read Only Memory (DVD-ROM) CD-R (Recordable CD-ROM or Write Once CD-ROM WOROM) Magnetic Tape Drives Ultrium Cartridge Tape Drive Digital Audio Tapes (DAT) 426 Summary 427 Exercises Input-Output Organization Learning Goals Introduction Device Interfacing Overview of I/O Methods Program Controlled Data Transfer Interrupt Structures Single Levesl Interrupt Processing Handling Multiple Interrupts Interrupt Controlled Data Transfer Software Polling Bus Arbitration Daisy Chaining Vectored Interrupts 448
10 Contents ix Multiple Interrupt Lines VLSI Chip Interrupt Controller Programmable Peripheral Interface Unit DMA Based Data Transfer Input/Output (I/O) Processors Bus Structure Structure of a Bus Types of Bus Bus Transaction Type Timings of Bus Transactions Bus Arbitration Some Standard Buses Serial Data Communication Asynchronous Serial Data Communication Asynchronous Communication Interface Adapter (ACIA) Digital Modems Local Area Networks Ethernet Local Area Network Bus Topology Ethernet Using Star Topology Wireless LAN Client-Server Computing Using LAN 475 Summary 476 Exercises Case Study of a Real Computer System Learning Goals Introduction Viewing Pentium as a Member of a Family of Computers Memory System View The Programmer s View of Pentium Processor General Registers: EAX, EBX, ECX, EDX Pointers and Index Registers: ESP, EBP, ESI, EDI Segment Registers: CS, DS, SS, ES, FS, GS Program Flow Control Registers: EIP and EFLAGS Instruction Format Instruction Set View Classes of Instructions Interconnecting the Components into a Computer System 493 Summary 496 Exercises 496 Appendix A Suggested Hardware Lab Experiments Appendix B Decision Table Terminology References Index
11 Digital Logic And Computer Organization 25% OFF Publisher : PHI Learning ISBN : Author : RAJARAMAN, V., T. RADHAKRISHNAN Type the URL : 09 Get this ebook
Honorary Professor Supercomputer Education and Research Centre Indian Institute of Science, Bangalore
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