MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI UNIT- IV

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1 UNIT- IV PART A (2 MARK QUESTIONS) 1. What is the need for de-bouncing the keyboard? (AUC NOV 2012) Debouncing is any kind of hardware device or software that ensures that only a single signal will be acted upon for a single opening or closing of a contact. 2. What is the size of the on-chip program memory and on-chip data memory of 8051 microcontroller? (AUC MAY 2012) On-chip Program memory 4KB On-chip data memory 128 Bytes 3. List the features of the parallel ports of 8051 microcontrollers. (AUC MAY 2012) Each port has bidirectional capability. Port-0 can be configured as a normal bidirectional I/O port or address/data interfacing. Port-1 dedicated solely for I/O interfacing. Port-2 can be configured as a normal bidirectional I/O port or higher address byte for external interfacing. Each pin of port-3 can be individually programmed for I/O operation or for alternate function. 4. What are the differences between a microprocessor and a microcontroller? (AUC NOV 2011) A microprocessor requires an external memory for program/data storage. Instruction execution requires movement of data from the external memory to the microprocessor or vice versa. Usually, microprocessors have good computing power and they have higher clock speed. A microcontroller has required on-chip memory with associated peripherals.

2 A microcontroller does not require much additional interfacing ICs for operation A microcontroller clock speed is limited only to a few tens of MHz. 5. What are the advantages of using a microcontroller in place of a microprocessor? (AUC MAY 2011) Built in program memory Interrupts Built-in Monitor Program Analog I/O Serial I/O Facility to Interface External Memory Timers 6. What are the functions of the following signals of 8051? ALE/PROG, PSEN. (AUC NOV 2010) PSEN: If external ROM is used for storing program then a logic zero (0) appears on it every time the microcontroller reads a byte from memory. ALE : After receiving signal from the ALE pin, the external register memorizes the state of P0 and uses it as a memory chip address. Immediately after that, the ALU pin is returned its previous logic state and P0 is now used as a Data Bus. As seen, port data multiplexing is performed by means of only one additional integrated circuit. In other words, this port is used for both data and address transmission. 7. What are the sources of interrupts in 8051? (AUC NOV 2010) There are five interrupt sources for the 8051, which means that they can recognize 5 different events that can interrupt regular program execution. Each interrupt can be enabled or disabled by setting bits of the IE register. Likewise, the whole interrupt system can be disabled by clearing the EA bit of the same register. External interrupt INT0 Timer 0 interrupt External Interrupt INT1 Timer 1 interrupt Serial Communication Interrupt

3 8. With XTAL = MHz, what value should be loaded into TH1 to have 9600 baud rate? (AUC MAY 2010) With XTAL = MHz, value FD h should be loaded into TH1 to have 9600 baud rate. 9. How do you select the register bank in 8051 micro-controller? (AUC MAY 2010) (AUC NOV 2011) The selection of a register bank is based on the RS0 & RS1 bits of the PSW register. R S1 R S2 S PACE IN RAM 0 0 Bank0 00h-07h 0 1 Bank1 08h-0Fh 1 0 Bank2 10h-17h 1 1 Bank3 18h-1Fh 10. What are the features of a microcontroller? Built - in Program memory. Interrupts Analog I/O Serial I/O Facility to interface External memory Timers. 11. What are the features of the 8051 microcontroller? 8-bit CPU 16- bit Program Counter 8-bit Processor Status Word Internal RAM of 128 bytes Special Function Registers of 128 bytes 32 I/O pins arranged as four 8-bit ports PART- B (16 MARK QUESTIONS)

4 1. (i)explain the internal data memory structure of 8051 microcontroller with its SFRs. Internal Data Memory and Special Function Register (SFR) Map Internal Data Memory Map The special function registers (SFRs) are mapped in the upper 128 bytes of internal data memory address. Hence there is an address overlap between the upper 128 bytes of data RAM and SFRs. Please note that the upper 128 bytes of data RAM are present only in the 8052 family. The lower128 bytes of RAM (00H - 7FH) can be accessed both by direct or indirect addressing while the upper 128 bytes of RAM (80H - FFH) are accessed by indirect addressing.the SFRs (80H - FFH) are accessed by direct addressing only. This feature distinguishes the upper 128 bytes of memory from the SFRs, as shown in fig 5.4. SFR Map The set of Special Function Registers (SFRs) contains important registers such as Accumulator, Register B, I/O Port latch registers, Stack pointer, Data Pointer, Processor Status Word (PSW) and various control registers. Some of these registers are bit addressable (they are marked with a * in the diagram below). The detailed map of various registers is shown in the following figure. Address F8H F0H B* E8H E0H ACC* D8H D0H PSW* C8H (T2CON)* (RCAP2L) (RCAP2H) (TL2) (TH2) C0H B8H IP* B0H P3* A8H IE* A0H P2*

5 SFR Ma 98H SCON* SBUF 90H P1* 88H TCON* TMOD TL0 TL1 TH0 TH1 80H P0* SP DPL DPH PCON (ii)what is timer/counter? Explain the 16-bit timer mode and 8-bit auto reload mode of 8051 microcontroller. (8) (AUC NOV 2012) The microcontroller oscillator uses quartz crystal for its operation. As the frequency of this oscillator is precisely defined and very stable, pulses it generates are always of the same width, which makes them ideal for time measurement. Such crystals are also used in quartz watches. In order to measure time between two events it is sufficient to count up pulses coming from this oscillator. That is exactly what the timer does. If the timer is properly programmed, the value stored in its register will be incremented (or decremented) with each coming pulse, i.e. once per each machine cycle. A single machine-cycle instruction lasts for 12 quartz oscillator periods, which means that by embedding quartz with oscillator frequency of 12MHz, a number stored in the timer register will be changed million times per second, i.e. each microsecond. TMOD Register (Timer Mode) The TMOD register selects the operational mode of the timers T0 and T1. As seen in figure below, the low 4 bits (bit0 - bit3) refer to the timer 0, while the high 4 bits (bit4 - bit7) refer to the timer 1. There are 4 operational modes and each of them is described herein. Bits of this register have the following function: GATE1 enables and disables Timer 1 by means of a signal brought to the INT1 pin (P3.3): 1 - Timer 1 operates only if the INT1 bit is set. 0 - Timer 1 operates regardless of the logic state of the INT1 bit. C/T1 selects pulses to be counted up by the timer/counter 1: 1 - Timer counts pulses brought to the T1 pin (P3.5). 0 - Timer counts pulses from internal oscillator. T1M1,T1M0 These two bits select the operational mode of the Timer 1. T 1 M1 T 1 M0 MODE D ESCRIPTION bit timer

6 bit timer bit auto-reload Split mode GATE0 enables and disables Timer 1 using a signal brought to the INT0 pin (P3.2): 1 - Timer 0 operates only if the INT0 bit is set. 0 - Timer 0 operates regardless of the logic state of the INT0 bit. C/T0 selects pulses to be counted up by the timer/counter 0: 1 - Timer counts pulses brought to the T0 pin (P3.4). 0 - Timer counts pulses from internal oscillator. T0M1,T0M0 These two bits select the operational mode of the Timer 0. T 0 M1 T 0 M0 MODE D ESCRIPTION bit timer bit timer bit auto-reload Split mode Timer 0 in mode 1 (16-bit timer) Mode 1 configures timer 0 as a 16-bit timer comprising all the bits of both registers TH0 and TL0. That's why this is one of the most commonly used modes. Timer operates in the same way as in mode 0, with difference that the registers count up to as allowable by the 16 bits.

7 Timer 0 in mode 2 (Auto-Reload Timer) Mode 2 configures timer 0 as an 8-bit timer. Actually, timer 0 uses only one 8-bit register for counting and never counts from 0, but from an arbitrary value (0-255) stored in another (TH0) register. The following example shows the advantages of this mode. Suppose it is necessary to constantly count up 55 pulses generated by the clock.if mode 1 or mode 0 is used, It is necessary to write the number 200 to the timer registers and constantly check whether an overflow has occured, i.e. whether they reached the value 255. When it happens, it is necessary to rewrite the number 200 and repeat the whole procedure. The same procedure is automatically performed by the microcontroller if set in mode 2. In fact, only the TL0 register operates as a timer, while another (TH0) register stores the value from which the counting starts. When the TL0 register is loaded, instead of being cleared, the contents of TH0 will be reloaded to it. Referring to the previous example, in order to register each 55th pulse, the best solution is to write the number 200 to the TH0 register and configure the timer to operate in mode 2.

8 The 8051 microcontroller has 2 timers/counters called T0 and T1. As their names suggest, their main purpose is to measure time and count external events. Besides, they can be used for generating clock pulses to be used in serial communication, so called Baud Rate. 2. How to interface and display LCD with microcontroller? (AUC MAY 2010) (AUC MAY 2012) (AUC NOV 2012)

9 Liquid crystal display is very important device in embedded system. It offers high flexibility to user as he can display the required data on it. But due to lack of proper approach to LCD interfacing many of them fail. Many people consider LCD interfacing a complex job but according to me LCD interfacing is very easy task, you just need to have a logical approach. This page is to help the enthusiast who wants to interface LCD with through understanding LCD driver is a link between the microcontroller and LCD. First thing to find out in datasheet is the features viz. operating voltage, type of interface, maximum speed for interface in MHz, size of display data RAM, number of pixels, bits per pixel, number of row and columns. You must have the pin diagram of LCD.Pin diagram of LCD driver can be omitted. Major task in LCD interfacing is the initialization sequence. In LCD initialization you have to send command bytes to LCD. Here you set the interface mode, display mode, address counter increment direction, set contrast of LCD, horizontal or vertical addressing mode, color format. This sequence is given in respective LCD driver datasheet. Studying the function set of LCD lets you know the definition of command bytes. It varies from one LCD to another. Next step after initialization is to send data bytes to required display data RAM memory location. Firstly set the address location using address set command byte and than send data bytes using the DDRAM write command. To address specific location in display data RAM one must have the knowledge of how the address counter is incremented. These modules are replacing seven segments and other multi segment LEDs for these purposes. The reasons being: LCDs are economical, easily programmable, have no limitation of displaying special & even custom characters (unlike in seven segments), animations and so on. LCD can be easily interfaced with a microcontroller to display a message or status of a device.

10 3. Explain the registers of 8051 micro controller.(auc NOV 2011)

11 The Accumulator The Accumulator, as its name suggests, is used as a general register to accumulate the results of a large number of instructions. It can hold an 8-bit (1-byte) value and is the most versatile register the 8051 has due to the shear number of instructions that make use of the accumulator. For example, if we want to add the number 10 and 20, the resulting 30 will be stored in the Accumulator. Once have a value in the Accumulator we may continue processing the value or store it in another register or in memory. The "R" registers The "R" registers are a set of eight registers that are named R0, R1, etc. up to and including R7.These registers are used as auxillary registers in many operations. To continue with the above example, perhaps you are adding 10 and 20. The original number 10 may be stored in the Accumulator whereas the value 20 may be stored in, say, register R4. To process the addition execute the command: ADD A,R4 After executing this instruction the Accumulator will contain the value. The Accumulator alone would not be very useful if it were not for these "R" registers.the "R" registers are also used to temporarily store values. For example, to add the values in R1 and R2 together and then subtract the values of R3 and R4. One way to do this would be: MOV A,R3 ;Move the value of R3 into the accumulator ADD A,R4 ;Add the value of R4 MOV R5,A ;Store the resulting value temporarily in R5 MOV A,R1 ;Move the value of R1 into the accumulator ADD A,R2 ;Add the value of R2 SUBB A,R5 ;Subtract the value of R5 (which now contains R3 + R4) we used R5 to temporarily hold the sum of R3 and R4. The "B" Register The "B" register is very similar to the Accumulator in the sense that it may hold an 8- bit (1-byte) value.the "B" register is only used by two 8051 instructions: MUL AB and DIV AB. Thus, if you want to quickly and easily multiply or divide A by another number, you may store the other number in "B" and make use of these two instructions.aside from the MUL and DIV instructions, the "B" register is often used as yet another temporary storage register much like a ninth "R" register. The Data Pointer (DPTR)

12 The Data Pointer (DPTR) is the 8051s only user-accessable 16-bit (2-byte) register. The Accumulator, "R" registers, and "B" register are all 1-byte values.dptr, as the name suggests, is used to point to data. It is used by a number of commands which allow the 8051 to access external memory. When the 8051 accesses external memory it will access external memory at the address indicated by DPTR.While DPTR is most often used to point to data in external memory, many programmers often take advantage of the fact that its the only true 16-bit register available. It is often used to store 2-byte values which have nothing to do with memory locations. The Program Counter (PC) The Program Counter (PC) is a 2-byte address which tells the 8051 where the next instruction to execute is found in memory. When the 8051 is initialized PC always starts at 0000h and is incremented each time an instruction is executed. It is important to note that PC isnt always incremented by one. Since some instructions require 2 or 3 bytes the PC will be incremented by 2 or 3 in these cases.the Program Counter is special in that there is no way to directly modify its value. That is to say, you cant do something like PC=2430h. On the other hand, if we execute LJMP 2430h can effectively accomplished the same thing. The Stack Pointer (SP) The Stack Pointer, like all registers except DPTR and PC, may hold an 8-bit (1-byte) value. The Stack Pointer is used to indicate where the next value to be removed from the stack should be taken from.to push a value onto the stack, the 8051 first increments the value of SP and then stores the value at the resulting memory location.to pop a value off the stack, the 8051 returns the value from the memory location indicated by SP, and then decrements the value of SP. SP is modified directly by the 8051 by six instructions: PUSH, POP, ACALL, LCALL, RET, and RETI. It is also used intrinsically whenever an interrupt is triggered.

13 Port Registers: Input/Output ports named P0, P1, P2 and P3 has got four corresponding port registers with same name P0, P1, P2 and P3. Data must be written into port registers first to send it out to any other external device through ports. Similarly any data received through ports must be read from port registers for performing any operation. All 4 port registers are bit as well as byte addressable. Take a look at the figure below for a better understanding of port registers. Power Management Register This register is used for efficient power management of 8051 micro controller. Commonly referred to as PCON register, this is a dedicated SFR for power management alone. From the figure below you can observe that there are 2 modes for this register :- Idle mode and Power down mode.

14 Processor Status Ward This register reflects the status of the operation that is being carried out in the processor. The picture below shows PSW register and the way register banks are selected using PSW register bits RS1 and RS0. PSW register is both bit and byte addressable. The physical address of PSW starts from D0H. The individual bits are then accessed using D1, D2 D7. 4. How to transfer data between a PC and microcontroller using serial communication? Draw the necessary diagrams and explain. (8) (AUC NOV 2012) UART (Universal Asynchronous Receiver and Transmitter) One of the microcontroller features making it so powerful is an integrated UART, better known as a serial port. It is a full-duplex port, thus being able to transmit and receive data simultaneously and at different baud rates. Without it, serial data send and receive would be an enormously complicated part of the program in which the pin state is constantly changed and checked at regular intervals. When using UART, all the programmer has to do is to simply select serial port mode and baud rate. When it's done, serial data transmit is nothing

15 but writing to the SBUF register, while data receive represents reading the same register. The microcontroller takes care of not making any error during data transmission. Serial port must be configured prior to being used. In other words, it is necessary to determine how many bits is contained in one serial word, baud rate and synchronization clock source. The whole process is in control of the bits of the SCON register (Serial Control). Serial Port Control (SCON) Register SM0 - Serial port mode bit 0 is used for serial port mode selection. SM1 - Serial port mode bit 1. SM2 - Serial port mode 2 bit, also known as multiprocessor communication enable bit. When set, it enables multiprocessor communication in mode 2 and 3, and eventually mode 1. It should be cleared in mode 0. REN - Reception Enable bit enables serial reception when set. When cleared, serial reception is disabled. TB8 - Transmitter bit 8. Since all registers are 8-bit wide, this bit solves the problem of transmiting the 9th bit in modes 2 and 3. It is set to transmit a logic 1 in the 9th bit. RB8 - Receiver bit 8 or the 9th bit received in modes 2 and 3. Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. TI - Transmit Interrupt flag is automatically set at the moment the last bit of one byte is sent. It's a signal to the processor that the line is available for a new byte transmite. It must be cleared from within the software. RI - Receive Interrupt flag is automatically set upon one byte receive. It signals that byte is received and should be read quickly prior to being replaced by a new data. This bit is also cleared from within the software. As seen, serial port mode is selected by combining the SM0 and SM2 bits: S M0 S M1 MODE D ESCRIPTION B A UD RATE bit Shift Register 1/12 the quartz frequency bit UART Determined by the timer bit UART 1/32 the quartz frequency (1/64 the quartz freque

16 bit UART Determined by the timer 1 In mode 0, serial data are transmitted and received through the RXD pin, while the TXD pin output clocks. The bout rate is fixed at 1/12 the oscillator frequency. On transmit, the least significant bit (LSB bit) is sent/received first. TRANSMIT - Data transmit is initiated by writing data to the SBUF register. In fact, this process starts after any instruction being performed upon this register. When all 8 bits have been sent, the TI bit of the SCON register is automatically set. RECEIVE - Data receive through the RXD pin starts upon the two following conditions are met: bit REN=1 and RI=0 (both of them are stored in the SCON register). When all 8 bits have been received, the RI bit of the SCON register is automatically set indicating that one byte receive is complete. Since there are no START and STOP bits or any other bit except data sent from the SBUF register in the pulse sequence, this mode is mainly used when the distance between devices is

17 short, noise is minimized and operating speed is of importance. A typical example is I/O port expansion by adding a cheap IC (shift registers 74HC595, 74HC597 and similar). Mode 1 In mode 1, 10 bits are transmitted through the TXD pin or received through the RXD pin in the following manner: a START bit (always 0), 8 data bits (LSB first) and a STOP bit (always 1). The START bit is only used to initiate data receive, while the STOP bit is automatically written to the RB8 bit of the SCON register. TRANSMIT - Data transmit is initiated by writing data to the SBUF register. End of data transmission is indicated by setting the TI bit of the SCON register. RECEIVE - The START bit (logic zero (0)) on the RXD pin initiates data receive. The following two conditions must be met: bit REN=1 and bit RI=0. Both of them are stored in the SCON register. The RI bit is automatically set upon data reception is complete. The Baud rate in this mode is determined by the timer 1 overflow. Mode 2 In mode 2, 11 bits are transmitted through the TXD pin or received through the RXD pin: a START bit (always 0), 8 data bits (LSB first), a programmable 9th data bit and a STOP bit (always 1). On transmit, the 9th data bit is actually the TB8 bit of the SCON register. This bit usually has a function of parity bit. On receive, the 9th data bit goes into the RB8 bit of the same register (SCON).The baud rate is either 1/32 or 1/64 the oscillator frequency. TRANSMIT - Data transmit is initiated by writing data to the SBUF register. End of data transmission is indicated by setting the TI bit of the SCON register. RECEIVE - The START bit (logic zero (0)) on the RXD pin initiates data receive. The following two conditions must be met: bit REN=1 and bit RI=0. Both of them are stored in the SCON register. The RI bit is automatically set upon data reception is complete. 5. Draw the circuit diagram to interface a keyboard with microcontroller and explain how microcontroller recognizes the key-press. (8)(AUC MAY 2012)(AUC NOV 2011) Interfacing the Keyboard to the 8051

18 keyboards are organized in a matrix of rows and columns. The CPU accesses both rows and column through ports; therefore, with two 8-bit ports, an 8*8 matrix of keys can be connected to a microprocessor. When a key pressed, a row and column make a connect; otherwise, there is no connection between row and column. In IBM PC keyboards, a single microcontroller (consisting of microprocessor, RAM and EPROM, and several ports all on a single chip) takes care of software and hardware interfacing of keyboard. In such systems it is the function of programs stored in the EPROM of microcontroller to scan the keys continuously, identify which one has been activated, and present it to the motherboard. In this section we look at the mechanism by which the 8051 scans and identifies the key. Scanning and identifying the key Figure13.5 shows a 4*4 matrix connected to two ports. The rows are connected to an output port and the columns are connected to an input port. If no key has been pressed, reading the input port will yield 1s for all columns since they are all connected to high (Vcc) If all the rows are grounded and a key is pressed, one of the columns will have 0 since the key pressed provides the path to ground. It is the function of the microcontroller to scan the keyboard continuously to detect and identify the key pressed. How it is done is explained next.

19 Grounding rows and reading columns To detect a pressed key, the microcontroller grounds all rows by providing 0 to the output latch, and then it reads the columns. If the data read from the columns is D3- D0=1111, no key has been pressed and the process continues until a key press is detected. However, if one of the column bits has a zero, this means that a key press has occurred. For example, if D3-D0=1101, this means that a key in the D1 column has been pressed. After a key press is detected, the microcontroller will go through the process of identifying the key. Starting with the top row, the microcontroller grounds it by providing a low to row D0 only; then it reads the columns. If the data read is all1s, no key in that row is activated and the process is moved to the next row. It grounds the next row, reads the columns, and checks for any zero. This process continues until the row is identified. After identification of the row in which the key has been pressed, the next task is to find out which column the pressed key belongs to. This should be easy since the microcontroller knows at any time which row and

20 column are being accessed. Assembly language program for detection and identification of key activation is given below. In this program, it is assumed that P1 and P2 are initialized as output and input, respectively. Program13.1 goes through the following four major stages: 1. To make sure that the preceding key has been released, 0s are output to all rows at once, and the columns are read and checked repeatedly until all the columns are high. When all columns are found to be high, the program waits for a short amount of time before it goes to the next stage of waiting for a key to be pressed. 2) To see if any key is pressed, the columns are scanned over and over in an infinite loop until one of them has a 0 on it. Remember that the output latches connected to rows still have their initial zeros (provided in stage 1), making them grounded. After the key press detection, it waits 20ms for the bounce and then scans the columns again. This serves two functions: (a) it ensures that the first key press detection was not an erroneous one due to spike noise, and(b) the 20ms delay prevents the same key press from being interpreted as a multiple key press. If after the 20-ms delay the key is still pressed, it goes to the next stage to detect which row it belongs to; otherwise, it goes back into the loop to detect a real key press 3) To detect which row the key press belongs to, it grounds one row at a time, reading the columns each time. If it finds that all columns are high, this means that the key press cannot belong to that row; therefore, it grounds the next row and continues until it finds the row the key press belongs to. Upon finding the row that the key press belongs to, it sets up the starting address for the look-up table holding the scan codes (or the ASCII value) for that row and goes to the next stage to identify the key. 4) To identify the key press, it rotates the column bits, one bit at a time, into the carry flag and checks to see if it is low. Upon finding the zero, it pulls out the ASCII code for that key from the look-up table; Otherwise, it increments the pointer to point to the next element of the look-up table.while the key press detection is standard for all

21 keyboards, the process for determining which key is pressed varies. The look-up table method shown in program can be modified to work with any matrix up to 8*8.There are IC chips such as National Semiconductors MM74C923 that incorporate keyboard scanning and decoding all in one chip. Such chips use combinations of counters and logic gates (No microcontroller). ;Keyboard subroutine. This program sends the ASCII code ;for pressed key to P0.1 ;P1.0-P1.3 connected to rows P2.0-P2.3 connected to columns MOV P2,#0FFH ;make P2 an input port K1: MOV P1,#0 ;ground all rows at once MOV A,P2 ;read all col. (ensure all keys open) ANL A, B ;masked unused bits CJNE A,# B,K1 ;check til all keys released K2: ACALL DELAY ;call 20 msec delay MOV A,P2 ;see if any key is pressed ANL A,# B ;mask unused bits CJNE A,# B,OVER ;key pressed, await closure SJMP K2 ;check il key pressed OVER: ACALL DELAY ;wait 20 msec debounce time MOV A,P2 ;check key closure ANL A,# B ;mask unused bits CJNE A,# B,OVER1;key pressed, find row SJMP K2 ;if none, keep polling OVER1: MOV P1,# B ;ground row 0 MOV A,P2 ;read all columns ANL A,# B ;mask unused bits CJNE A,# B,ROW_0;key row 0, find the col. MOV P1,# B ;ground row 1 MOV A,P2 ;read all columns ANL A,# B ;mask unused bits CJNE A,# B,ROW_1;keyrow 1, find the col. MOV P1,# B ;ground row 2 MOV A,P2 ;read all columns ANL A,# B ;mask unused bits CJNE A,# B,ROW_2;key row 2, find the col. MOV P1,# B ;ground row 3 MOV A,P2 ;read all columns ANL A,# B ;mask unused bits CJNE A,# B,ROW_3;keyrow 3, find the col. LJMP K2 ;if none, false input, repeat ROW_0: MOV DPTR,#KCODE0 ;set DPTR=start of row 0 SJMP FIND ;find col. key belongs to ROW_1: MOV DPTR,#KCODE1 ;set DPTR=start of row 1 SJMP FIND ;find col. key belongs to ROW_2: MOV DPTR,#KCODE2 ;set DPTR=start of row 2 SJMP FIND ;find col. key belongs to ROW_3: MOV DPTR,#KCODE3 ;set DPTR=start of row 3 FIND: RRC A ;see if any CY bit low JNC MATCH ;if zero, get the ASCII code

22 INC DPTR SJMP FIND MATCH: CLR A MOVC A,@A+DPTR MOV P0,A LJMP K1 ;point to next col. address ;keep searching ;set A=0 (match is found) ;get ASCII code from table ;display pressed key ;ASCII LOOK-UP TABLE FOR EACH ROW ORG 300H KCODE0: DB '0','1','2','3' ;ROW 0 KCODE1: DB '4','5','6','7' ;ROW 1 KCODE2: DB '8','9','A','B' ;ROW 2 KCODE3: DB 'C','D','E','F' ;ROW 3 END 6. (i)draw the pin diagram of 8051 microcontroller and explain the functions of each pin. (10)(AUC NOV 2010) Pins 1-8: Port 1 Each of these pins can be configured as an input or an output. Pin 9: RS A logic one on this pin disables the microcontroller and clears the contents of most registers. In other words, the positive voltage on this pin resets the

23 microcontroller. By applying logic zero to this pin, the program starts execution from the beginning. Pins10-17: Port 3 Similar to port 1, each of these pins can serve as general input or output. Besides, all of them have alternative functions: Pin 10: RXD Serial asynchronous communication input or Serial synchronous communication output. Pin 11: TXD Serial asynchronous communication output or Serial synchronous communication clock output. Pin 12: INT0 Interrupt 0 input. Pin 13: INT1 Interrupt 1 input. Pin 14: T0 Counter 0 clock input. Pin 15: T1 Counter 1 clock input. Pin 16: WR Write to external (additional) RAM. Pin 17: RD Read from external RAM. Pin 18, 19: X2, X1 Internal oscillator input and output. A quartz crystal which specifies operating frequency is usually connected to these pins. Instead of it, miniature ceramics resonators can also be used for frequency stability. Later versions of microcontrollers operate at a frequency of 0 Hz up to over 50 Hz. Pin 20: GND Ground. Pin 21-28: Port 2 If there is no intention to use external memory then these port pins are configured as general inputs/outputs. In case external memory is used, the higher address byte, i.e. addresses A8-A15 will appear on this port. Even though memory with capacity of 64Kb is not used, which means that not all eight port bits are used for its addressing, the rest of them are not available as inputs/outputs. Pin 29: PSEN If external ROM is used for storing program then a logic zero (0) appears on it every time the microcontroller reads a byte from memory. Pin 30: ALE Prior to reading from external memory, the microcontroller puts the lower address byte (A0-A7) on P0 and activates the ALE output. After receiving signal from the ALE pin, the external register (usually 74HCT373 or 74HCT375 addon chip) memorizes the state of P0 and uses it as a memory chip address. Immediately after that, the ALU pin is returned its previous logic state and P0 is now used as a Data Bus. As seen, port data multiplexing is performed by means of only one additional (and cheap) integrated circuit. In other words, this port is used for both data and address transmission.

24 Pin 31: EA By applying logic zero to this pin, P2 and P3 are used for data and address transmission with no regard to whether there is internal memory or not. It means that even there is a program written to the microcontroller, it will not be executed. Instead, the program written to external ROM will be executed. By applying logic one to the EA pin, the microcontroller will use both memories, first internal then external (if exists). Pin 32-39: Port 0 Similar to P2, if external memory is not used, these pins can be used as general inputs/outputs. Otherwise, P0 is configured as address output (A0-A7) when the ALE pin is driven high (1) or as data output (Data Bus) when the ALE pin is driven low (0). Pin 40: VCC +5V power supply. 7. Briefly write about the IE and IP register in 8051 microcontroller.(6) (AUC NOV 2011) interrupts can be individually enabled or disabled by 'setting' or 'clearing' the corresponding bit in the IE (Interrupt Enable Register) SFR. IE contains a global enable bit EA which enables/disables all interrupts at once. Interrupt Enable register (IE): Address: A8H EX0 ET0 EX1 ET1 ES ET2 EA Setting '1' interrupt (External) enable bit Timer-0 interrupt enable bit interrupt (External) enable bit Timer-1 interrupt enable bit Serial port interrupt enable bit Timer-2 interrupt enable bit Enable/Disable all Enable the corresponding interrupt Setting '0' Disable the corresponding interrupt Priority level structure: Each interrupt source can be programmed to have one of the two priority levels by setting (high priority) or clearing (low priority) a bit in the IP (Interrupt Priority) Register. A low priority interrupt can itself be

25 interrupted by a high priority interrupt, but not by another low priority interrupt. If two interrupts of different priority levels are received simultaneously, the request of higher priority level is served. If the requests of the same priority level are received simultaneously, an internal polling sequence determines which request is to be serviced. Thus, within each priority level, there is a second priority level determined by the polling sequence, as follows. Interrupt Priority register (IP) '0' low priority '1' high priority Interrupt handling: The interrupt flags are sampled at P2 of S5 of every instruction cycle (Note that every instruction cycle has six states each consisting of P1 and P2 pulses). The samples are polled during the next machine cycle (or instruction cycle). If one of the flags was set at S5P2 of the preceding instruction cycle, the polling detects it and the interrupt process generates a long call (LCALL) to the appropriate vector location of the interrupt. The LCALL is generated provided this hardware generated LCALL is not blocked by any one of the following conditions. 1. An interrupt of equal or higher priority level is already in progress. 2. The current polling cycle is not the final cycle in the execution of the instruction in progress. 3. The instruction in progress is RETI or any write to IE or IP registers. When an interrupt comes and the program is directed to the interrupt vector address, the Program Counter (PC) value of the interrupted program is stored (pushed) on the stack. The required Interrupt Service Routine (ISR) is executed. At the end of the ISR, the instruction RETI returns the value of the PC from the stack and the originally interrupted program is resumed. Reset is a non-maskable interrupt. A reset is accomplished by holding the RST pin high for at least two machine cycles. On resetting the program starts from 0000H and some flags are modified as follows - Register PC DPTR A B SP PSW Value(Hex) on Reset 0000H 0000H 00H 00H 07H 00H

26 Ports P0-3 Latches IP IE TCON TMOD TH0 TL0 TH1 TL1 SCON SBUF PCON FFH XXX b 0 XX b 00H 00H 00H 00H 00H 00H 00H XX H 0 XXXX XXX b 8. Explain with a help of a neat block diagram how DAC is interfaced with 8051 microcontroller. (AUC MAY 2011) (AUC NOV 2010) Fig 1 shows DAC0800 series are monolithic 8-bit high-speed current output digitalto-analog converters (DAC) featuring typical settling times of 100 ns.. The noise immune inputs will accept variety of logic levels. The performance and characteristics of the device are essentially unchanged over the ±4.5V to ±18V power supply range and power consumption at only 33 mw with ±5V supplies is independent of logic input levels.

27 Fig 1: pin diagram of DAC 0800 INTERFACING DAC WITH 8051 we now want to convert the Digital signal to analog voltage by using PS/ trainer board. Here we are using DAC The DAC 0800 consists of a 8 data lines and REF voltage lines. When the DAC is given the digital input it converts the Digital data to corresponding current, to convert the I to V we use UA 741. PIN ASSIGNMENT WITH PIN ASSIGNMENT WITH DAC 0800 DAC 0800 PIN DIAGRAM

28 ASSEMBLY PROGRAM TO INTERFACE DAC 0800 WITH 8051 CNTRL : 4003H PORTA : 4000CH

29 MEMORY ADDRESS OPCODE MNEMONICS MOV A, #80H FF 0F MOV DPTR, #CNTRL 8505 F0 A START: MOV A, #00H FF 0C L1: MOV DPTR, #PORTA 850B F0 A 850C 04 INC A 850D 70 F9 CJNE A, #0FF, L1 850F 80 F5 SJMP START 9. Describe the various interrupts and their associated priorities in 8051 Interrupts microcontroller. (AUC NOV 2010) 8051 provides 5 vectored interrupts. They are TF TF1 5. RI/TI Out of these, and are external interrupts whereas Timer and Serial port interrupts are generated int interrupts could be negative edge triggered or low level triggered. All these interrupt, when activated, s interrupt flags. Except for serial interrupt, the interrupt flags are cleared when the processor branches to Routine (ISR). The external interrupt flags are cleared on branching to Interrupt Service Routine (ISR), pro negative edge triggered. For low level triggered external interrupt as well as for serial interrupt, the correspon cleared by software by the programmer. The schematic representation of the interrupts is as follows - Interrupt Location

30 8051 Interrupt Details Each of these interrupts can be individually enabled or disabled by 'setting' or 'clearing' the corresponding b Enable Register) SFR. IE contains a global enable bit EA which enables/disables all interrupts at once. Interrupt Enable register (IE): Address: A8H EX0 ET0 EX1 ET1 ES ET2 EA interrupt (External) enable bit Timer-0 interrupt enable bit interrupt (External) enable bit Timer-1 interrupt enable bit Serial port interrupt enable bit Timer-2 interrupt enable bit Enable/Disable all

31 Setting '1' Enable the corresponding interrupt Setting '0' Disable the corresponding interrupt Priority level structure: Each interrupt source can be programmed to have one of the two priority levels by setting (high priority) or c a bit in the IP (Interrupt Priority) Register. A low priority interrupt can itself be interrupted by a high priority another low priority interrupt. If two interrupts of different priority levels are received simultaneously, t priority level is served. If the requests of the same priority level are received simultaneously, an intern determines which request is to be serviced. Thus, within each priority level, there is a second priority lev polling sequence, as follows. Interrupt Priority register (IP) '0' low priority '1' high priority Interrupt handling: The interrupt flags are sampled at P2 of S5 of every instruction cycle (Note that every instruction cycle consisting of P1 and P2 pulses). The samples are polled during the next machine cycle (or instruction cycle was set at S5P2 of the preceding instruction cycle, the polling detects it and the interrupt process generates to the appropriate vector location of the interrupt. The LCALL is generated provided this hardware gene blocked by any one of the following conditions. 1. An interrupt of equal or higher priority level is already in progress. 2. The current polling cycle is not the final cycle in the execution of the instruction in progress. 3. The instruction in progress is RETI or any write to IE or IP registers. When an interrupt comes and the program is directed to the interrupt vector address, the Program Count interrupted program is stored (pushed) on the stack. The required Interrupt Service Routine (ISR) is execut ISR, the instruction RETI returns the value of the PC from the stack and the originally interrupted program is Reset is a non-maskable interrupt. A reset is accomplished by holding the RST pin high for at least two resetting the program starts from 0000H and some flags are modified as follows - Register PC DPTR A Value(Hex) on Reset 0000H 0000H 00H

32 B SP PSW Ports P0-3 Latches IP IE TCON TMOD TH0 TL0 TH1 TL1 SCON SBUF PCON 00H 07H 00H FFH XXX b 0 XX b 00H 00H 00H 00H 00H 00H 00H XX H 0 XXXX XXX b The schematic diagram of the detection and processing of interrupts is given as follows. Instruction Cycles Interrupt Handling in 8051 It should be noted that the interrupt which is blocked due to the three conditions mentioned before is not re flag that generated interrupt is not still active when the above blocking conditions are removed, i.e.,every pol 10. Explain the internal architecture of an 8051 Micro-controller. (8) Basic 8051 Architecture 8051 employs Harvard architecture. It has some peripherals such as 32 bit digital I/O, Timers and Serial I/O. The basic architecture of 8051 is given in fig 5.1

33 Basic 8051 Architecture Various features of 8051 microcontroller are given as follows. 8-bit CPU 16-bit Program Counter 8-bit Processor Status Word (PSW) 8-bit Stack Pointer Internal RAM of 128bytes Special Function Registers (SFRs) of 128 bytes 32 I/O pins arranged as four 8-bit ports (P0 - P3) Two 16-bit timer/counters : T0 and T1 Two external and three internal vectored interrupts One full duplex serial I/O 8051 Clock and Instruction Cycle In 8051, one instruction cycle consists of twelve (12) clock cycles. Instruction cycle is sometimes called as Machine cycle by some authors. Instruction cycle of 8051 In 8051, each instruction cycle has six states (S 1 - S 6 ). Each state has two pulses (P1 and P2) 128 bytes of Internal RAM Structure (lower address space)

34 Internal RAM Structure The lower 32 bytes are divided into 4 separate banks. Each register bank has 8 registers of one byte each. A register bank is selected depending upon two bank select bits in the PSW register. Next 16bytes are bit addressable. In total, 128bits (16X8) are available in bitaddressable area. Each bit can be accessed and modified by suitable instructions. The bit addresses are from 00H (LSB of the first byte in 20H) to 7FH (MSB of the last byte in 2FH). Remaining 80bytes of RAM are available for general purpose. Internal Data Memory and Special Function Register (SFR) Map Internal Data Memory Map The special function registers (SFRs) are mapped in the upper 128 bytes of internal data memory address. Hence there is an address overlap between the upper 128 bytes of data RAM and SFRs. Please note that the upper 128 bytes of data RAM are present only in the 8052 family. The lower128 bytes of RAM (00H - 7FH) can be accessed both by direct or indirect addressing while the upper 128 bytes of RAM (80H - FFH) are accessed by indirect addressing.the SFRs (80H - FFH) are accessed by direct addressing only. This feature distinguishes the upper 128 bytes of memory from the SFRs, as shown in fig 5.4. SFR Map The set of Special Function Registers (SFRs) contains important registers such as Accumulator, Register B,

35 I/O Port latch registers, Stack pointer, Data Pointer, Processor Status Word (PSW) and various control registers. Some of these registers are bit addressable (they are marked with a * in the diagram below). The detailed map of various registers is shown in the following figure. Address F8H F0H B* E8H E0H ACC* D8H D0H PSW* C8H (T2CON)* (RCAP2L) (RCAP2H) (TL2) (TH2) C0H B8H IP* B0H P3* A8H IE* A0H P2* 98H SCON* 90H P1* SBUF 88H TCON* TMOD TL0 TL1 TH0 TH1 80H P0* SP DPL DPH PCON SFR Map 11. Explain the on- chip timer modes of an 8051 Micro-controller. (AUC NOV 2012) Timers / Counters 8051 has two 16-bit programmable UP timers/counters. They can be configured to operate either as timers or as event counters. The names of the two counters are T0 and T1 respectively. The timer content is available in four 8-bit special function registers, viz, TL0,TH0,TL1 and TH1 respectively.in the "timer" function mode, the counter is incremented in every machine cycle. Thus, one can think of it as counting machine cycles. Hence the clock rate is 1/12 th of the oscillator frequency.in the "counter" function mode, the register is incremented in response to a 1 to 0 transition at its corresponding external input pin (T0 or T1). It requires 2 machine cycles to detect a high to low transition. Hence maximum count rate is 1/24 th of oscillator frequency.the operation of the timers/counters is controlled by two special function registers, TMOD and TCON respectively. Timer Mode control (TMOD) Special Function Register: TMOD register is not bit addressable. TMOD

36 Address: 89 H Various bits of TMOD are described as follows - Gate: This is an OR Gate enabled bit which controls the effect of on START/STOP of Timer. It is set to one ('1') by the program to enable the interrupt to start/stop the timer. If TR1/0 in TCON is set and signal on pin is high then the timer starts counting using either internal clock (timer mode) or external pulses (counter mode). It is used for the selection of Counter/Timer mode. Mode Select Bits: M1 and M0 are mode select bits. Timer/ Counter control logic: Timer control (TCON) Special function register: Fig 8.1 Timer/Counter Control Logic TCON is bit addressable. The address of TCON is 88H. It is partly related to Timer and partly to interrupt.

37 Fig 8.2 TCON Register The various bits of TCON are as follows. TF1 : Timer1 overflow flag. It is set when timer rolls from all 1s to 0s. It is cleared when processor vectors to execute ISR located at address 001BH. TR1 : Timer1 run control bit. Set to 1 to start the timer / counter. TF0 : Timer0 overflow flag. (Similar to TF1) TR0 : Timer0 run control bit. IE1 : Interrupt1 edge flag. Set by hardware when an external interrupt edge is detected. It is cleared when interrupt is processed. IE0 : Interrupt0 edge flag. (Similar to IE1) IT1 : Interrupt1 type control bit. Set/ cleared by software to specify falling edge / low level triggered external interrupt. IT0 : Interrupt0 type control bit. (Similar to IT1) As mentioned earlier, Timers can operate in four different modes. They are as follows Timer Mode-0: In this mode, the timer is used as a 13-bit UP counter as follows. Operation of Timer on Mode-0 The lower 5 bits of TLX and 8 bits of THX are used for the 13 bit count.upper 3 bits of TLX are ignored. When the counter rolls over from all 0's to all 1's, TFX flag is set and an interrupt is generated. The input pulse is obtained from the previous stage. If TR1/0 bit is 1 and Gate bit is 0, the counter continues counting up. If TR1/0 bit is 1 and Gate bit is 1, then the operation of the counter is controlled by input This mode is useful to measure the width of a given pulse fed to input. Timer Mode-1: This mode is similar to mode-0 except for the fact that the Timer operates in 16-bit mode. Operation of Timer in Mode 1 Timer Mode-2: (Auto-Reload Mode) This is a 8 bit counter/timer operation. Counting is performed in TLX while THX stores a constant value. In this mode when the timer overflows i.e. TLX becomes FFH, it is fed with the value stored in THX. For example if we load THX with 50H then the timer in mode 2 will count from 50H to FFH. After that 50H is again reloaded. This mode is useful in applications like fixed time sampling.

38 Operation of Timer in Mode 2 Timer Mode-3: Timer 1 in mode-3 simply holds its count. The effect is same as setting TR1=0. Timer0 in mode-3 establishes TL0 and TH0 as two separate counters. Operation of Timer in Mode 3 Control bits TR1 and TF1 are used by Timer-0 (higher 8 bits) (TH0) in Mode-3 while TR0 and TF0 are available to Timer-0 lower 8 bits(tl0). (ii)explain how interface an 8- bit ADC with 8051 Micro-controller. (8) (AUC MAY 2010) (AUC NOV 2010) INTERFACING ADC804 TO 8051 Signals to be interfaced (on the ADC804) D0-D7, RD, WR, INTR, CS Can do both Memory mapping and IO mapping Memory Mapping (timing is critical) Connect D0-D7 of ADC804 to the data bus of the 8051 system Connect RD, WR of the ADC804 to the 8051 system (ensure polarity) Connect CS of ADC804 to an appropriate address decoder output Connect INTR of ADC804 to an external interrupt Pin on the 8051 (INT0 or INT1) IO Mapping (easiest - I prefer ) Connect D0-D7, RD, WR, CS, INTR to some port bits on the 8051 (12 in all).

39 Algorithm Make CS=0 and send a low-to-high to pin WR to start the conversion. Keep monitoring INTR If INTR =0, the conversion is finished and we can go to the next step. If INTR=1, keep polling until it goes low. After INTR=0, we make CS=0 and send a high-to-low pulse to RD to get the data out of the ADC804 chip. ASSEMBLY LANGUEGE (A51) ADC_IO: mov P1, #0xff ; To configure as input AGAIN clr p3.7 ;Chip select setb P3.6 ;RD=1 clr P3.5 ;WR=0 setb P3.5 ;WR=1- low to high transition WAIT: jb P3.4, WAIT ;wait for INTR clr p3.7 ;generate cs to ADC clr P3.6 ;RD=0 -High to low transition mov A, P1 ;read digital o/p sjmp AGAIN INTERFACING ADC804 TO 8051 ADC808/809 Chip with 8 analog channel. This means this kind of chip allows to monitor 8 different transducers. ADC804 has only ONE analog input: Vin(+). ALE: Latch in the address Start : Start of conversion (same as WR in 804) OE: output enable (same as RD in 804) EOC: End of Conversion (same as INTR in 804)

40 Channel C B A IN0 000 IN1 001 IN2 010 IN3 011 IN4 100 IN5 101 IN6 110 IN7 111 MAHALAKSHMI Algorithm Notice that the ADC808/809 that there is no self-clocking and the clock must be provided from an external source to the CLK pin. (you can use programmable clock oscillator to enable or disable clock by programmable bit. ) Select an analog channel by provide bits to A, B, C. Enable clock Activate ALE with a low-to-high pulse. Activate SC with a high-to-low pulse (start conversion) The conversion is begun on the falling edge of the start conversion pulse. you can use circuit like Monitor EOC Pin.After conversion this pin goes high. Activate OE with a high-to-low pulse to read data out of the ADC chip. 12. Write a note on Jump and Call instructions. Jump and Call Instructions There are 3 types of jump instructions. They are:- 1. Relative Jump 2. Short Absolute Jump 3. Long Absolute Jump Relative Jump Jump that replaces the PC (program counter) content with a new address that is greater than (the address following the jump instruction by 127 or less) or less than (the address following the jump by 128 or less) is called a relative jump. Schematically, the relative jump can be shown as follows: -

41 The advantages of the relative jump are as follows:- Fig 10.1 Relative Jump 1. Only 1 byte of jump address needs to be specified in the 2's complement form, ie. For jumping ahead, the range is 0 to 127 and for jumping back, the range is -1 to Specifying only one byte reduces the size of the instruction and speeds up program execution. 3. The program with relative jumps can be relocated without reassembling to generate absolute jump addresses. Disadvantages of the absolute jump: - 1. Short jump range (-128 to 127 from the instruction following the jump instruction) Instructions that use Relative Jump SJMP <relative address> (The remaining relative jumps are conditional jumps) JC <relative address> JNC <relative address> JB bit, <relative address> JNB bit, <relative address> JBC bit, <relative address> CJNE <destination byte>, <source byte>, <relative address> DJNZ <byte>, <relative address> JZ <relative address> JNZ <relative address> Short Absolute Jump In this case only 11bits of the absolute jump address are needed. The absolute jump address is calculated in the following manner. In 8051, 64 kbyte of program memory space is divided into 32 pages of 2 kbyte each. The hexadecimal addresses of the pages are given as follows:- Page (Hex) Address (Hex) FF FFF FF FFF.. 1E F000 - F7FF 1F F800 - FFFF

42 It can be seen that the upper 5bits of the program counter(pc) hold the page number and the lower 11bits of the PC hold the address within that page. Thus, an absolute address is formed by taking page numbers of the instruction (from the program counter) following the jump and attaching the specified 11bits to it to form the 16-bit address. Advantage: The instruction length becomes 2 bytes. However, difficulty is encountered when the next instruction following the jump instruction begins from a fresh page (at X000H or at X800H). This does not give any problem for the forward jump, but results in an error for the backward jump. In such a case the assembler prompts the user to relocate the program suitably. Example of short absolute jump: - ACALL <address 11> AJMP <address 11> Long Absolute Jump/Call Applications that need to access the entire program memory from 0000H to FFFFH use long absolute jump. Since the absolute address has to be specified in the op-code, the instruction length is 3 bytes (except for A+DPTR). This jump is not re locatable. Example: - LCALL <address 16> LJMP <address 16> 8051 Instructions 13. Explain the instruction set of 8051 microcontroller has about 111 instructions. These can be grouped into the following categories 1. Arithmetic Instructions 2. Logical Instructions 3. Data Transfer instructions 4. Boolean Variable Instructions 5. Program Branching Instructions The following nomenclatures for register, data, address and variables are used while write instructions. A: Accumulator B: "B" register C: Carry bit Rn: Register R0 - R7 of the currently selected register bank Direct: 8-bit internal direct address for data. The data could be in lower 128bytes of RAM (00-7FH) or it could be in the special function register ( bit external or internal RAM address available in register R0 or R1. This is used for indirect addressing mode. #data8: Immediate 8-bit data available in the instruction. #data16: Immediate 16-bit data available in the instruction. Addr11: 11-bit destination address for short absolute jump. Used by instructions AJMP & ACALL. Jump range is 2 kbyte (one page). Addr16: 16-bit destination address for long call or long jump.

43 Rel: 2's complement 8-bit offset (one - byte) used for short jump (SJMP) and all conditional jumps. bit: Directly addressed bit in internal RAM or SFR Arithmetic Instructions Mnemonics Description Bytes Instruction Cycles ADD A, Rn A A + Rn 1 1 ADD A, direct A A + (direct) 2 1 ADD A A 1 1 ADD A, #data A A + data 2 1 ADDC A, Rn A A + Rn + C 1 1 ADDC A, direct A A + (direct) + C 2 1 ADDC A A + C 1 1 ADDC A, #data A A + data + C 2 1 DA A Decimal adjust accumulator 1 1 DIV AB Divide A by B A quotient 1 4 B remainder DEC A A A DEC Rn Rn Rn DEC direct (direct) (direct) @Ri INC A A A INC Rn Rn Rn INC direct (direct) (direct) @Ri INC DPTR DPTR DPTR MUL AB Multiply A by B A low byte (A*B) 1 4 B high byte (A* B) SUBB A, Rn A A - Rn - C 1 1 SUBB A, direct A A - (direct) - C 2 1 SUBB A A - C 1 1 SUBB A, #data A A - data - C 2 1 Logical Instructions Mnemonics Description Bytes Instruction Cycles ANL A, Rn A A AND Rn 1 1 ANL A, direct A A AND (direct) 2 1 ANL A A 1 1 ANL A, #data A A AND data 2 1 ANL direct, A (direct) (direct) AND A 2 1 ANL direct, #data (direct) (direct) AND data 3 2 CLR A A 00H 1 1 CPL A A A 1 1 ORL A, Rn A A OR Rn 1 1 ORL A, direct A A OR (direct) 1 1 ORL A A 2 1 ORL A, #data A A OR data 1 1 ORL direct, A (direct) (direct) OR A 2 1 ORL direct, #data (direct) (direct) OR data 3 2 RL A Rotate accumulator left 1 1 RLC A Rotate accumulator left through carry 1 1 RR A Rotate accumulator right 1 1

44 RRC A Rotate accumulator right through carry 1 1 SWAP A Swap nibbles within Acumulator 1 1 XRL A, Rn A A EXOR Rn 1 1 XRL A, direct A A EXOR (direct) 1 1 XRL A A 2 1 XRL A, #data A A EXOR data 1 1 XRL direct, A (direct) (direct) EXOR A 2 1 XRL direct, #data (direct) (direct) EXOR data 3 2 Data Transfer Instructions Mnemonics Description Bytes Instruction Cycles MOV A, Rn A Rn 1 1 MOV A, direct A (direct) 2 1 MOV 1 1 MOV A, #data A data 2 1 MOV Rn, A Rn A 1 1 MOV Rn, direct Rn (direct) 2 2 MOV Rn, #data Rn data 2 1 MOV direct, A (direct) A 2 1 MOV direct, Rn (direct) Rn 2 2 MOV direct1, direct2 (direct1) (direct2) 3 2 MOV 2 2 MOV direct, #data (direct) #data 3 2 A 1 1 (direct) 2 2 data 2 1 MOV DPTR, #data16 DPTR data MOVC A Code byte pointed by A + DPTR 1 2 MOVC A Code byte pointed by A + PC 1 2 MOVC A Code byte pointed by Ri 8-bit address) 1 2 MOVX A External data pointed by DPTR 1 2 A (External data - 8bit address) 1 2 A(External data - 16bit address) 1 2 PUSH direct (SP) (direct) 2 2 POP direct (direct) (SP) 2 2 XCH Rn Exchange A with Rn 1 1 XCH direct Exchange A with direct byte 2 1 Exchange A with indirect RAM 1 1 XCHD Exchange least significant nibble of A with that of indirect RAM 1 1 Boolean Variable Instructions Mnemonics Description Bytes Instruction Cycles CLR C C-bit CLR bit bit SET C C SET bit bit CPL C C 1 1 CPL bit bit 2 1 ANL C, /bit C C. 2 1 ANL C, bit C C. bit 2 1

45 ORL C, /bit C C ORL C, bit C C + bit 2 1 MOV C, bit C bit 2 1 MOV bit, C bit C 2 2 Program Branching Instructions Mnemonics Description Bytes Instruction Cycles ACALL addr11 PC + 2 (SP) ; addr 11 PC 2 2 AJMP addr11 Addr11 PC 2 2 CJNE A, direct, rel Compare with A, jump (PC + rel) if not equal 3 2 CJNE A, #data, rel Compare with A, jump (PC + rel) if not equal 3 2 CJNE Rn, #data, rel Compare with Rn, jump (PC + rel) if not equal 3 2 #data, rel Compare A, jump (PC + rel) if not equal 3 2 DJNZ Rn, rel Decrement Rn, jump if not zero 2 2 DJNZ direct, rel Decrement (direct), jump if not zero 3 2 JC rel Jump (PC + rel) if C bit = JNC rel Jump (PC + rel) if C bit = JB bit, rel Jump (PC + rel) if bit = JNB bit, rel Jump (PC + rel) if bit = JBC bit, rel Jump (PC + rel) if bit = A+DPTR PC 1 2 JZ rel If A=0, jump to PC + rel 2 2 JNZ rel If A 0, jump to PC + rel 2 2 LCALL addr16 PC + 3 (SP), addr16 PC 3 2 LJMP addr 16 Addr16 PC 3 2 NOP No operation 1 1 RET (SP) PC 1 2 RETI (SP) PC, Enable Interrupt 1 2 SJMP rel PC rel PC 2 2 A+DPTR PC 1 2 JZ rel If A = 0. jump PC+ rel 2 2 JNZ rel If A 0, jump PC + rel 2 2 NOP No operation Explain the I/O Port configuration of 8051 microcontroller. I/O Port Configuration Each port of 8051 has bidirectional capability. Port 0 is called 'true bidirectional port' as it floats (tristated) when configured as input. Port-1, 2, 3 are called 'quasi bidirectional port'. Port-0 Pin Structure Port -0 has 8 pins (P0.0-P0.7). The structure of a Port-0 pin is shown in fig 6.2.

46 Port-0 Structure Port-0 can be configured as a normal bidirectional I/O port or it can be used for address/data interfacing for accessing external memory. When control is '1', the port is used for address/data interfacing. When the control is '0', the port can be used as a normal bidirectional I/O port. Let us assume that control is '0'. When the port is used as an input port, '1' is written to the latch. In this situation both the output MOSFETs are 'off'. Hence the output pin floats. This high impedance pin can be pulled up or low by an external source. When the port is used as an output port, a '1' written to the latch again turns 'off' both the output MOSFETs and causes the output pin to float. An external pull-up is required to output a '1'. But when '0' is written to the latch, the pin is pulled down by the lower MOSFET. Hence the output becomes zero. When the control is '1', address/data bus controls the output driver MOSFETs. If the address/data bus (internal) is '0', the upper MOSFET is 'off' and the lower MOSFET is 'on'. The output becomes '0'. If the address/data bus is '1', the upper transistor is 'on' and the lower transistor is 'off'. Hence the output is '1'. Hence for normal address/data interfacing (for external memory access) no pull-up resistors are required. Port-0 latch is written to with 1's when used for external memory access. Port-1 Pin Structure Port-1 has 8 pins (P1.1-P1.7).The structure of a port-1 pin is shown in fig 6.3.

47 Port 1 Structure Port-1 does not have any alternate function i.e. it is dedicated solely for I/O interfacing. When used as output port, the pin is pulled up or down through internal pull-up. To use port-1 as input port, '1' has to be written to the latch. In this input mode when '1' is written to the pin by the external device then it read fine. But when '0 is written to the pin by the external device then the external source must sink current due to internal pull-up If the external device is not able to sink the current the pin voltage may rise, leading to a possible wrong reading. PORT 2 Pin Structure Port-2 has 8-pins (P2.0-P2.7). The structure of a port-2 pin is shown in fig 6.4.

e-pg Pathshala Subject : Computer Science Paper: Embedded System Module: 8051 Architecture Module No: CS/ES/5 Quadrant 1 e-text

e-pg Pathshala Subject : Computer Science Paper: Embedded System Module: 8051 Architecture Module No: CS/ES/5 Quadrant 1 e-text e-pg Pathshala Subject : Computer Science Paper: Embedded System Module: 8051 Architecture Module No: CS/ES/5 Quadrant 1 e-text In this lecture the detailed architecture of 8051 controller, register bank,

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