omputer Design Concept adao Nakamura
|
|
- Dylan Johnson
- 5 years ago
- Views:
Transcription
1 omputer Design Concept adao Nakamura
2 1 1 Pascal s Calculator
3 Leibniz s Calculator
4 Babbage s Calculator
5 Von Neumann Computer
6 Flynn s Classification of Computer Architecture
7 Microprocessor Design Process
8 Information to Adapt the Specification Requirement Clarification of the Requirement Specification Conceptual Design Concept Upgrade and Improve Design Stems of Mechanical Engineering
9 Number of Transistors (K) 1,000, ,000 10,000 Pentium 1, i Time Moore s Law 4.3 Billion Transistors in 2014 Pentium II Pentium III Pentium Pro
10 8-bit internal data bus Accumulator A Status Register SR ALU B D C E Instruction Register IR Clock Generator Control Circuits.., Internal Control Lines H L Stack Pointer SP Program Counter PC Serial IO Port Serial IO... External Control Data Register DR Address Buffer Address AD 0 -AD 7 / Data Address AD 8 -AD 15 Structure of Intel s Microprocessor 8085
11 1 10 Simple Model of von Neumann Computers
12 Cycles per Instruction CPI Scalar CISC Superscalar RISC VLIW Superpipeline Scalar RISC Frequency MHz 11 Distribution of Processors in Cycle per Instruction
13 Clock Cycles DE DE DE DE DE DE DE DE DE : Instruction Fetch DE: Decode & Operand Fetch : Execution : Write Back Instructions Superscalar Processor 12 Pipeline Execution in a Superscalar Processor
14 Clock Cycles DE DE : Instruction Fetch DE: Decode & Operand Fetch : Execution : Write Back DE 8 9 Instructions VLIW Processor 1 13 Pipeline Execution in a VLIW Processor
15 Instructions Clock Cycles DE DE DE DE DE DE : Instruction Fetch DE: Decode & Operand Fetch : Execution : Write Back Superpipeline Processor 14 Pipeline Execution in a Superpipeline Processor
16 Main Memory Switch CPU CPU CPU (a) Multiprocessor System Switch CPU CPU CPU Main Memory Main Memory Main Memory (b) Multicomputer System 15 Parallel Computers
17 X=x1E+x2 Y=y1E-y2 Compare exponents Shift Add Normalize Z=X+Y (a) Floating Point Arithmetic Pipeline X1,Y1 Z1 X1,Y1 Z1 X2,Y2 Z2 X2,Y2 Z2 X3,Y3 Z3 X3,Y3 Z3 1 clock / 1 result (one processor) 4 clocks / 3 results (3 processors) (b) Pipeline Processing (c) Array Processing 16 Floating Point Arithmetic Processing
18 (a) Scheme of SIMD (b) Scheme of MISD 17 Some Duality of SIMD and MISD
19 CPU Memory Vector Register Arithmetic Pipeline (a) Vector Computer Memory S W I CPU C ac Local Memory Register (File) T C h e ALU H (b) Parallel Computere 18 Comparison of Vector and Parallel Computers
20 19 Scalar and Vector Processing in Applications
21 NOVEL PROGRAMMING LANGUAGE SUPPORT SOFTWARE PARALLEL APPLICATIONS AND ALGORITHMS PARALLEL ARCHITECTURE(S) Paradigm for Application-Driven Parallel Processing
22 Relations among algorithm, computation model and architecture
23 More General Relations among algorithm, computation model and architecture
24 Specification Domain Architecure Domain Conceptual Design Design Concept = Computer Architecture Software Design & Production Domain Machine Instructions Assembler & Assembly Language Semiconductor-Physical Design of Circuit with Devices Chip Implementation CHIP Operating System Compiler High-Level Language Design Flow of Microprocessors
25 Hierarchy of Computer Architecture
26 c0 (ADD) ALU M A I N M E M O R Y c1 (READ) c2 (WRITE) D R c6 c4 c7 AC c3 c5 c8 A R PC c10 c9 IR CONTROL UNIT c0 c1 c10 1 Structure of a Simple CPU
27 Control signal c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 Microoperation AC AC + DR DR M(AR)(READ M) M(AR) DR(WRITE M) RIGHT-SHT AC DR AC AC DR AR DR(ADR) PC DR(ADR) IR DR(OP) PC PC + 1 AR PC 2 Control Signals of the Simple CPU
28 Begin CPU active? No End Yes AR PC READ M PC PC + 1 IR DR(OP) Decode OP Fetch cycle AC = Accumulator AR = Memory address register DR = Memory data register DR(OP) = Opecode field of DR DR(ADR) = Address field of DR IR = Instruction register M = Main memory PC = Program counter LOAD ADD JUMP AR DR(ADR) READ M AR DR(ADR) READ M Execute cycle AC DR AC AC + DR PC DR(ADR) 3 Operation of an Three-Instruction CPU
29 External Address Source Control Memory Address Registar Control Memory 1 to 8 Decoder S a 2 a 1 a 0 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 External Condition Address Field Control Signals
30 Microprogram 1 FETCH: Microprogram 2 LOAD: Microprogram 3 ADD: Microprogram 4 JUMP: AR PC; READ M; PC PC + 1, IR DR(OP); go to IR; AR DR(ADR); READ M; AC DR; go to FETCH; AR DR(ADR); READ M; AC AC + DR; go to FETCH; PC DR(ADR); go to FETCH; 5 Examples of Microprogarams
31 Multiplexer External Conditions External Address PC Control Memory CM Microinstruction Register IR Decorder Control Signals 6 Microprogrammed Control Unit
32 Condition Select Branch Address Control Fields for Control Signals 7 Microinstraction Format
33 From Instruction Register IR Microprogram Control Unit Control Memory Microinstruction Register npc Nanoprogram Control Unit Control Memory ncm Nanoinstruction Register nir Control Signals 8 Microprogram and Nanoprogram followed
34 ID OF ID OF Ex : : : : Instruction Fetch Instruction Decode Operand Fetch Execution 9 CISC Instruction Pipeline
35 Clock Stage Clock Register File Register File Mux B OF Stage Mux B Stage Function Unit Function Unit Mux D Stage Mux D (a) Conventional Datapath (b) Pipelined Datapath 10 Tadapath Timing
36 Clock Cycle 1 Clock Cycle 2 w x y z w: The control signals are set up. x: The registers are loaded onto the input buses. y: The ALU operates. z: The results back to registers through the output bus. One Datapath Cycle
37 Microoperation Clock Cycle OF OF OF OF OF OF OF 3 12 Pipeline Execution for Microoperation Sequence
38 Clock Cycles DE DE DE Datapath Domain 4 DE 5 DE 6 DE Instructions : Instruction Fetch DE: Decode and Operand Fetch : Execution : Write Back Control Unit Domain 13 Control Unit and Datapath Domains in Pipelining
39
40 ID MEM ID Ex MEM : : : : Instruction Fetch Instruction Decode Execution Memory Read / Write : Write Back 1 RISC Instruction pipeline
41 PC stage Instruction memory IR Register file DOF stage Instruction decoder Zero fill MUX Data Control Address stage Function unit Data memory Data Address stage MUX Data memory Control Datapath Register file
42 U Reg A B C ALU U Reg A B C ALU U Reg A B C ALU U Reg A B C ALU U Reg A B C ALU U Reg A B C ALU U Reg A B C ALU U Reg A B C ALU U Reg A B C ALU U Reg A B C ALU U Reg A B C ALU U Reg A B C ALU U Reg A B C ALU U Reg A B C ALU U Reg A B C ALU U A B C ALU Reg INSTRUCTION Process of How A Pipeline Works
43 1 Model of a Superscalar Processor
44 Program Instruction Fetch & Branch Prediction Window of Execution Instruction Execution Instruction Reorder & Commit Instruction Dispatch Instruction Issue 18 General Model of Superscalar Processors
45 C = A + B C = A + B E = C + D E = C + D D = F + G J = F + G D = H + I K = H + I 19 Data Dependency
46 MOV R1, R5 R1<= R5 ID ADD R2,R1,R6 R2<=R1+R6 ID ADD R3,R1,R2 R3<=R1+R2 ID A Data Hazard Problem
47 MOV R1, R5 ID NOP ID ADD R2,R1,R6 ID NOP ID ADD R3,R1,R2 ID [NOP]:NOPs IN CASE OF SOFTWARE SOLUTION :BUBBLES IN CASE OF HARDWARE SOLUTION 2 Program-Based and Hardware Solutions
48 1 BZ R1,18 ID 2 MOV R2,R3 [NOP] ID 3 MOV R1,R2 [NOP] ID 4 MOV R5,R6 ID [NOP]:NOPs IN CASE OF SOFTWARE SOLUTION :BUBBLEs IN CASE OF HARDWARE SOLUTION 2 Control Hazard and Its Solution
49 Cycle Decode Execute Write I1 I3 I3 I5 I2 I4 I4 I4 I6 I6 I1 I1 I2 I5 I6 I3 I4 I1 I3 I5 I2 I4 I6 2 In Order Issue - In Order Completion
50 Cycle Decode Execute Write I1 I3 I5 I2 I4 I4 I6 I6 I1 I1 I2 I5 I6 I3 I4 I2 I1 I4 I5 I6 I3 2 In Order Issue - Out of Order Completion
51 1 I3 I4 I1 I2 ID 2 3 n INSTRUCTION ISSUE NEYWORK 2 In Order Issue Out of Order Completion Structure
52 Cycle Decode Window Execute Write I1 I3 I5 I2 I4 I6 I1, I2 I3, I4 I4, I5, I6 I5 I1 I1 I2 I6 I5 I3 I4 I2 I1 I4 I5 I3 I6 2 Out of Order Issue - Out of Order Completion
Lecture1: introduction. Outline: History overview Central processing unite Register set Special purpose address registers Datapath Control unit
Lecture1: introduction Outline: History overview Central processing unite Register set Special purpose address registers Datapath Control unit 1 1. History overview Computer systems have conventionally
More informationArchitectures & instruction sets R_B_T_C_. von Neumann architecture. Computer architecture taxonomy. Assembly language.
Architectures & instruction sets Computer architecture taxonomy. Assembly language. R_B_T_C_ 1. E E C E 2. I E U W 3. I S O O 4. E P O I von Neumann architecture Memory holds data and instructions. Central
More informationProcessing Unit CS206T
Processing Unit CS206T Microprocessors The density of elements on processor chips continued to rise More and more elements were placed on each chip so that fewer and fewer chips were needed to construct
More informationBasic Computer Architecture
Basic Computer Architecture CSCE 496/896: Embedded Systems Witawas Srisa-an Review of Computer Architecture Credit: Most of the slides are made by Prof. Wayne Wolf who is the author of the textbook. I
More informationClass Notes. Dr.C.N.Zhang. Department of Computer Science. University of Regina. Regina, SK, Canada, S4S 0A2
Class Notes CS400 Part VI Dr.C.N.Zhang Department of Computer Science University of Regina Regina, SK, Canada, S4S 0A2 C. N. Zhang, CS400 83 VI. CENTRAL PROCESSING UNIT 1 Set 1.1 Addressing Modes and Formats
More informationComputer Architecture
Computer Architecture Slide Sets WS 2013/2014 Prof. Dr. Uwe Brinkschulte M.Sc. Benjamin Betting Part 3 Fundamentals in Computer Architecture Computer Architecture Part 3 page 1 of 55 Prof. Dr. Uwe Brinkschulte,
More informationTHE MICROPROCESSOR Von Neumann s Architecture Model
THE ICROPROCESSOR Von Neumann s Architecture odel Input/Output unit Provides instructions and data emory unit Stores both instructions and data Arithmetic and logic unit Processes everything Control unit
More informationRAČUNALNIŠKEA COMPUTER ARCHITECTURE
RAČUNALNIŠKEA COMPUTER ARCHITECTURE 6 Central Processing Unit - CPU RA - 6 2018, Škraba, Rozman, FRI 6 Central Processing Unit - objectives 6 Central Processing Unit objectives and outcomes: A basic understanding
More informationCOURSE DESCRIPTION. CS 232 Course Title Computer Organization. Course Coordinators
COURSE DESCRIPTION Dept., Number Semester hours CS 232 Course Title Computer Organization 4 Course Coordinators Badii, Joseph, Nemes 2004-2006 Catalog Description Comparative study of the organization
More informationstructural RTL for mov ra, rb Answer:- (Page 164) Virtualians Social Network Prepared by: Irfan Khan
Solved Subjective Midterm Papers For Preparation of Midterm Exam Two approaches for control unit. Answer:- (Page 150) Additionally, there are two different approaches to the control unit design; it can
More informationEC 513 Computer Architecture
EC 513 Computer Architecture Complex Pipelining: Superscalar Prof. Michel A. Kinsy Summary Concepts Von Neumann architecture = stored-program computer architecture Self-Modifying Code Princeton architecture
More informationLatches. IT 3123 Hardware and Software Concepts. Registers. The Little Man has Registers. Data Registers. Program Counter
IT 3123 Hardware and Software Concepts Notice: This session is being recorded. CPU and Memory June 11 Copyright 2005 by Bob Brown Latches Can store one bit of data Can be ganged together to store more
More informationASSEMBLY LANGUAGE MACHINE ORGANIZATION
ASSEMBLY LANGUAGE MACHINE ORGANIZATION CHAPTER 3 1 Sub-topics The topic will cover: Microprocessor architecture CPU processing methods Pipelining Superscalar RISC Multiprocessing Instruction Cycle Instruction
More informationMICROPROGRAMMED CONTROL
MICROPROGRAMMED CONTROL Hardwired Control Unit: When the control signals are generated by hardware using conventional logic design techniques, the control unit is said to be hardwired. Micro programmed
More informationEN164: Design of Computing Systems Lecture 24: Processor / ILP 5
EN164: Design of Computing Systems Lecture 24: Processor / ILP 5 Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Brown University
More informationLecture 26: Parallel Processing. Spring 2018 Jason Tang
Lecture 26: Parallel Processing Spring 2018 Jason Tang 1 Topics Static multiple issue pipelines Dynamic multiple issue pipelines Hardware multithreading 2 Taxonomy of Parallel Architectures Flynn categories:
More informationEE 4980 Modern Electronic Systems. Processor Advanced
EE 4980 Modern Electronic Systems Processor Advanced Architecture General Purpose Processor User Programmable Intended to run end user selected programs Application Independent PowerPoint, Chrome, Twitter,
More informationCOMPUTER ORGANIZATION AND ARCHITECTURE
Page 1 1. Which register store the address of next instruction to be executed? A) PC B) AC C) SP D) NONE 2. How many bits are required to address the 128 words of memory? A) 7 B) 8 C) 9 D) NONE 3. is the
More informationTi Parallel Computing PIPELINING. Michał Roziecki, Tomáš Cipr
Ti5317000 Parallel Computing PIPELINING Michał Roziecki, Tomáš Cipr 2005-2006 Introduction to pipelining What is this What is pipelining? Pipelining is an implementation technique in which multiple instructions
More informationComputer Architecture
Computer Architecture Lecture 1: Digital logic circuits The digital computer is a digital system that performs various computational tasks. Digital computers use the binary number system, which has two
More information2 MARKS Q&A 1 KNREDDY UNIT-I
2 MARKS Q&A 1 KNREDDY UNIT-I 1. What is bus; list the different types of buses with its function. A group of lines that serves as a connecting path for several devices is called a bus; TYPES: ADDRESS BUS,
More informationMicro-programmed Control Ch 15
Micro-programmed Control Ch 15 Micro-instructions Micro-programmed Control Unit Sequencing Execution Characteristics 1 Hardwired Control (4) Complex Fast Difficult to design Difficult to modify Lots of
More informationMachine Instructions vs. Micro-instructions. Micro-programmed Control Ch 15. Machine Instructions vs. Micro-instructions (2) Hardwired Control (4)
Micro-programmed Control Ch 15 Micro-instructions Micro-programmed Control Unit Sequencing Execution Characteristics 1 Machine Instructions vs. Micro-instructions Memory execution unit CPU control memory
More informationWhat is Superscalar? CSCI 4717 Computer Architecture. Why the drive toward Superscalar? What is Superscalar? (continued) In class exercise
CSCI 4717/5717 Computer Architecture Topic: Instruction Level Parallelism Reading: Stallings, Chapter 14 What is Superscalar? A machine designed to improve the performance of the execution of scalar instructions.
More informationMicro-programmed Control Ch 17
Micro-programmed Control Ch 17 Micro-instructions Micro-programmed Control Unit Sequencing Execution Characteristics Course Summary 1 Hardwired Control (4) Complex Fast Difficult to design Difficult to
More informationMicro-programmed Control Ch 15
Micro-programmed Control Ch 15 Micro-instructions Micro-programmed Control Unit Sequencing Execution Characteristics 1 Hardwired Control (4) Complex Fast Difficult to design Difficult to modify Lots of
More informationHardwired Control (4) Micro-programmed Control Ch 17. Micro-programmed Control (3) Machine Instructions vs. Micro-instructions
Micro-programmed Control Ch 17 Micro-instructions Micro-programmed Control Unit Sequencing Execution Characteristics Course Summary Hardwired Control (4) Complex Fast Difficult to design Difficult to modify
More informationDigital System Design Using Verilog. - Processing Unit Design
Digital System Design Using Verilog - Processing Unit Design 1.1 CPU BASICS A typical CPU has three major components: (1) Register set, (2) Arithmetic logic unit (ALU), and (3) Control unit (CU) The register
More informationPIPELINING AND VECTOR PROCESSING
1 PIPELINING AND VECTOR PROCESSING Parallel Processing Pipelining Arithmetic Pipeline Instruction Pipeline RISC Pipeline Vector Processing Array Processors 2 PARALLEL PROCESSING Parallel Processing Execution
More informationWhat Are The Main Differences Between Program Counter Pc And Instruction Register Ir
What Are The Main Differences Between Program Counter Pc And Instruction Register Ir and register-based instructions - Anatomy on a CPU - Program Counter (PC): holds memory address of next instruction
More informationEN164: Design of Computing Systems Topic 06.b: Superscalar Processor Design
EN164: Design of Computing Systems Topic 06.b: Superscalar Processor Design Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Brown
More informationRISC Processors and Parallel Processing. Section and 3.3.6
RISC Processors and Parallel Processing Section 3.3.5 and 3.3.6 The Control Unit When a program is being executed it is actually the CPU receiving and executing a sequence of machine code instructions.
More informationProcessor Architecture. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University
Processor Architecture Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Moore s Law Gordon Moore @ Intel (1965) 2 Computer Architecture Trends (1)
More informationA superscalar machine is one in which multiple instruction streams allow completion of more than one instruction per cycle.
CS 320 Ch. 16 SuperScalar Machines A superscalar machine is one in which multiple instruction streams allow completion of more than one instruction per cycle. A superpipelined machine is one in which a
More informationAdvanced d Instruction Level Parallelism. Computer Systems Laboratory Sungkyunkwan University
Advanced d Instruction ti Level Parallelism Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu ILP Instruction-Level Parallelism (ILP) Pipelining:
More informationChapter 3 : Control Unit
3.1 Control Memory Chapter 3 Control Unit The function of the control unit in a digital computer is to initiate sequences of microoperations. When the control signals are generated by hardware using conventional
More informationChapter 2: Data Manipulation
Chapter 2 Data Manipulation Computer Science An Overview Tenth Edition by J. Glenn Brookshear Presentation files modified by Farn Wang Chapter 2 Data Manipulation 2.1 Computer Architecture 2.2 Machine
More informationComputer Architecture Programming the Basic Computer
4. The Execution of the EXCHANGE Instruction The EXCHANGE routine reads the operand from the effective address and places it in DR. The contents of DR and AC are interchanged in the third microinstruction.
More informationREGISTER TRANSFER LANGUAGE
REGISTER TRANSFER LANGUAGE The operations executed on the data stored in the registers are called micro operations. Classifications of micro operations Register transfer micro operations Arithmetic micro
More informationProcessor Architecture
Processor Architecture Jinkyu Jeong (jinkyu@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong (jinkyu@skku.edu)
More informationINTEL Architectures GOPALAKRISHNAN IYER FALL 2009 ELEC : Computer Architecture and Design
INTEL Architectures GOPALAKRISHNAN IYER FALL 2009 GBI0001@AUBURN.EDU ELEC 6200-001: Computer Architecture and Design Silicon Technology Moore s law Moore's Law describes a long-term trend in the history
More informationThe Processor: Instruction-Level Parallelism
The Processor: Instruction-Level Parallelism Computer Organization Architectures for Embedded Computing Tuesday 21 October 14 Many slides adapted from: Computer Organization and Design, Patterson & Hennessy
More informationWilliam Stallings Computer Organization and Architecture
William Stallings Computer Organization and Architecture Chapter 16 Control Unit Operations Rev. 3.2 (2009-10) by Enrico Nardelli 16-1 Execution of the Instruction Cycle It has many elementary phases,
More informationWilliam Stallings Computer Organization and Architecture 8 th Edition. Chapter 14 Instruction Level Parallelism and Superscalar Processors
William Stallings Computer Organization and Architecture 8 th Edition Chapter 14 Instruction Level Parallelism and Superscalar Processors What is Superscalar? Common instructions (arithmetic, load/store,
More informationCHETTINAD COLLEGE OF ENGINEERING AND TECHNOLOGY COMPUTER ARCHITECURE- III YEAR EEE-6 TH SEMESTER 16 MARKS QUESTION BANK UNIT-1
CHETTINAD COLLEGE OF ENGINEERING AND TECHNOLOGY COMPUTER ARCHITECURE- III YEAR EEE-6 TH SEMESTER 16 MARKS QUESTION BANK UNIT-1 Data representation: (CHAPTER-3) 1. Discuss in brief about Data types, (8marks)
More informationMicrocomputer Architecture and Programming
IUST-EE (Chapter 1) Microcomputer Architecture and Programming 1 Outline Basic Blocks of Microcomputer Typical Microcomputer Architecture The Single-Chip Microprocessor Microprocessor vs. Microcontroller
More informationLECTURE 10. Pipelining: Advanced ILP
LECTURE 10 Pipelining: Advanced ILP EXCEPTIONS An exception, or interrupt, is an event other than regular transfers of control (branches, jumps, calls, returns) that changes the normal flow of instruction
More informationProcessor (IV) - advanced ILP. Hwansoo Han
Processor (IV) - advanced ILP Hwansoo Han Instruction-Level Parallelism (ILP) Pipelining: executing multiple instructions in parallel To increase ILP Deeper pipeline Less work per stage shorter clock cycle
More informationAdvanced Parallel Architecture Lesson 3. Annalisa Massini /2015
Advanced Parallel Architecture Lesson 3 Annalisa Massini - 2014/2015 Von Neumann Architecture 2 Summary of the traditional computer architecture: Von Neumann architecture http://williamstallings.com/coa/coa7e.html
More informationThe von Neumann Architecture. IT 3123 Hardware and Software Concepts. The Instruction Cycle. Registers. LMC Executes a Store.
IT 3123 Hardware and Software Concepts February 11 and Memory II Copyright 2005 by Bob Brown The von Neumann Architecture 00 01 02 03 PC IR Control Unit Command Memory ALU 96 97 98 99 Notice: This session
More informationQUESTION BANK UNIT-I. 4. With a neat diagram explain Von Neumann computer architecture
UNIT-I 1. Write the basic functional units of computer? (Nov/Dec 2014) 2. What is a bus? What are the different buses in a CPU? 3. Define multiprogramming? 4.List the basic functional units of a computer?
More informationSuperscalar Processing (5) Superscalar Processors Ch 14. New dependency for superscalar case? (8) Output Dependency?
Superscalar Processors Ch 14 Limitations, Hazards Instruction Issue Policy Register Renaming Branch Prediction PowerPC, Pentium 4 1 Superscalar Processing (5) Basic idea: more than one instruction completion
More informationSuperscalar Processors Ch 14
Superscalar Processors Ch 14 Limitations, Hazards Instruction Issue Policy Register Renaming Branch Prediction PowerPC, Pentium 4 1 Superscalar Processing (5) Basic idea: more than one instruction completion
More informationCOSC 122 Computer Fluency. Computer Organization. Dr. Ramon Lawrence University of British Columbia Okanagan
COSC 122 Computer Fluency Computer Organization Dr. Ramon Lawrence University of British Columbia Okanagan ramon.lawrence@ubc.ca Key Points 1) The standard computer (von Neumann) architecture consists
More informationChapter 4. MARIE: An Introduction to a Simple Computer 4.8 MARIE 4.8 MARIE A Discussion on Decoding
4.8 MARIE This is the MARIE architecture shown graphically. Chapter 4 MARIE: An Introduction to a Simple Computer 2 4.8 MARIE MARIE s Full Instruction Set A computer s control unit keeps things synchronized,
More informationChapter 4. Chapter 4 Objectives
Chapter 4 MARIE: An Introduction to a Simple Computer Chapter 4 Objectives Learn the components common to every modern computer system. Be able to explain how each component contributes to program execution.
More informationChapter 05: Basic Processing Units Control Unit Design. Lesson 15: Microinstructions
Chapter 05: Basic Processing Units Control Unit Design Lesson 15: Microinstructions 1 Objective Understand that an instruction implement by sequences of control signals generated by microinstructions in
More informationAdvanced Parallel Architecture Lesson 3. Annalisa Massini /2015
Advanced Parallel Architecture Lesson 3 Annalisa Massini - Von Neumann Architecture 2 Two lessons Summary of the traditional computer architecture Von Neumann architecture http://williamstallings.com/coa/coa7e.html
More informationBlog - https://anilkumarprathipati.wordpress.com/
Control Memory 1. Introduction The function of the control unit in a digital computer is to initiate sequences of microoperations. When the control signals are generated by hardware using conventional
More informationInstruction Pipelining
Instruction Pipelining Simplest form is a 3-stage linear pipeline New instruction fetched each clock cycle Instruction finished each clock cycle Maximal speedup = 3 achieved if and only if all pipe stages
More informationMARIE: An Introduction to a Simple Computer
MARIE: An Introduction to a Simple Computer 4.2 CPU Basics The computer s CPU fetches, decodes, and executes program instructions. The two principal parts of the CPU are the datapath and the control unit.
More informationControl unit. Input/output devices provide a means for us to make use of a computer system. Computer System. Computer.
Lecture 6: I/O and Control I/O operations Control unit Microprogramming Zebo Peng, IDA, LiTH 1 Input/Output Devices Input/output devices provide a means for us to make use of a computer system. Computer
More informationCOMPUTER STRUCTURE AND ORGANIZATION
COMPUTER STRUCTURE AND ORGANIZATION Course titular: DUMITRAŞCU Eugen Chapter 4 COMPUTER ORGANIZATION FUNDAMENTAL CONCEPTS CONTENT The scheme of 5 units von Neumann principles Functioning of a von Neumann
More informationInstruction Pipelining
Instruction Pipelining Simplest form is a 3-stage linear pipeline New instruction fetched each clock cycle Instruction finished each clock cycle Maximal speedup = 3 achieved if and only if all pipe stages
More informationCOSC 243. Computer Architecture 1. COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 1
COSC 243 Computer Architecture 1 COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 1 Overview Last Lecture Flip flops This Lecture Computers Next Lecture Instruction sets and addressing
More informationInstruction Level Parallelism. Appendix C and Chapter 3, HP5e
Instruction Level Parallelism Appendix C and Chapter 3, HP5e Outline Pipelining, Hazards Branch prediction Static and Dynamic Scheduling Speculation Compiler techniques, VLIW Limits of ILP. Implementation
More informationCOMPUTER ORGANIZATION AND DESI
COMPUTER ORGANIZATION AND DESIGN 5 Edition th The Hardware/Software Interface Chapter 4 The Processor 4.1 Introduction Introduction CPU performance factors Instruction count Determined by ISA and compiler
More informationAnnouncement. Computer Architecture (CSC-3501) Lecture 25 (24 April 2008) Chapter 9 Objectives. 9.2 RISC Machines
Announcement Computer Architecture (CSC-3501) Lecture 25 (24 April 2008) Seung-Jong Park (Jay) http://wwwcsclsuedu/~sjpark 1 2 Chapter 9 Objectives 91 Introduction Learn the properties that often distinguish
More informationWhere Does The Cpu Store The Address Of The
Where Does The Cpu Store The Address Of The Next Instruction To Be Fetched The three most important buses are the address, the data, and the control buses. The CPU always knows where to find the next instruction
More informationAdvanced d Processor Architecture. Computer Systems Laboratory Sungkyunkwan University
Advanced d Processor Architecture Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Modern Microprocessors More than just GHz CPU Clock Speed SPECint2000
More informationChapter 2 Logic Gates and Introduction to Computer Architecture
Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are
More informationReal instruction set architectures. Part 2: a representative sample
Real instruction set architectures Part 2: a representative sample Some historical architectures VAX: Digital s line of midsize computers, dominant in academia in the 70s and 80s Characteristics: Variable-length
More informationComputer Architecture 2/26/01 Lecture #
Computer Architecture 2/26/01 Lecture #9 16.070 On a previous lecture, we discussed the software development process and in particular, the development of a software architecture Recall the output of the
More informationCourse Description: This course includes concepts of instruction set architecture,
Computer Architecture Course Title: Computer Architecture Full Marks: 60+ 20+20 Course No: CSC208 Pass Marks: 24+8+8 Nature of the Course: Theory + Lab Credit Hrs: 3 Course Description: This course includes
More informationRISC & Superscalar. COMP 212 Computer Organization & Architecture. COMP 212 Fall Lecture 12. Instruction Pipeline no hazard.
COMP 212 Computer Organization & Architecture Pipeline Re-Cap Pipeline is ILP -Instruction Level Parallelism COMP 212 Fall 2008 Lecture 12 RISC & Superscalar Divide instruction cycles into stages, overlapped
More informationINTELLIGENCE PLUS CHARACTER - THAT IS THE GOAL OF TRUE EDUCATION UNIT-I
UNIT-I 1. List and explain the functional units of a computer with a neat diagram 2. Explain the computer levels of programming languages 3. a) Explain about instruction formats b) Evaluate the arithmetic
More informationExample of A Microprogrammed Computer
Example of A Microprogrammed omputer The purpose of this example is to demonstrate some of the concepts of microprogramming. We are going to create a simple 16-bit computer that uses three buses A, B,
More informationIntel released new technology call P6P
P6 and IA-64 8086 released on 1978 Pentium release on 1993 8086 has upgrade by Pipeline, Super scalar, Clock frequency, Cache and so on But 8086 has limit, Hard to improve efficiency Intel released new
More informationSYLLABUS. osmania university CHAPTER - 1 : REGISTER TRANSFER LANGUAGE AND MICRO OPERATION CHAPTER - 2 : BASIC COMPUTER
Contents i SYLLABUS osmania university UNIT - I CHAPTER - 1 : REGISTER TRANSFER LANGUAGE AND MICRO OPERATION Difference between Computer Organization and Architecture, RTL Notation, Common Bus System using
More informationComputer Organization Question Bank
Id 1 Question Mass produced first working machine (50 copies) was invented by A C D Answer Wilhelm Schickhard laise Pascal Gottfried Liebniz Charles abbage Id 2 Question Father of Modern Computer A Wilhelm
More informationThe Stored Program Computer
The Stored Program Computer 1 1945: John von Neumann Wrote a report on the stored program concept, known as the First Draft of a Report on EDVAC also Alan Turing Konrad Zuse Eckert & Mauchly The basic
More informationSuperscalar Processors Ch 13. Superscalar Processing (5) Computer Organization II 10/10/2001. New dependency for superscalar case? (8) Name dependency
Superscalar Processors Ch 13 Limitations, Hazards Instruction Issue Policy Register Renaming Branch Prediction 1 New dependency for superscalar case? (8) Name dependency (nimiriippuvuus) two use the same
More informationECE 587 Advanced Computer Architecture I
ECE 587 Advanced Computer Architecture I Instructor: Alaa Alameldeen alaa@ece.pdx.edu Spring 2015 Portland State University Copyright by Alaa Alameldeen and Haitham Akkary 2015 1 When and Where? When:
More informationChapter 1: Basics of Microprocessor [08 M]
Microprocessor: Chapter 1: Basics of Microprocessor [08 M] It is a semiconductor device consisting of electronic logic circuits manufactured by using either a Large scale (LSI) or Very Large Scale (VLSI)
More informationDEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING QUESTION BANK
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING QUESTION BANK SUBJECT : CS6303 / COMPUTER ARCHITECTURE SEM / YEAR : VI / III year B.E. Unit I OVERVIEW AND INSTRUCTIONS Part A Q.No Questions BT Level
More informationCISC / RISC. Complex / Reduced Instruction Set Computers
Systems Architecture CISC / RISC Complex / Reduced Instruction Set Computers CISC / RISC p. 1/12 Instruction Usage Instruction Group Average Usage 1 Data Movement 45.28% 2 Flow Control 28.73% 3 Arithmetic
More informationCC312: Computer Organization
CC312: Computer Organization Dr. Ahmed Abou EL-Farag Dr. Marwa El-Shenawy 1 Chapter 4 MARIE: An Introduction to a Simple Computer Chapter 4 Objectives Learn the components common to every modern computer
More informationCS 265. Computer Architecture. Wei Lu, Ph.D., P.Eng.
CS 265 Computer Architecture Wei Lu, Ph.D., P.Eng. Part 3: von Neumann Architecture von Neumann Architecture Our goal: understand the basics of von Neumann architecture, including memory, control unit
More informationECE 571 Advanced Microprocessor-Based Design Lecture 4
ECE 571 Advanced Microprocessor-Based Design Lecture 4 Vince Weaver http://www.eece.maine.edu/~vweaver vincent.weaver@maine.edu 28 January 2016 Homework #1 was due Announcements Homework #2 will be posted
More informationMARIE: An Introduction to a Simple Computer
MARIE: An Introduction to a Simple Computer Outline Learn the components common to every modern computer system. Be able to explain how each component contributes to program execution. Understand a simple
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware 4.1 Introduction We will examine two MIPS implementations
More information3.1 Description of Microprocessor. 3.2 History of Microprocessor
3.0 MAIN CONTENT 3.1 Description of Microprocessor The brain or engine of the PC is the processor (sometimes called microprocessor), or central processing unit (CPU). The CPU performs the system s calculating
More informationCPE300: Digital System Architecture and Design
CPE300: Digital System Architecture and Design Fall 2011 MW 17:30-18:45 CBC C316 Pipelining 11142011 http://www.egr.unlv.edu/~b1morris/cpe300/ 2 Outline Review I/O Chapter 5 Overview Pipelining Pipelining
More informationComputer Architecture and Data Manipulation. Von Neumann Architecture
Computer Architecture and Data Manipulation Chapter 3 Von Neumann Architecture Today s stored-program computers have the following characteristics: Three hardware systems: A central processing unit (CPU)
More informationProcessors. Young W. Lim. May 12, 2016
Processors Young W. Lim May 12, 2016 Copyright (c) 2016 Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version
More informationCOS 140: Foundations of Computer Science
COS 140: Foundations of Computer Science CPU Organization and Assembly Language Fall 2018 CPU 3 Components of the CPU..................................................... 4 Registers................................................................
More informationCS Computer Architecture
CS 35101 Computer Architecture Section 600 Dr. Angela Guercio Fall 2010 Computer Systems Organization The CPU (Central Processing Unit) is the brain of the computer. Fetches instructions from main memory.
More informationReal Processors. Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University
Real Processors Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University Instruction-Level Parallelism (ILP) Pipelining: executing multiple instructions in parallel
More informationThese actions may use different parts of the CPU. Pipelining is when the parts run simultaneously on different instructions.
MIPS Pipe Line 2 Introduction Pipelining To complete an instruction a computer needs to perform a number of actions. These actions may use different parts of the CPU. Pipelining is when the parts run simultaneously
More informationCS6303 Computer Architecture Regulation 2013 BE-Computer Science and Engineering III semester 2 MARKS
CS6303 Computer Architecture Regulation 2013 BE-Computer Science and Engineering III semester 2 MARKS UNIT-I OVERVIEW & INSTRUCTIONS 1. What are the eight great ideas in computer architecture? The eight
More information