SLC NAND FLASH and LPDDR2 162-Ball MCP (Multi-Chip Package)
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1 SLC NND FLSH and LPDDR2 162-Ball MCP (Multi-Chip Package) Key Features NND Flash Features: Low Power Dissipation High Reliability 1
2 Contents 1. MCP FETURES BLOCK DIGRM PRT NME DESCRIPTION PRODUCT SELECTION GUIDE PIN CONFIGURTIONS Ball, BG (NND x16; LPDDR x32) Ball, BG (NND x8; LPDDR x32) Ball, BG (NND x8; LPDDR x16) Ball, BG (NND x16; LPDDR x16) PIN DESCRIPTION...11 LPDDR2 x LPDDR2 x PCKGE INFORMTION REISION HISTORY
3 1. MCP FETURES Operation Temperature -30 C to +85 C -40 C to +85 C Package 162-ball FBG - 8.0mmx10.5mm, 1.0mm (h) (max), 0.5mm pitch NND Flash Features 1G-bit/2G-bit/4G-bit SLC NND Flash - Bus: x8 / x16-8 bit-ecc SLC NND Flash: Page size: ( ) byte for x8 bus, ( ) word for x16 bus Block size: (128K+7K) byte for x8 bus, (64K+2K) word for x16 bus - 4 bit-ecc SLC NND Flash: Page size: ( ) byte for x8 bus, ( ) word for x16 bus Block size: (128K+4K) byte for x8 bus, (64K+2K) word for x16 bus - Plane size: 1024-block/plane x 1 for 1Gb 1024-block/plane x 2 for 2Gb 2048-block/plane x 2 for 4Gb ONFI 1.0 compliant User Redundancy - 8 bit-ecc SLC NND Flash: 112-byte attached to each page - 4 bit-ecc SLC NND Flash: 64-byte attached to each page Fast Read ccess - Latency of array to register: 25us - Sequential read: 25ns Cache Read Support Page Program Operation - Page program time: 320us (typ.) Cache Program Support Block Erase Operation - Block erase time: 1.0ms (typ.) Single oltage Operation: - CC: Low Power Dissipation - Max. 30m (1.8) ctive current (Read/Program/Erase) Sleep Mode - 50u (Max) standby current Unique ID Read support (ONFI) Secure OTP support Electronic Signature (5 Cycles) High Reliability - 8 bit-ecc SLC NND Flash: Endurance: typical 100K cycles (with 8-bit ECC per (512+28) Byte) - 4 bit-ecc SLC NND Flash: Endurance: typical 100K cycles (with 4-bit ECC per (512+16) Byte) - Data Retention: 10 years LPDDR2 DRM Features JEDEC LPDDR2-S4B compliance DLL is not implemented Low power consumption Mobile RM functions - Partial rray Self-Refresh (PSR) - uto Temperature Compensated Self-Refresh (TCSR) by built-in temperature sensor - Deep power-down mode - Per Bank Refresh DD Definition: Typical Range DD DD DDQ oltage source of REFC is DD2, REFC=1/2*DD2 (from voltage divider) - oltage source of REFDQ is DDQ, REFDQ=1/2*DDQ (from voltage divider) Min. Max. REFC 0.49xDD2 0.51xDD2 REFDQ 0.49xDDQ 0.51xDDQ 3
4 2. BLOCK DIGRM NND LE CLE IOx~IO0 CE# RE# WE# WP# PT NND R/B# LPDDR2 DD1 DD2 DDQ DDC Q C REFC REFDQ /CS CKE CK /CK DM C[9:0] LPDDR2 ZQ RZQ DQ[31:0]/DQ[15:0] DQS 4
5 3. PRT NME DESCRIPTION MX63 U 4G 2G B XM I 00 Option Code 00: -30 C to +85 C 01: -40 C to +85 C Product Grade I: Industrial Package: XM: 162-Ball FBG XN: 130-Ball FBG MCP Combinations Type CE# 1,1 Combination 1 NND; 1 LPDDR LPDDR Configuration Type Bus cc Generation Speed DDR2 x MHz B DDR2 x MHz C DDR2 x MHz E DDR x MHz F DDR x MHz J DDR x MHz K DDR x MHz G DDR2 x MHz H DDR2 x MHz LPDDR Density 256M = 56 2G = 2G 512M = 12 4G = 4G 1G = 1G 8G = 8G NND Configuration Type Bus Number of ECC-bit x8 8 B x16 8 C x8 4 D x16 4 NND Density 512M = 12 8G = 8G 1G = 1G 16G = G 2G = 2G 32G = BG 4G = 4G 64G = CG Generation 1st 1st 1st 1st E x8 4 2nd NND oltage: 1.8 Product Family MX63U : NND + LPDRM MCP 5
6 4. PRODUCT SELECTION GUIDE Please contact Macronix regional sales for the latest product selection and available form factors. Item No. Device NND Flash Mobile DRM Package Type DDC Pin 1. MX63U4GC2GGXMI00 4Gb, x8, 1.8, 4-bit ECC 2Gb, LPDDR2, x16, Ball BG Yes 2. MX63U4GC2GGXMI01 4Gb, x8, 1.8, 4-bit ECC 2Gb, LPDDR2, x16, Ball BG Yes 3. MX63U4GC2GHXMI00 4Gb, x8, 1.8, 4-bit ECC 2Gb, LPDDR2, x32, Ball BG Yes 4. MX63U4GC2GHXMI01 4Gb, x8, 1.8, 4-bit ECC 2Gb, LPDDR2, x32, Ball BG Yes 5. MX63U4G2GHXMI00 4Gb, x8, 1.8, 8bit ECC 2Gb, LPDDR2, x32, Ball BG Yes 6. MX63U2GE2GGXMI00 2Gb, x8, 1.8, 4-bit ECC 2Gb, LPDDR2, x16, Ball BG Yes 7. MX63U2GE2GGXMI01 2Gb, x8, 1.8, 4-bit ECC 2Gb, LPDDR2, x16, Ball BG Yes 8. MX63U2GE2GHXMI00 2Gb, x8, 1.8, 4-bit ECC 2Gb, LPDDR2, x32, Ball BG Yes 9. MX63U2GE2GHXMI01 2Gb, x8, 1.8, 4-bit ECC 2Gb, LPDDR2, x32, Ball BG Yes 10. MX63U1GC12HXMI01 1Gb, x8, 1.8, 4-bit ECC 512Mb, LPDDR2, x32, Ball BG 11. MX63U2GE1GHXMI01 2Gb, x8, 1.8, 4-bit ECC 1Gb, LPDDR2, x32, Ball BG 12. MX63U2GE1GHXMI00 2Gb, x8, 1.8, 4-bit ECC 1Gb, LPDDR2, x32, Ball BG 6
7 5. PIN CONFIGURTIONS 162-Ball, BG (NND x16; LPDDR x32) PT WP# CLE CC IO4 IO7 CC B CC IO11 LE RE# IO5 IO14 IO15 m B C IO10 IO1 IO3 WE# R/B# IO6 C D IO8 IO0 IO2 CE# IO12 IO13 D E m IO9 DD2 DD1 DQ31 DQ29 DQ26 E F DD1 Q DDQ DQ25 Q DDQ F G DD2 ZQ DDQ DQ30 DQ27 DQS3 /DQS3 Q G H C C9 C8 DQ28 DQ24 DM3 DQ15 DDQ Q H J K / DDC DD2 C6 C5 C7 REF (C) Q DQ11 DQ13 DQ14 DQ12 DDQ /DQS1 DQS1 DQ10 DQ9 DQ8 Q J K L M / DDC C /CK CK DM1 DDQ Q DDQ DD2 REF (DQ) L M N CKE DM0 DDQ N P /CS /DQS0 DQS0 DQ5 DQ6 DQ7 Q P R C4 C3 C2 Q DQ4 DQ2 DQ1 DQ3 DDQ R T / CDDC C1 DQ19 DQ23 DM2 DQ0 DDQ Q T U DD2 C0 DDQ DQ17 DQ20 DQS2 /DQS2 Q U DD1 Q DDQ DQ22 Q DDQ W DD2 DD1 DQ16 DQ18 DQ21 W Y Y LPDDR2 Command/ddress NND IO/Command/ddress LPDDR2 Data IO Ground (,C,Q, m) Power (DD1,DD2, REF, CC) Note: Please check Product Selection Guide for pin or DDC pin support. 7
8 162-Ball, BG (NND x8; LPDDR x32) PT WP# CLE CC IO4 IO7 CC B CC LE RE# IO5 m B C IO1 IO3 WE# R/B# IO6 C D IO0 IO2 CE# D E m DD2 DD1 DQ31 DQ29 DQ26 E F DD1 Q DDQ DQ25 Q DDQ F G DD2 ZQ DDQ DQ30 DQ27 DQS3 /DQS3 Q G H C C9 C8 DQ28 DQ24 DM3 DQ15 DDQ Q H J K / DDC C6 DD2 C5 C7 REF (C) Q DQ11 DQ13 DQ14 DQ12 DDQ /DQS1 DQS1 DQ10 DQ9 DQ8 Q J K L M / DDC C /CK CK DM1 DDQ Q DDQ DD2 REF (DQ) L M N CKE DM0 DDQ N P /CS /DQS0 DQS0 DQ5 DQ6 DQ7 Q P R C4 C3 C2 Q DQ4 DQ2 DQ1 DQ3 DDQ R T U / CDDC C1 DD2 C0 DQ19 DQ23 DM2 DQ0 DDQ Q DDQ DQ17 DQ20 DQS2 /DQS2 Q T U DD1 Q DDQ DQ22 Q DDQ W DD2 DD1 DQ16 DQ18 DQ21 W Y Y LPDDR2 Command/ddress NND IO/Command/ddress (NND pin must keep floating) LPDDR2 Data IO Ground (,C,Q, m) Power (DD1,DD2, REF, CC) Note: Please check Product Selection Guide for pin or DDC pin support. 8
9 162-Ball, BG (NND x8; LPDDR x16) PT WP# CLE CC IO4 IO7 CC B CC LE RE# IO5 m B C IO1 IO3 WE# R/B# IO6 C D IO0 IO2 CE# D E m DD2 DD1 E F DD1 Q DDQ Q DDQ F G DD2 ZQ DDQ Q G H C C9 C8 DQ15 DDQ Q H J K / DDC C6 DD2 C5 C7 REF (C) Q DQ11 DQ13 DQ14 DQ12 DDQ /DQS1 DQS1 DQ10 DQ9 DQ8 Q J K L M / DDC C /CK CK DM1 DDQ Q DDQ DD2 REF (DQ) L M N CKE DM0 DDQ N P /CS /DQS0 DQS0 DQ5 DQ6 DQ7 Q P R C4 C3 C2 Q DQ4 DQ2 DQ1 DQ3 DDQ R T U / CDDC C1 DD2 C0 DQ0 DDQ Q DDQ Q T U DD1 Q DDQ Q DDQ W DD2 DD1 W Y Y LPDDR2 Command/ddress NND IO/Command/ddress LPDDR2 Data IO Ground (,C,Q, m) Power (DD1,DD2, REF, CC) Note: Please check Product Selection Guide for pin or DDC pin support. 9
10 162-Ball, BG (NND x16; LPDDR x16) PT WP# CLE CC IO4 IO7 CC B CC IO11 LE RE# IO5 IO14 IO15 m B C IO10 IO1 IO3 WE# R/B# IO6 C D IO8 IO0 IO2 CE# IO12 IO13 D E m IO9 DD2 DD1 E F DD1 Q DDQ Q DDQ F G DD2 ZQ DDQ Q G H C C9 C8 DQ15 DDQ Q H J K / DDC C6 DD2 C5 C7 REF (C) Q DQ11 DQ13 DQ14 DQ12 DDQ /DQS1 DQS1 DQ10 DQ9 DQ8 Q J K L M / DDC C /CK CK DM1 DDQ Q DDQ DD2 REF (DQ) L M N CKE DM0 DDQ N P /CS /DQS0 DQS0 DQ5 DQ6 DQ7 Q P R C4 C3 C2 Q DQ4 DQ2 DQ1 DQ3 DDQ R T U / CDDC C1 DD2 C0 DQ0 DDQ Q DDQ Q T U DD1 Q DDQ Q DDQ W DD2 DD1 W Y Y LPDDR2 Command/ddress NND IO/Command/ddress LPDDR2 Data IO Ground (,C,Q, m) Power (DD1,DD2, REF, CC) Note: Please check Product Selection Guide for pin or DDC pin support. 10
11 6. PIN DESCRIPTION LPDDR2 x32 SYMBOL DESCRIPTION NND Flash 4Gb (512Mb x8) 2Gb (256Mb x8) 1Gb (128Mb x8) LPDDR2x32 2Gb (64Mb x32) 1Gb (32Mb x32) 512Mb (16Mb x32) I/O0 - I/OX Data Input / Output CLE Command Latch Enable LE ddress Latch Enable CE# Chip Enable WE# Write Enable RE# Read Enable WP# Write Protect R/B# Ready / Busy Out CC Supply oltage m Ground PT Chip Protection Enable /CS Chip Select CK, /CK Differential Clocks CKE Clock Enable C0 - C9 Command / ddress DQ0 - DQ31 Data I/O DM0 - DM3 Input Data Mask DQS0 - DQS3 Differential Data Strobe (rising edge) /DQS0 - /DQS3 Differential Data Strobe (falling edge) ZQ Drive Strength Calibration REF(DQ) Reference oltage REF(C) Reference oltage DD1 Core Power Supply DD2 Core Power Supply, C, Q Ground DDQ I/O Power Supply DDC C Power Supply No Connection * Do Not Use * : pin of NND must keep floating. 11
12 LPDDR2 x16 SYMBOL DESCRIPTION * : pin of NND must keep floating. NND Flash 4Gb (512Mb x8) 2Gb (256Mb x8) 1Gb (128Mb x8) LPDDR2 x16 1Gb(64Mb x16) I/O0 - I/OX Data Input / Output CLE Command Latch Enable LE ddress Latch Enable CE# Chip Enable WE# Write Enable RE# Read Enable WP# Write Protect R/B# Ready / Busy Out CC Supply oltage m Ground PT Chip Protection Enable /CS Chip Select CK, /CK Differential Clocks CKE Clock Enable C0 - C9 Command / ddress DQ0-DQ15 Data I/O DM0-DM1 Input Data Mask DQS0-DQS1 Differential Data Strobe (rising edge) /DQS0-/DQS1 Differential Data Strobe (falling edge) ZQ Drive Strength Calibration REF(DQ) Reference oltage REF(C) Reference oltage DD1 Core Power Supply DD2 Core Power Supply, C, Q Ground DDQ I/O Power Supply DDC C Power Supply No Connection * Do Not Use 12
13 7. PCKGE INFORMTION 13
14 8. REISION HISTORY Revision No. Description Page Date Modified PRT NME DESCRIPTION P4 JUL/21/ Removed the title "dvanced information" ll 3. Revised Bus information, Page program and Block erase time P2 4. Revised block diagram (NND) P dded DD definition P2 OCT/24/ dded two part numbers: MX63U2GC1GCXMI00 and P2,4,5 MX63U4GC2GBXMI dded part numbers: MX63U1GC1GXMI00, P3-6,9, PR/22/2015 MX63U1GD1GXMI00, MX63U1GC1GXMI01, MX63U4GC2GBXMI01,MX63U4GC2GGXMI00, MX63U2GE2GGXMI00, MX63U4GC2GGXMI01 and MX63U2GE2GGXMI01 2. Modified DDC pin P Revised PRT NME DESCRIPTION P5 4. dded PIN CONFIGURTIONS: NND x16; LPDDR x16 P10 5. Content modification P dded Option Code (Operation Temperature) P3, dded part numbers: MX63U4GC2GHXMI00, P6 MY/29/2015 MX63U4GC2GHXMI01 and MX63U2GE2GHXMI00 2. Removed dvanced Information "*" for MX63U4GC2GBXMI00 P6 and MX63U1GD1GXMI Removed two part numbers: MX63U4GB2GBXMI00 P6 JUN/11/2015 and MX63U4GC2GBXMI01 2. dded part number: MX63U4G2GHXMI00 P Removed dvanced Information "*" for three part numbers: P6 OCT/29/2015 MX63U2GC1GCXMI00, MX63U1GC1GXMI00 and MX63U1GC1GXMI dded part number: MX63U2GE2GHXMI01 P6 NO/27/ dded part number: MX63U2GD1GCXMI01 P6 DEC/14/ dded a statement for product ordering information. P6 MR/09/ Removed all dvanced Information "*" P6 3. dded two part numbers: P6 MX63U2GC1GCXMI01 MX63U1GC1GCXMI dded a part number: MX63U1GC12HXMI01 P6 OCT/18/
15 Revision No. Description Page Date Removed part numbers: MX63U4G2GBXMI00, P6 NO/14/2018 MX63U4GC2GBXMI00, MX63U2G1GCXMI00, MX63U2GB1GCXMI00, MX63U2GC1GCXMI00, MX63U2GC1GCXMI01, MX63U2GD1GCXMI01, MX63U1GC1GXMI00, MX63U1GD1GXMI00, MX63U1GC1GCXMI01 and MX63U1GC1GXMI01 2. dded part numbers: MX63U2GE1GHXMI01 and P6 MX63U2GE1GHXMI00 3. dded "" footnote. LL 4. Format modification. P13 15
16 Except for customized products which has been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it s suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright Macronix International Co., Ltd ll rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, Nbit, Macronix NBit, HybridNM, HybridFlash, HybridXFlash, XtraROM, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vee, Macronix MP, RichBook, Rich T, OctaRM, OctaBus, OctaFlash, and FitCM. The names and brands of third party referred thereto (if any) are for identification purposes only. For the contact and order information, please visit Macronix s Web site at: MCRONIX INTERNTIONL CO., LTD. reserves the right to change product and specifications without notice. 16
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