Washington University School of Engineering and Applied Science. Power Consumption of Customized Numerical Representations for Audio Signal Processing
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1 Washington University School of Engineering and Applied Science Power Consumption of Customized Numerical Representations for Audio Signal Processing Roger Chamberlain, Yen Hsiang Chew, Varuna DeAlwis, Eric Hemmeter,John Lockwood, Robert Morley, Ed Richter, Jason White, and Huakai Zhang This research is supported by the NIH under grant 1R4-3DC HPEC Outline Audio Signal Requirements Customized Numerical Representations SNR and Dynamic Range Design of Computation Structures Power Consumption Results Summary and Conclusions HPEC
2 Audio Signal Applications Music MP3 players Speech communications equipment hearing aids (our target application) Signal requirements to understand speech ~30 db SNR over entire dynamic range ~100 db dynamic range Power consumption critical for all of above HPEC Customized Numerical Representations 16-bit integer is traditional for audio 90 db dynamic range, SNR from 0 to 90 db Logarithmic representation more closely mimics human perception Loudness response is highly non-linear SNR is relatively constant across dynamic range Floating gpoint representations are partially logarithmic and partially linear 32-bit IEEE standard is more than is needed Tailor choice for number of bits in exponent and mantissa to needs of application HPEC
3 SNR and Dynamic Range SNR (db) = 20 log 10 V i 2 2 V i + 1 V i 12 V V Dynamic Range (db) = 20 log 10 V max min HPEC SNR (db) bit Integer SNR Input Value (Vi) HPEC
4 9-bit Logarithmic SNR SNR (db) E Input Value (Vi) HPEC SNR (db) Floating Point SNR 5-bit exponent 4, 5, and 6-bit mantissa E Input Value (Vi) FP 5-6 FP 5-5 FP 5-4 HPEC
5 400 6-bit exp. Dynamic Range Range (db) bit exp. log. 4-bit exp. int FP 6-5 FP 6-4 FP 5-6 FP 5-5 FP 5-4 FP 9-bit Log 4-6 FP 4-5 FP 4-4 FP 16-bit Integer Representation HPEC Hearing Aid Architecture Most of the computations the hearing aid performs are multiply-accumulates. HPEC
6 Floating Point MAC Design Traditional structure for floating point hardware computations ti Perl script generates synthesizable VHDL code for specific exponent and mantissa size Small size of mantissa implies lower power multiplier hardware HPEC Floating Point MAC Xi_j Xi_j/Cj(4 downto 0) Yi(4 downto 0) Mant Mant Mant * Normalize Shifter Acc Normalize Mant S Register Yi Cj Xi_j/Cj(9 downto 5) Exp + Exp Normalize Exp Sub Exp Normalize Yi(10) Yi(9 downto 5) S Xi_j/Cj(10) S Clk Latch Reset Enable HPEC
7 Logarithmic MAC Design Multiply function provided by an adder: log( A B ) = log( A ) + log( B ) Addition function exploits the following relationship: log B + + A ( A B) = log( A) + log 1 Last term implemented via a lookup table HPEC bit Logarithmic MAC Xi_j Cj Xi_j/Cj(8 downto 0) * Multiplied Result Look-up Table Add Result or Pass-through Register Yi Xi_j/Cj (9) s s Comparator Clk Latch Enable Reset HPEC
8 Verification Via FPX Platform Audio Data FPX Fieldprogrammable Port Extender Audio Data HPEC FPX Platform HPEC
9 Layout AMI 0.5 μm process ADK library from Mentor Graphics HEP 5-55 floating point MAC is shown HPEC Power Estimation via Simulation Simulate using Mentor Graphics MACH-PA Spice-level simulation tool Driven by extracted layout Focus on Multiply-Accumulate units Random input vectors Simulation provides current usage P = IVprovides power results HPEC
10 Power Consumption Average Power (mw) bit bit Integer Log Numerical Representation HPEC Summary and Conclusions Customizing a numerical representation to the specific needs of an application can have tangible benefits Several 9 or 10-bit representations have improved SNR and dynamic range for audio speech applications relative to traditional 16- bit integers Both customized floating point and logarithmic representations have been considered Power savings are significant HPEC
11 For Further Information or HPEC
Washington University
Washington University School of Engineering and Applied Science Power Consumption of Customized Numerical Representations for Audio Signal Processing Roger Chamberlain, Yen Hsiang Chew, Varuna DeAlwis,
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