Washington University School of Engineering and Applied Science. Power Consumption of Customized Numerical Representations for Audio Signal Processing

Size: px
Start display at page:

Download "Washington University School of Engineering and Applied Science. Power Consumption of Customized Numerical Representations for Audio Signal Processing"

Transcription

1 Washington University School of Engineering and Applied Science Power Consumption of Customized Numerical Representations for Audio Signal Processing Roger Chamberlain, Yen Hsiang Chew, Varuna DeAlwis, Eric Hemmeter,John Lockwood, Robert Morley, Ed Richter, Jason White, and Huakai Zhang This research is supported by the NIH under grant 1R4-3DC HPEC Outline Audio Signal Requirements Customized Numerical Representations SNR and Dynamic Range Design of Computation Structures Power Consumption Results Summary and Conclusions HPEC

2 Audio Signal Applications Music MP3 players Speech communications equipment hearing aids (our target application) Signal requirements to understand speech ~30 db SNR over entire dynamic range ~100 db dynamic range Power consumption critical for all of above HPEC Customized Numerical Representations 16-bit integer is traditional for audio 90 db dynamic range, SNR from 0 to 90 db Logarithmic representation more closely mimics human perception Loudness response is highly non-linear SNR is relatively constant across dynamic range Floating gpoint representations are partially logarithmic and partially linear 32-bit IEEE standard is more than is needed Tailor choice for number of bits in exponent and mantissa to needs of application HPEC

3 SNR and Dynamic Range SNR (db) = 20 log 10 V i 2 2 V i + 1 V i 12 V V Dynamic Range (db) = 20 log 10 V max min HPEC SNR (db) bit Integer SNR Input Value (Vi) HPEC

4 9-bit Logarithmic SNR SNR (db) E Input Value (Vi) HPEC SNR (db) Floating Point SNR 5-bit exponent 4, 5, and 6-bit mantissa E Input Value (Vi) FP 5-6 FP 5-5 FP 5-4 HPEC

5 400 6-bit exp. Dynamic Range Range (db) bit exp. log. 4-bit exp. int FP 6-5 FP 6-4 FP 5-6 FP 5-5 FP 5-4 FP 9-bit Log 4-6 FP 4-5 FP 4-4 FP 16-bit Integer Representation HPEC Hearing Aid Architecture Most of the computations the hearing aid performs are multiply-accumulates. HPEC

6 Floating Point MAC Design Traditional structure for floating point hardware computations ti Perl script generates synthesizable VHDL code for specific exponent and mantissa size Small size of mantissa implies lower power multiplier hardware HPEC Floating Point MAC Xi_j Xi_j/Cj(4 downto 0) Yi(4 downto 0) Mant Mant Mant * Normalize Shifter Acc Normalize Mant S Register Yi Cj Xi_j/Cj(9 downto 5) Exp + Exp Normalize Exp Sub Exp Normalize Yi(10) Yi(9 downto 5) S Xi_j/Cj(10) S Clk Latch Reset Enable HPEC

7 Logarithmic MAC Design Multiply function provided by an adder: log( A B ) = log( A ) + log( B ) Addition function exploits the following relationship: log B + + A ( A B) = log( A) + log 1 Last term implemented via a lookup table HPEC bit Logarithmic MAC Xi_j Cj Xi_j/Cj(8 downto 0) * Multiplied Result Look-up Table Add Result or Pass-through Register Yi Xi_j/Cj (9) s s Comparator Clk Latch Enable Reset HPEC

8 Verification Via FPX Platform Audio Data FPX Fieldprogrammable Port Extender Audio Data HPEC FPX Platform HPEC

9 Layout AMI 0.5 μm process ADK library from Mentor Graphics HEP 5-55 floating point MAC is shown HPEC Power Estimation via Simulation Simulate using Mentor Graphics MACH-PA Spice-level simulation tool Driven by extracted layout Focus on Multiply-Accumulate units Random input vectors Simulation provides current usage P = IVprovides power results HPEC

10 Power Consumption Average Power (mw) bit bit Integer Log Numerical Representation HPEC Summary and Conclusions Customizing a numerical representation to the specific needs of an application can have tangible benefits Several 9 or 10-bit representations have improved SNR and dynamic range for audio speech applications relative to traditional 16- bit integers Both customized floating point and logarithmic representations have been considered Power savings are significant HPEC

11 For Further Information or HPEC

Washington University

Washington University Washington University School of Engineering and Applied Science Power Consumption of Customized Numerical Representations for Audio Signal Processing Roger Chamberlain, Yen Hsiang Chew, Varuna DeAlwis,

More information

Lightweight Arithmetic for Mobile Multimedia Devices. IEEE Transactions on Multimedia

Lightweight Arithmetic for Mobile Multimedia Devices. IEEE Transactions on Multimedia Lightweight Arithmetic for Mobile Multimedia Devices Tsuhan Chen Carnegie Mellon University tsuhan@cmu.edu Thanks to Fang Fang and Rob Rutenbar IEEE Transactions on Multimedia EDICS Signal Processing for

More information

Floating-point to Fixed-point Conversion. Digital Signal Processing Programs (Short Version for FPGA DSP)

Floating-point to Fixed-point Conversion. Digital Signal Processing Programs (Short Version for FPGA DSP) Floating-point to Fixed-point Conversion for Efficient i Implementation ti of Digital Signal Processing Programs (Short Version for FPGA DSP) Version 2003. 7. 18 School of Electrical Engineering Seoul

More information

Lightweight Arithmetic for Mobile Multimedia Devices

Lightweight Arithmetic for Mobile Multimedia Devices Lightweight Arithmetic for Mobile Multimedia Devices Tsuhan Chen 陳祖翰 Carnegie Mellon University tsuhan@cmu.edu Thanks to Fang Fang and Rob Rutenbar Multimedia Applications on Mobile Devices Multimedia

More information

ECE 450:DIGITAL SIGNAL. Lecture 10: DSP Arithmetic

ECE 450:DIGITAL SIGNAL. Lecture 10: DSP Arithmetic ECE 450:DIGITAL SIGNAL PROCESSORS AND APPLICATIONS Lecture 10: DSP Arithmetic Last Session Floating Point Arithmetic Addition Block Floating Point format Dynamic Range and Precision 2 Today s Session Guard

More information

C NUMERIC FORMATS. Overview. IEEE Single-Precision Floating-point Data Format. Figure C-0. Table C-0. Listing C-0.

C NUMERIC FORMATS. Overview. IEEE Single-Precision Floating-point Data Format. Figure C-0. Table C-0. Listing C-0. C NUMERIC FORMATS Figure C-. Table C-. Listing C-. Overview The DSP supports the 32-bit single-precision floating-point data format defined in the IEEE Standard 754/854. In addition, the DSP supports an

More information

VLSI Signal Processing

VLSI Signal Processing VLSI Signal Processing Programmable DSP Architectures Chih-Wei Liu VLSI Signal Processing Lab Department of Electronics Engineering National Chiao Tung University Outline DSP Arithmetic Stream Interface

More information

ECE232: Hardware Organization and Design

ECE232: Hardware Organization and Design ECE232: Hardware Organization and Design Lecture 11: Floating Point & Floating Point Addition Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Last time: Single Precision Format

More information

IMPLEMENTATION OF DOUBLE PRECISION FLOATING POINT RADIX-2 FFT USING VHDL

IMPLEMENTATION OF DOUBLE PRECISION FLOATING POINT RADIX-2 FFT USING VHDL IMPLEMENTATION OF DOUBLE PRECISION FLOATING POINT RADIX-2 FFT USING VHDL Tharanidevi.B 1, Jayaprakash.R 2 Assistant Professor, Dept. of ECE, Bharathiyar Institute of Engineering for Woman, Salem, TamilNadu,

More information

REDUCED FLOATING POINT FOR MPEG1/2 LAYER III DECODING. Mikael Olausson, Andreas Ehliar, Johan Eilert and Dake liu

REDUCED FLOATING POINT FOR MPEG1/2 LAYER III DECODING. Mikael Olausson, Andreas Ehliar, Johan Eilert and Dake liu REDUCED FLOATING POINT FOR MPEG1/2 LAYER III DECODING Mikael Olausson, Andreas Ehliar, Johan Eilert and Dake liu Computer Engineering Department of Electraical Engineering Linköpings universitet SE-581

More information

Quixilica Floating Point FPGA Cores

Quixilica Floating Point FPGA Cores Data sheet Quixilica Floating Point FPGA Cores Floating Point Adder - 169 MFLOPS* on VirtexE-8 Floating Point Multiplier - 152 MFLOPS* on VirtexE-8 Floating Point Divider - 189 MFLOPS* on VirtexE-8 Floating

More information

VHDL simulation and synthesis

VHDL simulation and synthesis VHDL simulation and synthesis How we treat VHDL in this course You will not become an expert in VHDL after taking this course The goal is that you should learn how VHDL can be used for simulation and synthesis

More information

Introduction to Computers and Programming. Numeric Values

Introduction to Computers and Programming. Numeric Values Introduction to Computers and Programming Prof. I. K. Lundqvist Lecture 5 Reading: B pp. 47-71 Sept 1 003 Numeric Values Storing the value of 5 10 using ASCII: 00110010 00110101 Binary notation: 00000000

More information

When addressing VLSI design most books start from a welldefined

When addressing VLSI design most books start from a welldefined Objectives An ASIC application MSDAP Analyze the application requirement System level setting of an application Define operation mode Define signals and pins Top level model Write a specification When

More information

RECENTLY, researches on gigabit wireless personal area

RECENTLY, researches on gigabit wireless personal area 146 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 55, NO. 2, FEBRUARY 2008 An Indexed-Scaling Pipelined FFT Processor for OFDM-Based WPAN Applications Yuan Chen, Student Member, IEEE,

More information

Design Objectives of the 0.35µm Alpha Microprocessor (A 500MHz Quad Issue RISC Microprocessor)

Design Objectives of the 0.35µm Alpha Microprocessor (A 500MHz Quad Issue RISC Microprocessor) Design Objectives of the 0.35µm Alpha 21164 Microprocessor (A 500MHz Quad Issue RISC Microprocessor) Gregg Bouchard Digital Semiconductor Digital Equipment Corporation Hudson, MA 1 Outline 0.35µm Alpha

More information

Physical Synthesis and Electrical Characterization of the IP-Core of an IEEE-754 Compliant Single Precision Floating Point Unit

Physical Synthesis and Electrical Characterization of the IP-Core of an IEEE-754 Compliant Single Precision Floating Point Unit Physical Synthesis and Electrical Characterization of the IP-Core of an IEEE-754 Compliant Single Precision Floating Point Unit Alian Engroff, Leonardo Tomazine Neto, Edson Schlosser and Alessandro Girardi

More information

ECE 2030D Computer Engineering Spring problems, 5 pages Exam Two 8 March 2012

ECE 2030D Computer Engineering Spring problems, 5 pages Exam Two 8 March 2012 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

3. HARDWARE ARCHITECTURE

3. HARDWARE ARCHITECTURE 3. HARDWARE ARCHITECTURE The architecture of the Recognition Accelerator consists of two main parts: a dedicated classifier engine and a general-purpose 16-bit microcontroller. The classifier implements

More information

Quixilica Floating-Point QR Processor Core

Quixilica Floating-Point QR Processor Core Data sheet Quixilica Floating-Point QR Processor Core With 13 processors on XC2V6000-5 - 20 GFlop/s at 100MHz With 10 processors on XC2V6000-5 - 15 GFlop/s at 97MHz With 4 processors on XC2V3000-5 - 81

More information

Chapter 03: Computer Arithmetic. Lesson 09: Arithmetic using floating point numbers

Chapter 03: Computer Arithmetic. Lesson 09: Arithmetic using floating point numbers Chapter 03: Computer Arithmetic Lesson 09: Arithmetic using floating point numbers Objective To understand arithmetic operations in case of floating point numbers 2 Multiplication of Floating Point Numbers

More information

Open Floating Point Unit

Open Floating Point Unit Open Floating Point Unit The Free IP Cores Projects www.opencores.org Author: Rudolf Usselmann rudi@asics.ws www.asics.ws Summary: This documents describes a free single precision floating point unit.

More information

Inf2C - Computer Systems Lecture 2 Data Representation

Inf2C - Computer Systems Lecture 2 Data Representation Inf2C - Computer Systems Lecture 2 Data Representation Boris Grot School of Informatics University of Edinburgh Last lecture Moore s law Types of computer systems Computer components Computer system stack

More information

Toward hardware support for Reproducible BLAS

Toward hardware support for Reproducible BLAS Toward hardware support for Reproducible BLAS http://bebop.cs.berkeley.edu/reproblas/ James Demmel, Hong Diep Nguyen SCAN 2014 - Wurzburg, Germany Sep 24, 2014 1 / 17 Reproducibility Reproducibility: obtaining

More information

LOW POWER PROBABILISTIC FLOATING POINT MULTIPLIER DESIGN

LOW POWER PROBABILISTIC FLOATING POINT MULTIPLIER DESIGN LOW POWER PROBABILISTIC FLOATING POINT MULTIPLIER DESIGN Aman Gupta,,*, Satyam Mandavalli, Vincent J. Mooney $,,*,, Keck-Voon Ling,*, Arindam Basu, Henry Johan $,* and Budianto Tandianus $,* International

More information

Formal Verification of Floating-Point programs

Formal Verification of Floating-Point programs Formal Verification of Floating-Point programs Sylvie Boldo and Jean-Christophe Filliâtre Montpellier June, 26th 2007 INRIA Futurs CNRS, LRI Motivations Goal: reliability in numerical software Motivations

More information

Outline. CPE/EE 422/522 Advanced Logic Design L15. Files. Files

Outline. CPE/EE 422/522 Advanced Logic Design L15. Files. Files Outline CPE/EE 422/522 Advanced Logic Design L15 Electrical and Computer Engineering University of Alabama in Huntsville VHDL What we know (additional topics) Attributes Transport and Inertial Delays Operator

More information

Computer Arithmetic Ch 8

Computer Arithmetic Ch 8 Computer Arithmetic Ch 8 ALU Integer Representation Integer Arithmetic Floating-Point Representation Floating-Point Arithmetic 1 Arithmetic Logical Unit (ALU) (2) (aritmeettis-looginen yksikkö) Does all

More information

INTRODUCTION TO CATAPULT C

INTRODUCTION TO CATAPULT C INTRODUCTION TO CATAPULT C Vijay Madisetti, Mohanned Sinnokrot Georgia Institute of Technology School of Electrical and Computer Engineering with adaptations and updates by: Dongwook Lee, Andreas Gerstlauer

More information

ARCHITECTURAL DESIGN OF 8 BIT FLOATING POINT MULTIPLICATION UNIT

ARCHITECTURAL DESIGN OF 8 BIT FLOATING POINT MULTIPLICATION UNIT ARCHITECTURAL DESIGN OF 8 BIT FLOATING POINT MULTIPLICATION UNIT Usha S. 1 and Vijaya Kumar V. 2 1 VLSI Design, Sathyabama University, Chennai, India 2 Department of Electronics and Communication Engineering,

More information

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering An Efficient Implementation of Double Precision Floating Point Multiplier Using Booth Algorithm Pallavi Ramteke 1, Dr. N. N. Mhala 2, Prof. P. R. Lakhe M.Tech [IV Sem], Dept. of Comm. Engg., S.D.C.E, [Selukate],

More information

Representing and Manipulating Floating Points. Computer Systems Laboratory Sungkyunkwan University

Representing and Manipulating Floating Points. Computer Systems Laboratory Sungkyunkwan University Representing and Manipulating Floating Points Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu The Problem How to represent fractional values with

More information

Computer Arithmetic Ch 8

Computer Arithmetic Ch 8 Computer Arithmetic Ch 8 ALU Integer Representation Integer Arithmetic Floating-Point Representation Floating-Point Arithmetic 1 Arithmetic Logical Unit (ALU) (2) Does all work in CPU (aritmeettis-looginen

More information

IEEE-754 compliant Algorithms for Fast Multiplication of Double Precision Floating Point Numbers

IEEE-754 compliant Algorithms for Fast Multiplication of Double Precision Floating Point Numbers International Journal of Research in Computer Science ISSN 2249-8257 Volume 1 Issue 1 (2011) pp. 1-7 White Globe Publications www.ijorcs.org IEEE-754 compliant Algorithms for Fast Multiplication of Double

More information

COE 405 Design Methodology Based on VHDL

COE 405 Design Methodology Based on VHDL COE 405 Design Methodology Based on VHDL Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Outline Elements of VHDL Top-Down Design Top-Down Design with

More information

Divide: Paper & Pencil

Divide: Paper & Pencil Divide: Paper & Pencil 1001 Quotient Divisor 1000 1001010 Dividend -1000 10 101 1010 1000 10 Remainder See how big a number can be subtracted, creating quotient bit on each step Binary => 1 * divisor or

More information

23. Digital Baseband Design

23. Digital Baseband Design 23. Digital Baseband Design Algorithm-to-VLSI Circuit Refinement (Floating Point) Tradeoff (SNR Loss, BER) (Fixed Point) VHDL, Verilog VHDL, Verilog Memory Control For I=0 to I=15 Sum = Sum + array[i]

More information

In this lesson you will learn: how to add and multiply positive binary integers how to work with signed binary numbers using two s complement how fixed and floating point numbers are used to represent

More information

Floating-point Arithmetic. where you sum up the integer to the left of the decimal point and the fraction to the right.

Floating-point Arithmetic. where you sum up the integer to the left of the decimal point and the fraction to the right. Floating-point Arithmetic Reading: pp. 312-328 Floating-Point Representation Non-scientific floating point numbers: A non-integer can be represented as: 2 4 2 3 2 2 2 1 2 0.2-1 2-2 2-3 2-4 where you sum

More information

COE 405, Term 062. Design & Modeling of Digital Systems. HW# 1 Solution. Due date: Wednesday, March. 14

COE 405, Term 062. Design & Modeling of Digital Systems. HW# 1 Solution. Due date: Wednesday, March. 14 COE 405, Term 062 Design & Modeling of Digital Systems HW# 1 Solution Due date: Wednesday, March. 14 Q.1. Consider the 4-bit carry-look-ahead adder (CLA) block shown below: A 3 -A 0 B 3 -B 0 C 3 4-bit

More information

Lecture 11 Logic Synthesis, Part 2

Lecture 11 Logic Synthesis, Part 2 Lecture 11 Logic Synthesis, Part 2 Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ Write Synthesizable Code Use meaningful names for signals and variables

More information

Data Representation Floating Point

Data Representation Floating Point Data Representation Floating Point CSCI 2400 / ECE 3217: Computer Architecture Instructor: David Ferry Slides adapted from Bryant & O Hallaron s slides via Jason Fritts Today: Floating Point Background:

More information

ISSN Vol.02, Issue.11, December-2014, Pages:

ISSN Vol.02, Issue.11, December-2014, Pages: ISSN 2322-0929 Vol.02, Issue.11, December-2014, Pages:1208-1212 www.ijvdcs.org Implementation of Area Optimized Floating Point Unit using Verilog G.RAJA SEKHAR 1, M.SRIHARI 2 1 PG Scholar, Dept of ECE,

More information

An Efficient Implementation of Floating Point Multiplier

An Efficient Implementation of Floating Point Multiplier An Efficient Implementation of Floating Point Multiplier Mohamed Al-Ashrafy Mentor Graphics Mohamed_Samy@Mentor.com Ashraf Salem Mentor Graphics Ashraf_Salem@Mentor.com Wagdy Anis Communications and Electronics

More information

Data Representation Floating Point

Data Representation Floating Point Data Representation Floating Point CSCI 2400 / ECE 3217: Computer Architecture Instructor: David Ferry Slides adapted from Bryant & O Hallaron s slides via Jason Fritts Today: Floating Point Background:

More information

Integer Multiplication. Back to Arithmetic. Integer Multiplication. Example (Fig 4.25)

Integer Multiplication. Back to Arithmetic. Integer Multiplication. Example (Fig 4.25) Back to Arithmetic Before, we did Representation of integers Addition/Subtraction Logical ops Forecast Integer Multiplication Integer Division Floating-point Numbers Floating-point Addition/Multiplication

More information

An Ultra Low-Power WOLA Filterbank Implementation in Deep Submicron Technology

An Ultra Low-Power WOLA Filterbank Implementation in Deep Submicron Technology An Ultra ow-power WOA Filterbank Implementation in Deep Submicron Technology R. Brennan, T. Schneider Dspfactory td 611 Kumpf Drive, Unit 2 Waterloo, Ontario, Canada N2V 1K8 Abstract The availability of

More information

15213 Recitation 2: Floating Point

15213 Recitation 2: Floating Point 15213 Recitation 2: Floating Point 1 Introduction This handout will introduce and test your knowledge of the floating point representation of real numbers, as defined by the IEEE standard. This information

More information

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1> Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building

More information

CPE300: Digital System Architecture and Design

CPE300: Digital System Architecture and Design CPE300: Digital System Architecture and Design Fall 2011 MW 17:30-18:45 CBC C316 Arithmetic Unit 10122011 http://www.egr.unlv.edu/~b1morris/cpe300/ 2 Outline Recap Fixed Point Arithmetic Addition/Subtraction

More information

An FPGA Implementation of the Powering Function with Single Precision Floating-Point Arithmetic

An FPGA Implementation of the Powering Function with Single Precision Floating-Point Arithmetic An FPGA Implementation of the Powering Function with Single Precision Floating-Point Arithmetic Pedro Echeverría, Marisa López-Vallejo Department of Electronic Engineering, Universidad Politécnica de Madrid

More information

COSC 243. Data Representation 3. Lecture 3 - Data Representation 3 1. COSC 243 (Computer Architecture)

COSC 243. Data Representation 3. Lecture 3 - Data Representation 3 1. COSC 243 (Computer Architecture) COSC 243 Data Representation 3 Lecture 3 - Data Representation 3 1 Data Representation Test Material Lectures 1, 2, and 3 Tutorials 1b, 2a, and 2b During Tutorial a Next Week 12 th and 13 th March If you

More information

Project Goals. Project Approach

Project Goals. Project Approach Project Goals Design a simple, but relatively complete, digital logic system in CMOS using a modern approach to logic cell design Estimate complexity, area, speed, power for a variety of possible technologies

More information

Accelerate FPGA Prototyping with

Accelerate FPGA Prototyping with Accelerate FPGA Prototyping with MATLAB and Simulink September 21 st 2010 Stephan van Beek Senior Application Engineer 1 From Idea to Implementation DESIGN Algorithm Development MATLAB Simulink Stateflow

More information

Number Systems. Both numbers are positive

Number Systems. Both numbers are positive Number Systems Range of Numbers and Overflow When arithmetic operation such as Addition, Subtraction, Multiplication and Division are performed on numbers the results generated may exceed the range of

More information

Designing with VHDL and FPGA

Designing with VHDL and FPGA Designing with VHDL and FPGA Instructor: Dr. Ahmad El-Banna lab# 5-II 1 Agenda Structural way in VHDL Mixed Example 2 Modeling the Structurural way Structural architecture implements the module as a composition

More information

Numbers and Computers. Debdeep Mukhopadhyay Assistant Professor Dept of Computer Sc and Engg IIT Madras

Numbers and Computers. Debdeep Mukhopadhyay Assistant Professor Dept of Computer Sc and Engg IIT Madras Numbers and Computers Debdeep Mukhopadhyay Assistant Professor Dept of Computer Sc and Engg IIT Madras 1 Think of a number between 1 and 15 8 9 10 11 12 13 14 15 4 5 6 7 12 13 14 15 2 3 6 7 10 11 14 15

More information

Intel s MMX. Why MMX?

Intel s MMX. Why MMX? Intel s MMX Dr. Richard Enbody CSE 820 Why MMX? Make the Common Case Fast Multimedia and Communication consume significant computing resources. Providing specific hardware support makes sense. 1 Goals

More information

Head, Dept of Electronics & Communication National Institute of Technology Karnataka, Surathkal, India

Head, Dept of Electronics & Communication National Institute of Technology Karnataka, Surathkal, India Mapping Signal Processing Algorithms to Architecture Sumam David S Head, Dept of Electronics & Communication National Institute of Technology Karnataka, Surathkal, India sumam@ieee.org Objectives At the

More information

Podcasting: How to Create Your Own in 30-Minutes

Podcasting: How to Create Your Own in 30-Minutes Podcasting: How to Create Your Own in 30-Minutes Podcasts Included in this Tutorial: o What is a Podcast? o What are the Learning Benefits of Podcasts? o Creating a Podcast with Audacity o Creating a Podcast

More information

CENG 3420 Lecture 05: Arithmetic and Logic Unit

CENG 3420 Lecture 05: Arithmetic and Logic Unit CENG 3420 Lecture 05: Arithmetic and Logic Unit Bei Yu byu@cse.cuhk.edu.hk CENG3420 L05.1 Spring 2017 Outline q 1. Overview q 2. Addition q 3. Multiplication & Division q 4. Shift q 5. Floating Point Number

More information

Storage I/O Summary. Lecture 16: Multimedia and DSP Architectures

Storage I/O Summary. Lecture 16: Multimedia and DSP Architectures Storage I/O Summary Storage devices Storage I/O Performance Measures» Throughput» Response time I/O Benchmarks» Scaling to track technological change» Throughput with restricted response time is normal

More information

Binary representation of integer numbers Operations on bits

Binary representation of integer numbers Operations on bits Outline Binary representation of integer numbers Operations on bits The Bitwise AND Operator The Bitwise Inclusive-OR Operator The Bitwise Exclusive-OR Operator The Ones Complement Operator The Left Shift

More information

Finite arithmetic and error analysis

Finite arithmetic and error analysis Finite arithmetic and error analysis Escuela de Ingeniería Informática de Oviedo (Dpto de Matemáticas-UniOvi) Numerical Computation Finite arithmetic and error analysis 1 / 45 Outline 1 Number representation:

More information

SH4 RISC Microprocessor for Multimedia

SH4 RISC Microprocessor for Multimedia SH4 RISC Microprocessor for Multimedia Fumio Arakawa, Osamu Nishii, Kunio Uchiyama, Norio Nakagawa Hitachi, Ltd. 1 Outline 1. SH4 Overview 2. New Floating-point Architecture 3. Length-4 Vector Instructions

More information

EE577A FINAL PROJECT REPORT Design of a General Purpose CPU

EE577A FINAL PROJECT REPORT Design of a General Purpose CPU EE577A FINAL PROJECT REPORT Design of a General Purpose CPU Submitted By Youngseok Lee - 4930239194 Narayana Reddy Lekkala - 9623274062 Chirag Ahuja - 5920609598 Phase 2 Part 1 A. Introduction The core

More information

mith College Computer Science Fixed & Floating Point Formats CSC231 Fall 2017 Week #15 Dominique Thiébaut

mith College Computer Science Fixed & Floating Point Formats CSC231 Fall 2017 Week #15 Dominique Thiébaut mith College Computer Science Fixed & Floating Point CSC231 Fall 2017 Week #15 Formats Dominique Thiébaut dthiebaut@smith.edu Trick Question for ( double d = 0; d!= 0.3; d += 0.1 ) System.out.println(

More information

COPROCESSOR APPROACH TO ACCELERATING MULTIMEDIA APPLICATION [CLAUDIO BRUNELLI, JARI NURMI ] Processor Design

COPROCESSOR APPROACH TO ACCELERATING MULTIMEDIA APPLICATION [CLAUDIO BRUNELLI, JARI NURMI ] Processor Design COPROCESSOR APPROACH TO ACCELERATING MULTIMEDIA APPLICATION [CLAUDIO BRUNELLI, JARI NURMI ] Processor Design Lecture Objectives Background Need for Accelerator Accelerators and different type of parallelizm

More information

CS101 Introduction to computing Floating Point Numbers

CS101 Introduction to computing Floating Point Numbers CS101 Introduction to computing Floating Point Numbers A. Sahu and S. V.Rao Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati 1 Outline Need to floating point number Number representation

More information

Lecture 15: System Modeling and Verilog

Lecture 15: System Modeling and Verilog Lecture 15: System Modeling and Verilog Slides courtesy of Deming Chen Intro. VLSI System Design Outline Outline Modeling Digital Systems Introduction to Verilog HDL Use of Verilog HDL in Synthesis Reading

More information

Implementation and Impact of LNS MAC Units in Digital Filter Application

Implementation and Impact of LNS MAC Units in Digital Filter Application Implementation and Impact of LNS MAC Units in Digital Filter Application Hari Krishna Raja.V.S *, Christina Jesintha.R * and Harish.I * * Department of Electronics and Communication Engineering, Sri Shakthi

More information

Timing for Ripple Carry Adder

Timing for Ripple Carry Adder Timing for Ripple Carry Adder 1 2 3 Look Ahead Method 5 6 7 8 9 Look-Ahead, bits wide 10 11 Multiplication Simple Gradeschool Algorithm for 32 Bits (6 Bit Result) Multiplier Multiplicand AND gates 32

More information

Implementation of DSP Algorithms

Implementation of DSP Algorithms Implementation of DSP Algorithms Main frame computers Dedicated (application specific) architectures Programmable digital signal processors voice band data modem speech codec 1 PDSP and General-Purpose

More information

FPGA Implementation of Multiplierless 2D DWT Architecture for Image Compression

FPGA Implementation of Multiplierless 2D DWT Architecture for Image Compression FPGA Implementation of Multiplierless 2D DWT Architecture for Image Compression Divakara.S.S, Research Scholar, J.S.S. Research Foundation, Mysore Cyril Prasanna Raj P Dean(R&D), MSEC, Bangalore Thejas

More information

FPGA Based Antilog Computation Unit with Novel Shifter

FPGA Based Antilog Computation Unit with Novel Shifter International Journal of Engineering Trends and Technology (IJETT) Volume 3 Number 3- January 6 FPGA Based Antilog Computation nit with Novel Shifter Swapna Kalyani P #, Lakshmi Priyanka S *, Santhosh

More information

SIMULINK AS A TOOL FOR PROTOTYPING RECONFIGURABLE IMAGE PROCESSING APPLICATIONS

SIMULINK AS A TOOL FOR PROTOTYPING RECONFIGURABLE IMAGE PROCESSING APPLICATIONS SIMULINK AS A TOOL FOR PROTOTYPING RECONFIGURABLE IMAGE PROCESSING APPLICATIONS B. Kovář, J. Schier Ústav teorie informace a automatizace AV ČR, Praha P. Zemčík, A. Herout, V. Beran Ústav počítačové grafiky

More information

CENG3420 L05: Arithmetic and Logic Unit

CENG3420 L05: Arithmetic and Logic Unit CENG3420 L05: Arithmetic and Logic Unit Bei Yu byu@cse.cuhk.edu.hk (Latest update: January 25, 2018) Spring 2018 1 / 53 Overview Overview Addition Multiplication & Division Shift Floating Point Number

More information

ISSN:

ISSN: 1441 A NOVEL DESIGN APPROACH TO INCREASE THE SPEED OF VLSI CIRCUITS IN MIXED-SIGNAL ENVIRONMENT R.PRAKASH RAO 1, B.K.MADHAVI 2 1 Associate Professor, St.Peter s Engineering College,Near Forest Academy,

More information

ECE 2300 Digital Logic & Computer Organization

ECE 2300 Digital Logic & Computer Organization ECE 2300 Digital Logic & Computer Organization Spring 201 Memories Lecture 14: 1 Announcements HW6 will be posted tonight Lab 4b next week: Debug your design before the in-lab exercise Lecture 14: 2 Review:

More information

FFT/IFFT Block Floating Point Scaling

FFT/IFFT Block Floating Point Scaling FFT/IFFT Block Floating Point Scaling October 2005, ver. 1.0 Application Note 404 Introduction The Altera FFT MegaCore function uses block-floating-point (BFP) arithmetic internally to perform calculations.

More information

Lecture 7. Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits. Hardware Description Language)

Lecture 7. Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits. Hardware Description Language) Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits Hardware Description Language) 1 Standard ICs PLD: Programmable Logic Device CPLD: Complex PLD FPGA: Field Programmable

More information

Byeong-Gyu Nam, Jeabin Lee, Kwanho Kim, Seung Jin Lee, and Hoi-Jun Yoo

Byeong-Gyu Nam, Jeabin Lee, Kwanho Kim, Seung Jin Lee, and Hoi-Jun Yoo A Low-Power Handheld GPU using Logarithmic Arithmetic and Triple DVFS Power Domains Byeong-Gyu Nam, Jeabin Lee, Kwanho Kim, Seung Jin Lee, and Hoi-Jun Yoo Outline Backgrounds Proposed Handheld GPU Low-Power

More information

Computer Organization and Levels of Abstraction

Computer Organization and Levels of Abstraction Computer Organization and Levels of Abstraction Announcements Today: PS 7 Lab 8: Sound Lab tonight bring machines and headphones! PA 7 Tomorrow: Lab 9 Friday: PS8 Today (Short) Floating point review Boolean

More information

Evaluation of High Speed Hardware Multipliers - Fixed Point and Floating point

Evaluation of High Speed Hardware Multipliers - Fixed Point and Floating point International Journal of Electrical and Computer Engineering (IJECE) Vol. 3, No. 6, December 2013, pp. 805~814 ISSN: 2088-8708 805 Evaluation of High Speed Hardware Multipliers - Fixed Point and Floating

More information

Fundamental Design Concepts. Fundamental Concepts. Modeling Domains. Basic Definitions. New terminology and overloaded use of common words

Fundamental Design Concepts. Fundamental Concepts. Modeling Domains. Basic Definitions. New terminology and overloaded use of common words Fundamental Design Concepts Fundamental Concepts Basic Definitions study now revisit later New terminology and overloaded use of common words Modeling Domains Structural Domain a domain in which a component

More information

Representing and Manipulating Floating Points. Jo, Heeseung

Representing and Manipulating Floating Points. Jo, Heeseung Representing and Manipulating Floating Points Jo, Heeseung The Problem How to represent fractional values with finite number of bits? 0.1 0.612 3.14159265358979323846264338327950288... 2 Fractional Binary

More information

TSIU03, SYSTEM DESIGN LECTURE 10

TSIU03, SYSTEM DESIGN LECTURE 10 LINKÖPING UNIVERSITY Department of Electrical Engineering TSIU03, SYSTEM DESIGN LECTURE 10 Mario Garrido Gálvez mario.garrido.galvez@liu.se Linköping, 2018 1 TODAY Time and frequency domains. Parameterizing

More information

Digital Logic & Computer Design CS Professor Dan Moldovan Spring 2010

Digital Logic & Computer Design CS Professor Dan Moldovan Spring 2010 Digital Logic & Computer Design CS 434 Professor Dan Moldovan Spring 2 Copyright 27 Elsevier 5- Chapter 5 :: Digital Building Blocks Digital Design and Computer Architecture David Money Harris and Sarah

More information

ECE 2030B 1:00pm Computer Engineering Spring problems, 5 pages Exam Two 10 March 2010

ECE 2030B 1:00pm Computer Engineering Spring problems, 5 pages Exam Two 10 March 2010 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

Chapter 2 Using Hardware Description Language Verilog. Overview

Chapter 2 Using Hardware Description Language Verilog. Overview Chapter 2 Using Hardware Description Language Verilog CSE4210 Winter 2012 Mokhtar Aboelaze based on slides by Dr. Shoab A. Khan Overview Algorithm development isa usually done in MATLAB, C, or C++ Code

More information

EE 434 ASIC & Digital Systems

EE 434 ASIC & Digital Systems EE 434 ASIC & Digital Systems Dae Hyun Kim EECS Washington State University Spring 2018 Course Website http://eecs.wsu.edu/~ee434 Themes Study how to design, analyze, and test a complex applicationspecific

More information

A SIMULINK-TO-FPGA MULTI-RATE HIERARCHICAL FIR FILTER DESIGN

A SIMULINK-TO-FPGA MULTI-RATE HIERARCHICAL FIR FILTER DESIGN A SIMULINK-TO-FPGA MULTI-RATE HIERARCHICAL FIR FILTER DESIGN Xiaoying Li 1 Fuming Sun 2 Enhua Wu 1, 3 1 University of Macau, Macao, China 2 University of Science and Technology Beijing, Beijing, China

More information

A Low Power Asynchronous FPGA with Autonomous Fine Grain Power Gating and LEDR Encoding

A Low Power Asynchronous FPGA with Autonomous Fine Grain Power Gating and LEDR Encoding A Low Power Asynchronous FPGA with Autonomous Fine Grain Power Gating and LEDR Encoding N.Rajagopala krishnan, k.sivasuparamanyan, G.Ramadoss Abstract Field Programmable Gate Arrays (FPGAs) are widely

More information

Representing and Manipulating Floating Points

Representing and Manipulating Floating Points Representing and Manipulating Floating Points Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu The Problem How to represent fractional values with

More information

Corrections for Digital Systems Design Using VHDL, 3rd printing

Corrections for Digital Systems Design Using VHDL, 3rd printing Corrections for Digital Systems Design Using VHDL, 3rd printing Corrected VHDL code can be found on the web page: http://www.brookscole.com/engineering/ee/roth.html line 7 means 7th line from bottom, etc.

More information

Computer Arithmetic Floating Point

Computer Arithmetic Floating Point Computer Arithmetic Floating Point Chapter 3.6 EEC7 FQ 25 About Floating Point Arithmetic Arithmetic basic operations on floating point numbers are: Add, Subtract, Multiply, Divide Transcendental operations

More information

hp calculators HP 20b Using Memories to Solve Problems Constant memory and planning Memory registers Other memory locations

hp calculators HP 20b Using Memories to Solve Problems Constant memory and planning Memory registers Other memory locations HP 20b Using Memories to Solve Problems Constant memory and planning Memory registers Other memory locations Understanding register arithmetic Viewing register contents Clearing memories Practice using

More information

FPGA Implementation of Low-Area Floating Point Multiplier Using Vedic Mathematics

FPGA Implementation of Low-Area Floating Point Multiplier Using Vedic Mathematics FPGA Implementation of Low-Area Floating Point Multiplier Using Vedic Mathematics R. Sai Siva Teja 1, A. Madhusudhan 2 1 M.Tech Student, 2 Assistant Professor, Dept of ECE, Anurag Group of Institutions

More information

Basics of Computation. PHY 604:Computational Methods in Physics and Astrophysics II

Basics of Computation. PHY 604:Computational Methods in Physics and Astrophysics II Basics of Computation Basics of Computation Computers store information and allow us to operate on it. That's basically it. Computers have finite memory, so it is not possible to store the infinite range

More information

In this article, we present and analyze

In this article, we present and analyze [exploratory DSP] Manuel Richey and Hossein Saiedian Compressed Two s Complement Data s Provide Greater Dynamic Range and Improved Noise Performance In this article, we present and analyze a new family

More information