AN Home Power Line Support for the LAN91C Introduction APPLICATION NOTE

Transcription

1 AN Home Power Line Support for the LAN91C111 1 Introduction This document describes how SMSC's family of 10/100 Ethernet MAC/PHY solutions can be configured to allow both Ethernet "10/100Base-t" as well as "Home Power Line" or "HomePlug" technology solutions for multiple physical layer connectivity. Interoperability results will also be discussed showing how the SMSC LAN91C111 and Home Power Line Manufacturers such as Cogency and Intellon's physical layer solutions function together. Cogency's power line integrated circuit and Intellon EK51MX HomePlug evaluation kit, in conjunction with SMSC LAN91C111 Ethernet MAC, makes use of existing in-home AC electrical wires for transmitting digital data at high speed. The connection medium between the Mac and Home Plug PHY is the MII (Medium Independent Interface). The AC power line network can be a harsh environment for data communication. To compensate, Cogency and Intellon uses orthogonal frequency-division multiplexing (OFDM) in the 4.5 to 21 MHz band and a sophisticated forward error correction scheme to provide reliable data transmission. Network security risks are addressed by encrypting data to create a private Logical Network in the home if the customer requires. Password-bound encryption keys, private to the home network, are used to encrypt each message as it is sent and decrypt data as it is received. Even if data is intercepted outside the home, it remains secure. OFDM-based physical layer support, which is compatible with the HomePlug Power line specification, and is the industry standard for power line home networking is used in this solution. SMSC's Ethernet MAC, with Cogency's PHY solution, is ideal for a broad range of networking, entertainment and computer products such as network cards, PC motherboards, network adapters, cable and DSL modems, MP3 players, jukeboxes, and Internet appliances. SMSC's Ethernet MAC with both an integrated 10/100 Base-T Phy with Cogency or Intellon's "Home Plug" technology permits data transfer rates at 10 Mbps Ethernet-class speeds using ordinary in-home electrical wires as well as 100Mbps Ethernet-class speeds using standard CAT-5 twisted pair wiring. The diagram shown in Figure 1.1 Typical Application on page 2, describes a system configuration that is using the SMSC LAN91C111 and Cogency's CS1100 DSP PHY and CS5100 AFE chip set. This solution would allow a system designer to create a solution that can connect to a standard 10/100 CAT5 Ethernet LAN as well as connecting a network via the building's Power Line infrastructure. Note that this solution is utilizing the Cogency's external Home Plug PHY and the internal PHY of the SMSC LAN91C111 for its 10/100Base-t solution. Both networks cannot be used at the same time. The SMSC LAN91C111 MAC interfaces to the internal PHY or external Home Plug PHY via a MII interface. No bridging or router functionality is possible in this design. Revision 1.0 ( ) SMSC AN 10.17

2 Embedded Processor Network Appliance Local Bus SMSC LAN91C111 10/100 Base-t Home Network MII Cogency CS1100 DSP/PHY Cogency CS5100 Mixed Signal AFE Home Plug Enabled Power Supply Figure 1.1 Typical Application In addition, Intellon Corporation produces a family of IC devices for low-cost, high-speed in-home communications. The main product consists of a Base band and Analog Front-End (AFE) IC. The INT51MX SIMPLETM Embedded PowerPacketTM Module is a Single Inline Package (SIP) device that incorporates the INT51X1 IC and required support circuitry to provide a single component solution for the addition of PLC functionality to a product. The block diagram utilizing this Home Power Line solution with SMSC's Ethernet Controller is shown in Figure 1.2 Intellon / SMSC Home Power and Home Network Solution Block Diagram on page 3. Revision 1.0 ( ) 2 SMSC AN 10.17

3 Embedded Processor Network Appliance Local Bus SMSC LAN91C111 10/100 Base-t Home Network MII Intellon INT51X1 Mixed Signal AFE INT51MX SIMPLETM Embedded PowerPacketTM Module Home Plug Enabled Power Supply Power Line Figure 1.2 Intellon/SMSC Home Power and Home Network Solution Block Diagram 2 Intellon Interoperability Testing For this interoperability test, the evaluation board with SMSC LAN91C111 MAC and Intellon PHY must be configured. The device driver software must be modified to work with the hardware configuration. The hardware components in this test include: SMSC LAN91C111 Engineering Board ASSY 6181 Rev-A IntellonEK51MX HomePlug evaluation kit The software components in this test include: Modified SMSC LAN91C111 Device Driver for Windows 2000/XP 2.1 Test Configuration Hardware Configuration The SMSC LAN91C111 Engineering Board ASSY 6181 Rev-A (SMSC LAN91C111 evaluation board) is used as an ISA 10/100 Ethernet MAC plus 10/100base-t evaluation board and is used to integrate with Intellon's EK51MX HomePlug evaluation kit for the test. Figure 2.1 Intellon and SMSC Board Layout on page 4, shows the configuration for the tests done. SMSC AN Revision 1.0 ( )

4 The Intellon EK51MX HomePlug evaluation kit includes Intellon's SIMPLE Evaluation Module, PHY Interface Board, Host/DTE Interface Board and PowerPacket DC Wall Adapter. The PHY Interface Board is connected to SMSC LAN91C111 evaluation board through the MII interface via the cable connector shown in the diagram. Note that no modifications to the MII interface is required in this design. The Intellon solution main product consists of a Baseband and Analog Front-End (AFE) IC. This IC is available in a 144 pin µbga package. The designer takes this IC and adds the required support circuitry to develop a power line communication (PLC) device. The INT51MX SIMPLETM Embedded PowerPacketTM Module is a Single Inline Package (SIP) device that incorporates the INT51X1 IC and required support circuitry to provide a single component solution for the addition of PLC functionality to a product. SMSC's Ethernet controller, in conjunction with Intellon's PLC, offers a designer a Home Power Line and standard Home Network 10/100 Base-t solution in a simple design. The analog front-end circuitry for the PLC module is optimized for performance in the applications that use a direct connection to AC line (wall- module) or use Intellon DC coupler adapter (INT51M0) or applications running a standard 6' AC line cord (INT51M6). The two modules share the same PCB and Gerber layout files. The PCM module is configured in its INT51MX PHY Option: An MII (IEEE 802.3u 1995, Paragraph 22) or GPSI PHY interface for interconnection to micro controllers or Ethernet controllers. The INT51MX (PHY Option) is selected by connecting MODE0 pin to VSS. Figure 2.1 Intellon and SMSC Board Layout

5 The following modifications must be done on the PHY Interface Board in order to enable the EK51MX's PHY mode and the MII interface: 1. A male MII connector is soldered on the PHY Interface Board. 2. Connect Pin 31 (MODE0) to Pin 34 (VSS) on Host Module Connector to enable the PHY mode. 3. Connect Pin 32 (MDI_SPIS_N) to Pin 6 (VDDH) on Host Module Connector to enable the MII interface. On the SMSC LAN91C111 evaluation board side, the J3 jumper must be set to 2-3 to enable the +5V on the MII connector. Please refer to the picture shown in Figure 2.2 Close-Up View of Intellon Jumper Configuration on page 5, for additional details. EK51MX is connected directly to the MII interface of the LAN91C111. The internal PHY of LAN91C111 is disabled by setting the EXT PHY bit of MAC Configuration Register (Bank 1, Offset 0). This will enable the external PHY, the PHY of Intellon's EK51MX. The PHY address of the EK51MX is set as 01000b. Figure 2.2 Close-Up View of Intellon Jumper Configuration Software Configuration The LAN91C111 evaluation board device driver for Windows 2000/XP is modified to disable the internal PHY on LAN91C111 and enable the external PHY, which is Intellon's PHY. Auto-negotiation is also disabled, since Intellon's PHY does not support auto-negotiation. SMSC AN Revision 1.0 ( )

6 The following is an implementation sample of the initialization module. Assume the Windows XP NDIS Miniport model is used in the sample. BOOLEAN InitializeLink(MINIPORT_ADAPTER *Adapter) { USHORT temp; int timeout; DebugPrint(DEBUG_LEVEL_TRACE, ("Initializing Link \r\n")); // Enable external PHY DebugPrint(DEBUG_LEVEL_TRACE, ("Enabling external PHY...\r\n")); NdisRawWritePortUshort( Adapter->IOBase + BANK_SELECT, (USHORT) 1 ); NdisRawReadPortUshort( Adapter->IOBase + BANK1_CONFIG, &temp); temp = 0x0200; NdisRawWritePortUshort( Adapter->IOBase + BANK1_CONFIG, temp ); WritePhyRegister(Adapter->IOBase, 0, 0); // Clear PHY control register // Reset the PHY DebugPrint(DEBUG_LEVEL_TRACE, ("Resetting the PHY...\r\n")); WritePhyRegister(Adapter->IOBase, 0, 0x8000); // Set Reset bit in PHY Control register timeout = 5; // 5-second timeout while(timeout--) { temp = ReadPhyRegister(Adapter->IOBase, 0); // If Reset bit is cleared, reset is done. if (temp & 0x8000) break; Delay1mS(500); DebugPrint(DEBUG_LEVEL_TRACE, ("End of Resetting the PHY.\r\n")); // Disable AutoNeg from 91C111 M AC; // Set speed to 10Mbps; // Set duplex mode to Half Duplex; // Set LED to "Transmit/Receiving Packet Occurred" NdisRawWritePortUshort( Adapter->IOBase + BANK_SELECT, (USHORT) 0 ); NdisRawWritePortUshort( Adapter->IOBase + BANK0_RPCR, 0x0010); // Check link status timeout = 5; // 5-second timeout while(timeout--) { temp = ReadPhyRegister(Adapter->IOBase, 1); // If LNK bit is set, link is up. if (temp & 0x0004) break; Delay1mS(500); // Check if link is set up in time and tell upper layer the link status. if(timeout < 1) { DebugPrint(DEBUG_LEVEL_TRACE, ("Link is down.\r\n")); Adapter->LinkStatus = MEDIA_DISCONNECTED; else { Adapter->LinkStatus = MEDIA_CONNECTED; DebugPrint(DEBUG_LEVEL_TRACE, ("Link is up.\r\n")); DebugPrint(DEBUG_LEVEL_TRACE, ("End of Initializing Link.\r\n")); return TRUE; Revision 1.0 ( ) 6 SMSC AN 10.17

7 2.1.3 Test application and Setup Evaluation version of the network test software SpeedTest is used for the throughput testing. The following is the test setup. Power Strip Host #1 Windows 2000 with SpeedTest Server with SMSC LAN91C111 evaluation board and Intellon EK51MX evaluation kit Host #2 Windows 2000 with SpeedTest Client with LinkSys Instant PowerLine Ethernet 10/100 Bridge (Model PLEBR10) Figure 2.3 Test Setup The modified Windows driver for SMSC LAN91C111 evaluation board is installed on Host #1. Two kinds of tests are performed: Ping test and throughput test. The Ping test is using Windows Ping command ping from either computer to the other one and Ping on both directions at the same time. The throughput test is done using a evaluation version of SpeedTest software to measure the throughput of the transmission. The SpeedTest Server is installed and started on Host #2, while the SpeedTest Client is installed and started on the Host #1. The SpeedTest tests the network throughput by connecting to the SpeedTest server, transferring a file and measuring the speed of the transfer. A compressed file is used for more accurate results. 2.2 Test Results Ping Test For the test environment discussed above, Ping, in single shot mode, passed. The "Continuous Pings" test, which includes "Continuous Pings from both sides", performed well with no errors Throughput Test The following diagram shown in Figure 2.4 Screen Capture of the SpeedTest Client on page 8, is the screen capture of the SpeedTest Client, which shows the measured throughput of the transfer of a 16MB compressed file, a 1.2MB compressed file from SpeedTest Server to Client. The throughput averaged on the order of 660 Kbytes/s. The following diagram shown in Figure 2.5 Additional Screen Capture of the SpeedTest Client on page 8 Additional Screen Capture of the SpeedTest Client, is another screen shot for the test for transferring a larger file - 88MB compressed file. SMSC AN Revision 1.0 ( )

8 Figure 2.4 Screen Capture of the SpeedTest Client Figure 2.5 Additional Screen Capture of the SpeedTest Client Revision 1.0 ( ) 8 SMSC AN 10.17

9 3 Cogency Interoperability Testing In order to verify and validate that SMSC's Ethernet MAC/PHY solution operates correctly with Cogency's DSP PHY and AFE solution, testing and validation was done. For interoperability testing, the following modifications and changes needed to be made: 1. SMSC's evaluation board with SMSC LAN91C111 MAC and Cogency PHY was modified and configured through a special MII cable. 2. The SMSC LAN91C111 device driver software was be modified to work with this specific hardware configuration. 3. Typically, a specific Power Supply module is used to allow the sourcing of power while creating a signal to and from the Power supply and Cogency AFE PHY interface. For test purposes, this special power supply was not used. Instead, direct connection between AFE's was done. The hardware components in this test include: SMSC LAN91C111 Engineering Board ASSY 6181 Rev-A Cogency HomePlug Module evaluation board The software components in this test include: Modified SMSC LAN91C111 Device Driver for Windows 2000/XP 3.1 Test Configuration The diagram shown below describes the connection configuration between the SMSC LAN91C111 and the Cogency PHY. The CS1100 HomePlug Module is connected directly to the MII interface of the LAN91C111. In this MII interface connection, it requires that the CS1100 share the MII with the internal PHY of LAN91C111. The single clock output of the CS1100 (MII_CLK) drives both RX_CLK and TX_CLK from one source to LAN91C111. With this application, the only PHY present on the MII is the PHY of CS1100. Driving the MII clocks from one source presents no problem. SMSC AN Revision 1.0 ( )

10 TX_CLK RX_CLK M II_C LK TX_EN TX_EN TX_ER Open TXD0 TXD0 TXD1 TXD1 TXD2 TXD2 LAN91C111 Evaluation Board MAC / PHY LAN91C111 MII Interface TXD3 RX_DV RX_ER RXD0 TXD3 RX_DV RX_ER RXD0 CS1100 HomePlug Module MAC / PHY RXD1 RXD1 RXD2 RXD2 RXD3 RXD3 CRS CRS COL COL MDC MDC MDIO MDIO Figure 3.1 MII Interface Mode Connection with LAN91C111 The internal PHY of LAN91C111 is disabled by setting the EXT PHY bit of MAC Configuration Register (Bank 1, Offset 0). This will enable the external PHY, the PHY of Cogency CS1100. The bit 1, 2 and 3 of the Configuration Strap Settings on the HomePlug module are set to 101b. Therefore the PHY address is selected as 01000b. Two identical boards are configured and connected through a two-pin connector built-in on the Cogency HomePlug module. According to Cogency's technical contact, for the interoperability test, the special HomePlug enabled power supply is not needed, since the signaling on the two-pin cable is identical to that on the power line. 3.2 Hardware Configuration The image shown in Figure 3.2 SMSC - Cogency Test Environment on page 11, shows the SMSC LAN91C111 Engineering Board ASSY 6181 Rev-A (The name "SMSC LAN91C111 evaluation board"). This board is an ISA evaluation board that also has an external MII interface. This interface is used to integrate with Cogency's HomePlug evaluation board used in the tests performed. Cogency HomePlug evaluation board includes Cogency's Piranha SE chipset, a complete analog front end with coupling and local DC-DC power conversion. The HomePlug module is connected to SMSC LAN91C111 evaluation board through this MII interface. The SMSC LAN91C111 reference design interfaces to the Host via a ISA style bus connector. The diagram also shows the MII interface connection (White Wires) as well as the Home Plug emulation wires running between the two ISA cards. Revision 1.0 ( ) 10 SMSC AN 10.17

11 Figure 3.2 SMSC - Cogency Test Environment Figure 3.3 Close-Up View of SMSC PartNumber Reference ISA Card Wired via MII 3.3 Software Configuration The SMSC LAN91C111 evaluation board device driver for Windows 2000/XP was modified to: 1. Disable the internal PHY on the SMSC LAN91C Enable the external PHY, which is Cogency's Home Power Line PHY SMSC AN Revision 1.0 ( )

12 3. Auto-negotiation was disabled (Cogency's PHY does not support auto-negotiation) The following is an implementation sample of the initialization module. The Windows XP NDIS Miniport model is used in the sample. BOOLEAN InitializeLink(MINIPORT_ADAPTER *Adapter) { USHORT temp; int timeout; DebugPrint(DEBUG_LEVEL_TRACE, ("Initializing Link \r\n")); // Enable external PHY DebugPrint(DEBUG_LEVEL_TRACE, ("Enabling external PHY...\r\n")); NdisRawWritePortUshort( Adapter->IOBase + BANK_SELECT, (USHORT) 1 ); NdisRawReadPortUshort( Adapter->IOBase + BANK1_CONFIG, &temp); temp = 0x0200; NdisRawWritePortUshort( Adapter->IOBase + BANK1_CONFIG, temp ); WritePhyRegister(Adapter->IOBase, 0, 0); // Clear PHY control register // Reset the PHY DebugPrint(DEBUG_LEVEL_TRACE, ("Resetting the PHY...\r\n")); WritePhyRegister(Adapter->IOBase, 0, 0x8000); // Set Reset bit in PHY Control register timeout = 5; // 5-second timeout while(timeout--) { temp = ReadPhyRegister(Adapter->IOBase, 0); // If Reset bit is cleared, reset is done. if (temp & 0x8000) break; Delay1mS(500); DebugPrint(DEBUG_LEVEL_TRACE, ("End of Resetting the PHY.\r\n")); // Disable AutoNeg from 91C111 M AC; // Set speed to 10Mbps; // Set duplex mode to Half Duplex; // Set LED to "Transmit/Receiving Packet Occurred" NdisRawWritePortUshort( Adapter->IOBase + BANK_SELECT, (USHORT) 0 ); NdisRawWritePortUshort( Adapter->IOBase + BANK0_RPCR, 0x0010); // Check link status timeout = 5; // 5-second timeout while(timeout--) { temp = ReadPhyRegister(Adapter->IOBase, 1); // If LNK bit is set, link is up. if (temp & 0x0004) break; Delay1mS(500); // Check if link is set up in time and tell upper layer the link status. if(timeout < 1) { DebugPrint(DEBUG_LEVEL_TRACE, ("Link is down.\r\n")); Adapter->LinkStatus = MEDIA_DISCONNECTED; else { Adapter->LinkStatus = MEDIA_CONNECTED; DebugPrint(DEBUG_LEVEL_TRACE, ("Link is up.\r\n")); DebugPrint(DEBUG_LEVEL_TRACE, ("End of Initializing Link.\r\n")); return TRUE; Revision 1.0 ( ) 12 SMSC AN 10.17

13 The high level application used was the evaluation version of the network test software "SpeedTest" is used for the throughput testing. The software can be found at the following URL: The following is the test setup: 2-Wire Cable Connecting HomePlug Modules Windows 2000 with SpeedTest Server Windows 2000 with SpeedTest Client Figure 3.4 Test Setup 1. Install the modified Windows driver for SMSC LAN91C111 evaluation board with HomePlug module is installed on both computers 2. Run the "Ping" test and "throughput" test 3. The Ping test uses the Windows Ping command ping from either computer to the other one and Ping on both directions at the same time. 4. The throughput test is done using a evaluation version of SpeedTest software to measure the throughput of the transmission. The SpeedTest Server is installed and started on one computer, while the SpeedTest Client is installed and started on the other one. The SpeedTest tests the network throughput by connecting to the SpeedTest server, transferring a file and measuring the speed of the transfer. A compressed file is used for more accurate results. 3.4 Test Results Throughput Test The following is the screen capture of the SpeedTest Client, which shows the measured throughput of the transfer of a 1.16MB compressed file and a 3.9MB compressed file from SpeedTest Server to Client. SMSC AN Revision 1.0 ( )

14 4 Summary Figure 3.5 Speed Test Client The throughput for a 1.16MB file transfer is KB/s and for a 3.86MB file is KB/s. This document described how SMSC's family of 10/100 Ethernet MAC/PHY solutions can be configured to allow both Ethernet "10/100Base-t" as well as "Home Power Line" or "HomePlug" technology solutions for multiple physical layer connectivity. Interoperability results that were discussed showed how the SMSC LAN91C111 and Home Power Line Manufacturers such as Cogency Semiconductor and Intellon's physical layer solutions can function together. Cogency's power line integrated circuit and Intellon EK51MX HomePlug evaluation kit, in conjunction with SMSC LAN91C111 Ethernet MAC, via the MII (Media Independent Interface), will make use of existing in-home AC electrical wires for transmitting digital data at high speed. The AC power line network can be a harsh environments for data communication as well as standard 10/100 Base-t physical layer routing within a home utilizing CAT5 cable offering flexible wiring options. 5 Revision History NAME REVISION LEVEL AND DATE SECTION/FIGURE/ENTRY CORRECTION Marcom Revision 1.0 ( ) Standard SMSC Formatting Revision 1.0 ( ) 14 SMSC AN 10.17

15 80 ARKAY DRIVE, HAUPPAUGE, NY (631) , FAX (631) Copyright 2009 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC s website at SMSC is a registered trademark of Standard Microsystems Corporation ( SMSC ). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. SMSC AN Revision 1.0 ( )