DDR4 SDRAM UDIMM MTA16ATF1G64AZ 8GB. Features. 8GB (x64, DR) 288-Pin DDR4 UDIMM. Features. Figure 1: 288-Pin UDIMM (MO-309, R/C-B)

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1 DDR4 SDRAM UDIMM MTA6ATFG64AZ 8GB 8GB (x64, DR) 88-Pin DDR4 UDIMM Features Features DDR4 functionality and operations supported as defined in the component data sheet 88-pin, unbuffered dual in-line memory module (UDIMM) Fast data transfer rates: PC4-400, PC4-33, or PC GB ( Gig x 64) V DD =.V (typical) V PP =.5V (typical) V DDSPD =. 3.6V Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals Low-power auto self refresh (LPASR) Data bus inversion (DBI) for data bus On-die V REF generation and calibration Dual-rank On-board serial presence-detect (SPD) EEPROM 6 internal banks; 4 groups of 4 banks each Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) Selectable BC4 or BL8 on-the-fly (OTF) Gold edge contacts Halogen-free Fly-by topology Terminated control, command, and address bus Figure : 88-Pin UDIMM (MO-309, R/C-B) Module height: 3.5mm (.3in) Options Marking Operating temperature Commercial (0 C T OPER +95 C) None Package 88-pin DIMM (halogen-free) Z Frequency/CAS latency CL = 6 (DDR4-400) -G4 CL = 5 (DDR4-33) CL = 3 (DDR4-866) -G9 Table : Key Timing Parameters Speed Grade Industry Nomenclature Data Rate (MT/s) CL = 8 CL = 6 CL = 5 CL = 4 CL = 3 CL = CL = CL = 9 -G4 PC G PC G9 PC t RCD (ns) t RP (ns) t RC (ns) Products and specifications discussed herein are subject to change by Micron without notice.

2 8GB (x64, DR) 88-Pin DDR4 UDIMM Features Table : Addressing Parameter Row address Column address Device bank group address Device bank address per group Device configuration Module rank address 8GB 3K A[4:0] K A[9:0] 4 BG[:0] 4 BA[:0] 4Gb (5 Meg x 8), 6 banks CS_n[:0] Table 3: Part Numbers and Timing Parameters 8GB Modules Base device: MT40A5M8, 4Gb DDR4 SDRAM Part Number Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL- t RCD- t RP) MTA6ATFG64AZ-G4 8GB Gig x GB/s 0.83ns/400 MT/s MTA6ATFG64AZ-G 8GB Gig x GB/s 0.93ns/33 MT/s MTA6ATFG64AZ-G9 8GB Gig x GB/s.07ns/866 MT/s Notes:. The data sheet for the base device can be found on Micron s web site.. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MTA6ATFG64AZ-GA.

3 8GB (x64, DR) 88-Pin DDR4 UDIMM Pin Assignments Pin Assignments Table 4: Pin Assignments 88-Pin DDR4 UDIMM Front 88-Pin DDR4 UDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol V DD 09 V ss V DD CK0_t 0 DM5_n/ DBI5_n, 46 V REFCA 8 8 CK_t CK0_c CK_c 55 S5_c 4 40 DM3_n/ DBI3_n, 76 V DD V DD 56 S5_t V TT S3_c V TT EVENT_n, S3_t PARITY NF 7 DM0_n/ DBI0_n, A V DD V DD 6 5 S0_c BA BA S0_t 89 5 A0_AP RAS_n/ V DD 6 53 A6 47 CB4/ 83 V DD CS0_n CB5, 8 WE_n/ A CB0/ 85 V DD DM6_n/ DBI6_n, CAS_n/ A5 5 5 DM8_n/ DBI8_n, V DD CB, S6_c 87 ODT V DD 67 S6_t V DD S8_c 3 A CS_n S8_t 33 V DD DMI_n/ DBI_n, 54 CB6/ DBI8_n, 90 V DD ODT 7 63 S_c 99 CB7, CB/ 9 V DD S_t V DD CB3, RESET_n SA V DD CKE CKE DM7_n/ DBI7_n, V DD V DD S7_c 6 6 ACT_n V DD S7_t BG0 99 DM4_n/ DBI4_n, BG

4 8GB (x64, DR) 88-Pin DDR4 UDIMM Pin Assignments Table 4: Pin Assignments (Continued) 88-Pin DDR4 UDIMM Front 88-Pin DDR4 UDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 8 64 V DD ALERT_n 44 S4_c DM_n/ DBI_n, 65 A/BC_n V DD 45 S4_t A S_c 0 A V DD 03 V ss 39 SA0 75 S_t A A SA 76 V DD V DDSPD A SCL A SDA V DD V PP 78 4 A V PP 35 7 A V PP V DD V PP A A 5 88 V PP 4

5 Pin Descriptions Table 5: Pin Descriptions The pin description table below is a comprehensive list of all possible pins for DDR4 UDIMM, RDIMM, SODIMM and LRDIMM modules. All pins listed may not be supported on the module defined in this data sheet. See functional block diagram specific to this module to review all pins utilized on this module. Symbol Type Description Ax Input Address inputs: Provide the row address for ACTIVATE commands and the column address for READ/WRITE commands to select one location out of the memory array in the respective bank. (A0/AP, A/BC_n, WE_n/A4, CAS_n/A5, and RAS_n/A6 have additional functions; see individual entries in this table). The address inputs also provide the op-code during the MODE REGISTER SET command. A7 is only defined for x4 SDRAM configuration. A0/AP Input Auto precharge: A0 is sampled during READ and WRITE commands to determine whether auto precharge should be performed to the accessed bank after a READ or WRITE operation (HIGH = Auto precharge; LOW = No auto precharge). A0 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A0 LOW) or all banks (A0 HIGH). If only one bank is to be precharged, the bank is selected by the bank group and bank addresses. A/BC_n Input Burst chop: A/BC_n is sampled during READ and WRITE commands to determine if burst chop (on-the-fly) will be performed. (HIGH = No burst chop; LOW = Burst-chopped). See the Command Truth Table in DDR4 component data sheet for more information. ACT_n Input Command input: ACT_n defines the activation command being entered along with CS_n. The input into RAS_n/A6, CAS_n/A5, and WE_n/A4 will be considered as row address A6, A5, and A4. See the Command Truth Table in DDR4 component data sheet for more information. BAx Input Bank address inputs: Define to which bank an ACTIVATE, READ, WRITE, or PRE- CHARGE command is being applied. Also determines which mode register is to be accessed during a MODE REGISTER SET command. BGx Input Bank group address inputs: Define which bank group a REFRESH, ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. Also determines which mode register is to be accessed during a MODE REGISTER SET command. BG[:0] are used in the x4 and x8 configurations. x6 based SDRAMs only have BG0. C0, C, C (RDIMM/LRDIMM Only) CKx_t CKx_c Input Input 8GB (x64, DR) 88-Pin DDR4 UDIMM Pin Descriptions Chip ID: These inputs are used only when devices are stacked, that is, H, 4H, and 8H stacks for x4 and x8 configurations using though-silicon vias (TSVs). These pins are not used in the x6 configuration. Some DDR4 modules support a traditional DDP package, which use CS_n, CKE, and ODT to control the second die. For all other stack configurations, such as a 4H or 8H, it is assumed to be a single-load (master/slave)- type configuration where C0, C, and C are used as chip ID selects in conjunction with a single CS_n, CKE, and ODT. Chip ID is considered part of the command code. Clock: Differential clock inputs. All address, command, and control input signals are sampled on the crossing of the positive edge of CK_t and the negative edge of CK_c. 5

6 8GB (x64, DR) 88-Pin DDR4 UDIMM Pin Descriptions Table 5: Pin Descriptions (Continued) Symbol Type Description CKEx Input Clock enable: CKE HIGH activates, and CKE LOW deactivates, the internal clock signals, device input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is asynchronous for self refresh exit. After V REFCA has become stable during the power-on and initialization sequence, it must be maintained during all operations (including SELF REFRESH). CKE must be held HIGH throughout read and write accesses. Input buffers (excluding CK_t, CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Input buffers (excluding CKE and RESET#) are disabled during self refresh. CSx_n Input Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides external rank selection on systems with multiple ranks. CS_n is considered part of the command code. CS_n and CS3_n are not used on UDIMMs. ODTx Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR4 SDRAM. When ODT is enabled, on-die termination (R TT ) is applied only to each, S_t, S_c, DM_n//TS_t, and TS_c signal for x4 and x8 configurations (when the TS function is enabled via the mode register). For the x6 configuration, R TT is applied to each, SU_t, SU_c, SL_t, SL_c, UDM_n, and LDM_n signal. The ODT pin will be ignored if the mode registers are programmed to disable R TT. PARITY Input Parity for command and address: This function can be enabled or disabled via the mode register. When enabled in MR5, then DRAM calculates Parity with ACT_n, RAS_n/A6, CAS_n/A5, WE_n/A4, BG[:0], BA[:0], A[6:0]. Input parity should be maintained at the rising edge of the clock and at the same time with command and address with CS_n LOW. RAS_n/A6 CAS_n/A5 WE_n/A4 RESET_n SAx SCL Input Command inputs: RAS_n/A6, CAS_n/A5, and WE_n/A4 (along with CS_n) define the command and/or address being entered. Those pins have multifunction. For example, for activation with ACT_n LOW, these are addresses like A6, A5, and A4, but for a non-activation command with ACT_n HIGH, these are command pins for READ, WRITE, and other commands defined in the command truth table. CMOS Input Active LOW asynchronous reset: Reset is active when RESET_n is LOW; inactive when RESET_n is HIGH. RESET_n must be HIGH during normal operation. Input Input Serial address inputs: Used to configure the temperature sensor/spd EEPROM address range on the I C bus. Serial clock for temperature sensor/spd EEPROM: Used to synchronize communication to and from the temperature sensor/spd EEPROM on the I C bus. x, CBx I/O Data input/output and Check Bit input/output : Bidirectional data bus. represents [3:0], [7:0], and [5:0] for the x4, x8, and x6 configurations, respectively. If cyclic redundancy checksum (CRC) is enabled via the mode register, then CRC code is added at the end of the data burst. Either one or all of 0,,, or 3 is/are used for monitoring of internal V REF level during test via mode register setting MR[4] A[4] = HIGH; training times change when enabled. 6

7 8GB (x64, DR) 88-Pin DDR4 UDIMM Pin Descriptions Table 5: Pin Descriptions (Continued) Symbol Type Description DM_n// TS_t(DMU_n,DBI U_n),(DML_n/ DBIl_n) S_t S_c SU_t SU_c SL_t SL_c I/O I/O Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data. Input data is masked when DM_n is sampled LOW coincident with that input data during a write access. DM_n is sampled on both edges of S. DM is mux ed with DBI function by mode register A0, A, A setting in MR5. For x8 device, the function of DM or TS is enabled by mode register A setting in MR. is an input/output identifying whether to store/output the true or inverted data. If is LOW, the data will be stored/output after inversion inside the DDR4 SDRAM and not inverted if is HIGH. TS is only supported in x8 SDRAM configurations. TS is not valid for UDIMMs. Data strobe: Output with read data, input with write data. Edge-aligned with read data, centered-aligned with WRITE data. For x6 configurations, SL corresponds to the data on [7:0]; SU corresponds to the data on [5:8]. For the x4 and x8 configurations, S corresponds to the data on [3:0] and [7:0] respectively. DDR4 SDRAM support a differential data strobe only and do not support a singleended data strobe. ALERT_n Output Alert output: Possesses multifunctions such as CRC error flag and command and address parity error flag as output signal. If there is a CRC error, then ALERT_n goes LOW for the period time interval and returns HIGH. If there is error in command address parity check, then ALERT_n goes LOW until on-going DRAM internal recovery transaction is complete. During connectivity test mode this pin functions as an input. Using this signal or not is dependent on the system. If not connected as signal, ALERT_n pin must be connected to V DD on DIMM. EVENT_n Output Temperature event: The EVENT_n pin is asserted by the temperature sensor when critical temperature thresholds have been exceeded. This pin has no function (NF) on modules without temperature sensors. TS_t TS_c (x8 DRAM based RDIMM only) Output Termination data strobe: TS_t and TS_c are not valid for UDIMMs. When enabled via the mode register, the SDRAM enable the same R TT termination resistance on TS_t and TS_c that is applied to S_t and S_c. When the TS function is disabled via the mode register, the DM/TS_t pin provides the data mask (DM) function, and the TS_c pin is not used. The TS function must be disabled in the mode register for both the x4 and x6 configurations. The DM function is supported only in x8 and x6 configurations. DM, DBI, and TS are a shared pin and are enabled/disabled by mode register settings. For further information about TS, refer to DDR4 DRAM data sheet. V DD Supply Module Power supply:.v (typical) V PP Supply DRAM activating power supply:.5v -0.5V / +0.50V V REFCA Supply Reference voltage for control, command, and address pins. Supply Ground. V TT Supply Power supply for termination of address, command, and control, V DD /. V DDSPD Supply Power supply used to power the I C bus used for SPD. RFU Reserved for future use. No connect: No internal electrical connection is present. NF No function: Internal connection may be present but has no function. 7

8 8GB (x64, DR) 88-Pin DDR4 UDIMM Map Map Table 6: Component-to-Module Map Component Reference Number Component Module Module Pin Number Component Reference Number Component Module Module Pin Number U U U U U U U U

9 8GB (x64, DR) 88-Pin DDR4 UDIMM Map Table 6: Component-to-Module Map (Continued) Component Reference Number Component Module Module Pin Number Component Reference Number Component Module Module Pin Number U U U U U U U U

10 8GB (x64, DR) 88-Pin DDR4 UDIMM Functional Block Diagram Functional Block Diagram Figure : Functional Block Diagram CS_n CS0_n S0_t S0_c DBI0_n/DM0_n S4_t S4_c DBI4_n/DM4_n S_t S_c DBI_n/DM_n DM_n/ CS_n S_t S_c U DM_n/ CS_n S_t S_c U7 S5_t S5_c DBI5_n/DM5_n DM_n/ CS_n S_t S_c U5 DM_n/ CS_n S_t S_c U3 S_t S_c DBI_n/DM_n DM_n/ CS_n S_t S_c U DM_n/ CS_n S_t S_c U6 S6_t S6_c DBI6_n/DM6_n DM_n/ CS_n S_t S_c U6 DM_n/ CS_n S_t S_c U S3_t S3_c DBI3_n/DM3_n DM_n/ CS_n S_t S_c U3 DM_n/ CS_n S_t S_c U5 S7_t S7_c DBI7_n/DM7_n DM_n/ CS_n S_t S_c U7 DM_n/ CS_n S_t S_c U DM_n/ CS_n S_t S_c U4 DM_n/ CS_n S_t S_c U DM_n/ CS_n S_t S_c U8 DM_n/ CS_n S_t S_c U0 BA[:0] BG[:0] ACT_n A[3:0] RAS_n/A6 CAS_n/A5 WE_n/A4 CKE0 CKE ODT0 ODT RESET PARITY ALERT_n VDD 50W BA[:0]: DDR4 SDRAM BG[:0]: DDR4 SDRAM ACT_n: DDR4 SDRAM A[3:0]: DDR4 SDRAM RAS_n/A6: DDR4 SDRAM CAS_n/A5: DDR4 SDRAM WE_n/A4: DDR4 SDRAM CKE0: Rank 0 CKE: Rank ODT0: Rank 0 ODT: Rank RESET_n: DDR4 SDRAM PARITY: DDR4 SDRAM ALERT_n: DDR4 SDRAM CK0 CK0# CK CK# Rank 0: U U8 Rank : U0 U7 Rank 0 Rank SCL U9 SPD EEPROM NF A0 A A SA0 SA SA NF Clock, control, command, and address line terminations: CS_n[:0], BA[:0], BG[:0], ACT_n, A[3:0], RAS_n/A6, CAS_n/A5, WE_n/A4, PARITY, CKE[:0], ODT[:0] DDR4 SDRAM DDR4 SDRAM V TT SDA V DDSPD V DD V TT V REFCA V PP SPD EEPROM DDR4 SDRAM Control, command, and address termination DDR4 SDRAM DDR4 SDRAM DDR4 SDRAM CK CK# V DD Note:. The ball on each DDR4 component is connected to an external 40Ω ±% resistor that is tied to ground. It is used for the calibration of the component s ODT and output driver. 0

11 General Description 8GB (x64, DR) 88-Pin DDR4 UDIMM General Description High-speed DDR4 SDRAM modules use DDR4 SDRAM devices with or 4 internal memory bank groups. DDR4 SDRAM modules utilizing 4- and 8-bit-wide DDR4 SDRAM have 4 internal bank groups consisting of 4 memory banks each, providing a total of 6 banks. Sixteen-bit-wide DDR4 SDRAM has internal bank groups consisting of 4 memory banks each, providing a total of 8 banks. DDR4 SDRAM modules benefit from DDR4 SDRAM's use of an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM effectively consists of a single 8n-bit-wide, four-clock data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. DDR4 modules use two sets of differential signals: S_t, S_c to capture data and CK_t and CK_c to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. Fly-By Topology DDR4 modules use faster clock speeds than earlier DDR technologies, making signal quality more important than ever. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each DRAM is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the connector). Inherent to fly-by topology, the timing skew between the clock and S signals can be easily accounted for by using the write-leveling feature of DDR4. Serial Presence-Detect EEPROM Operation DDR4 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 5-byte JEDEC JC-4.4-compliant EEPROM that is segregated into 4, 8-byte, write protectable blocks. The SPD content is aligned with these blocks as follows. Block Range Description x000 0x07F Configuration and DRAM parameters x080 0x0FF Module parameters x00 0x3F Reserved All bytes coded as 0x x40 0xFF Manufacturing information x80 0xFF End-user programmable The first 384 bytes are programmed by Micron to comply with JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR4 SDRAM Modules." The remaining 8 bytes of storage are available for use by the customer. The EEPROM resides on a two-wire IC serial interface and is not integrated with the memory bus in any manner. It operates as a slave device in the IC bus protocol, with all operations synchronized by the serial clock. Transfer rates of up to MHz are achievable at. 3.6V. Micron implements reversible software write protection on DDR4 SDRAM-based modules. This prevents the lower 384 bytes (bytes 0 383) from being inadvertently program-

12 8GB (x64, DR) 88-Pin DDR4 UDIMM Serial Presence-Detect EEPROM Operation med or corrupted. The upper 8 bytes remain available for customer use and unprotected.

13 Electrical Specifications Table 7: Absolute Maximum Ratings 8GB (x64, DR) 88-Pin DDR4 UDIMM Electrical Specifications Stresses greater than those listed may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Symbol Parameter Min Max Units Notes V DD V DD supply voltage relative to V V D V D supply voltage relative to V V PP Voltage on VPP pin relative to Vss V V IN, V OUT Voltage on any pin relative to V Table 8: Operating Conditions Symbol Parameter Min Nom Max Units Notes V DD V DD supply voltage.4..6 V V PP DRAM Activating Power Supply V V REFCA(DC) Input reference voltage command/ address bus 0.49 V DD 0.5 V DD 0.5 V DD V 3 I VTT Termination reference current from V TT ma V TT Termination reference voltage (DC) command/address bus I I Input leakage current; Any input excluding ; 0V < V IN <.V V DD - 0mV 0.5 V DD 0.5 V DD + 0mV V µa 5 I I/O leakage; 0V<V in <V DD µa 5 I I Input leakage current; µa 5,6 I OZpd I OZpu I VREFCA Output leakage current; V OUT =V DD ; are disabled. Output leakage current; V OUT = ; and ODT are disabled; ODT is disabled with ODT input HIGH. V REFCA leakage; V REFCA = V DD / (After DRAM is initialized) 5.0 µa 5.0 µa µa 5 Notes:. V D tracks with V DD ; V D and V DD are tied together.. V PP must be greater than or equal to V DD at all times. 3. V REFCA must not be greater than 0.6 x V DD. When V DD are less than 500mV; V REF may be less than or equal to 300mV. 4. V TT termination voltages in excess of specification limit will adversely affect command and address signals' voltage margins, and reduce timing margins. 5. Multiply by the number of DRAM die on the module. 6. Tied to ground. Not connected to edge connector. 3

14 8GB (x64, DR) 88-Pin DDR4 UDIMM Electrical Specifications Table 9: Thermal Characteristics Parameter/Condition Value Units Symbol Notes Operating case temperature - Commercial 0 to +85 C T C,, 3 >85 to +95 C T C,, 3, 4 Normal operating temperature range 0 to +85 C T OPER 5,6 Extended temperature operating range (optional) >85 to 95 C T OPER 5,6 Notes:. MAX operating case temperature. T C is measured in the center of the package.. A thermal solution must be designed to ensure the DRAM device does not exceed the maximum T C during operation. 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum T C during operation. 4. If T C exceeds 85 C, the DRAM must be refreshed externally at x refresh, which is a 3.9µs interval refresh rate. 5. The refresh rate is required to double when 85 C < T OPER 95 C. 6. For additional information, refer to technical note TN-00-08: "Thermal Applications" available on Micron's web site. 4

15 8GB (x64, DR) 88-Pin DDR4 UDIMM DRAM Operating Conditions DRAM Operating Conditions Recommended AC operating conditions are given in the DDR4 component data sheets. Component specifications are available on Micron s web site. Module speed grades correlate with component speed grades, as shown below. Table 0: Module and Component Speed Grades DDR4 components may exceed the listed module speed grades; module may not be available in all listed speed grades Module Speed Grade Component Speed Grade -G4-083E -G -093E -G9-07E Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the edge connector of the module, not the DRAM. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. 5

16 8GB (x64, DR) 88-Pin DDR4 UDIMM I DD Specifications I DD Specifications Table : DDR4 I DD Specifications and Conditions 8GB (Die Revision A) Values are for the MT40A5M8 DDR4 SDRAM only and are computed from values specified in the 4Gb (5 Meg x 8) component data sheet Parameter Symbol Units One bank ACTIVATE-PRECHARGE current I DD ma One bank ACTIVATE-PRECHARGE, wordline boost, I PP current I PP ma One bank ACTIVATE-READ-PRECHARGE current I DD ma Precharge standby current I DDN ma Precharge standby ODT current I DDNT ma Precharge power-down current I DDP ma Precharge quite standby current I DDQ ma Active standby current I DD3N ma Active standby I PP current I PP3N ma Active power-down current I DD3P ma Burst read current I DD4R ma Burst read I D current I D4R ma Burst write current I DD4W ma Burst refresh current (x REF) I DD5B ma Burst refresh I PP current (x REF) I PP5B ma Self refresh current: Normal temperature range (0 85 C) I DD6N ma Self refresh current: Extended temperature range (0 95 C) I DD6E ma Self refresh current: Reduced temperature range (0 45 C) I DD6R ma Auto self refresh current (5 C) I DD6A ma Auto self refresh current (45 C) I DD6A ma Auto self refresh current (75 C) I DD6A ma Bank interleave read current I DD ma Bank interleave read I PP current I PP ma Maximum power-down current I DD ma Notes:. One module rank in the active I DD/PP, the other rank in I DDP/PP3N.. All ranks in this I DD/PP condition. 6

17 Serial Presence-Detect EEPROM For the latest SPD data, refer to Micron's SPD page: Table : Serial Presence-Detect EEPROM DC Operating Conditions Note: 8GB (x64, DR) 88-Pin DDR4 UDIMM Serial Presence-Detect EEPROM All voltages referenced to V DDSPD Parameter/Condition Symbol Min Max Units Supply voltage V DDSPD. 3.6 V Input low voltage: Logic 0; All inputs V IL 0.5 V DDSPD * 0.3 V Input high voltage: Logic ; All inputs V IH V DDSPD * 0.7 V DDSPD V Output low voltage: 3 ma sink current V DDSPD >V V OL 0.4 V Input leakage current: (SCL, SDA) V IN = V DDSPD or SPD I LI ±5 µa Output leakage current: V OUT = V DDSPD or SPD, SDA in Hi-Z I LO ±5 µa Note:. Table provided as a general reference. Please consult JEDEC JC-4.4 EE004 and TSE004 device specification for complete details. Table 3: Serial Presence-Detect EEPROM AC Operating Conditions Parameter/Condition Symbol Min Max Units Clock frequency t SCL khz Clock pulse width HIGH time t HIGH 60 ns Clock pulse width LOW time t LOW 500 ns Detect Clock Low Timeout t TIMEOUT 5 35 ms SDA rise time t R 0 ns SDA fall time t F 0 ns Data-in setup time t SU:DAT 50 ns Data-in hold time t HD:DI 0 ns Data out hold time t HD:DAT ns Start condition setup time t SU:STA 60 ns Start condition hold time t HD:STA 60 ns Stop condition setup time t SU:STO 60 ns Time the bus must be free before a new transition can start t BUF 500 ns WRITE time t W 5 ms Warm power cycle time off t POFF ms Time from power on to first command t INIT 0 ms Note:. Table provided as a general reference. Please consult JEDEC JC-4.4 EE004 and TSE004 device specification for complete details. 7

18 8GB (x64, DR) 88-Pin DDR4 UDIMM Module Dimensions Module Dimensions Figure 3: 88-Pin DDR4 UDIMM Front view (5.56) 33.0 (5.44) 3.9 (0.53) MAX 0.75 (0.03) R (8X) U U U3 U4 U5 U6 U7 U (.36) 3.0 (.4).50 (0.098) D (X) 4.8 (0.89) U9 6. (0.63) 9.5 (0.374).0 (0.087) 3.35 (0.3) (X) PIN 7.5 (.84) 0.85 (0.033) 0.60 (0.036) 0.75 (0.030) R PIN (0.059).30 (0.05) 6.65 (4.99) Back view.5 (0.049) x 45 (X) U0 U U U3 U4 U5 U6 U7 3.0 (0.8) (4X) 4.6 (0.57) 8.0 (0.35) 3.5 (0.4) PIN (0.90) 0. (0.4) 5.95 (0.34).95 (0.9) 5.5 (.0) 0. (0.4) 8.9 (.4) PIN (0.097) 56.0 (.) 64.6 (.54) Notes:. All dimensions are in millimeters (inches); MAX/MIN or typical () where noted.. The dimensional diagram is for reference only S. Federal Way, P.O. Box 6, Boise, ID , Tel: Customer Comment Line: Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 8