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Transcription

1 Memory Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr (479)

2 Memory Arrays Memory Arrays Random Access Memory Serial Access Memory Content Addressable Memory (CAM) Read/Write Memory (RAM) (Volatile) Read Only Memory (ROM) (Nonvolatile) Shift Registers Queues Static RAM (SRAM) Dynamic RAM (DRAM) Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) First In First Out (FIFO) Last In First Out (LIFO) Mask ROM Programmable ROM (PROM) Erasable Programmable ROM (EPROM) Electrically Erasable Programmable ROM (EEPROM) Flash ROM 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 2

3 Array Architecture 2 n words of 2 m bits each If n >> m, fold by 2 k into fewer rows of more columns Good regularity easy to design Very high density if good cells are used 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 3

4 12T SRAM Cell Basic building block: SRAM Cell Holds one bit of information, like a latch Must be read and written 12-transistor (12T) SRAM cell Use a simple latch connected to bitline 46 x 75 l unit cell write bit write_b read read_b 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 4

5 6T SRAM Cell Cell size accounts for most of array size Reduce cell size at expense of complexity 6T SRAM Cell Used in most commercial chips Data stored in cross-coupled inverters Read: Precharge bit, bit_b Raise wordline Write: Drive data onto bit, bit_b Raise wordline word bit bit_b 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 5

6 SRAM Read Precharge both bitlines high word bit bit_b Then turn on wordline One of the two bitlines will be pulled down N2 A P1 N1 P2 N3 A_b N4 Ex: A = 0, A_b = 1 bit discharges, bit_b stays high But A bumps up slightly 1.5 A_b bit_b Read stability A must not flip N1 >> N word bit A time (ps) 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 6

7 SRAM Write Drive one bitline high, the other low Then turn on wordline Bitlines overpower cell with new value Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 Force A_b low, then A rises high Writability Must overpower feedback inverter N2 >> P bit_b word A_b bit N2 A A P1 N1 P2 N3 A_b bit_b N4 0.5 word time (ps) 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 7

8 SRAM Sizing High bitlines must not overpower inverters during reads But low bitlines must write new value into cell word bit med weak bit_b med A strong A_b 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 8

9 SRAM Layout Cell size is critical: 26 x 45 l (even smaller in industry) Tile cells sharing V DD, GND, bitline contacts GND BIT BIT_B GND VDD WORD Cell boundary 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 9

10 Commercial SRAMs Five generations of Intel SRAM cell micrographs Steady scaling of cell area => Cheaper storage 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 10

11 Decoder n:2 n decoder consists of 2 n n-input AND gates One needed for each row of memory Build AND from NAND or NOR gates A1 A0 Decoders must be pitch-matched to SRAM cell Requires very skinny gates word0 word1 word2 word3 A3 A3 A2 A2 A1 A1 A0 A0 VDD word GND NAND gate buffer inverter 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 11

12 Bitline Conditioning Pre-charge bitlines high before reads bit bit_b Equalize bitlines to minimize voltage difference when using sense amplifiers bit bit_b 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 12

13 Sense Amplifiers Bitlines have many cells attached Ex: 32-kbit SRAM has 128 rows x 256 cols 128 cells on each bitline t pd (C/I) DV Even with shared diffusion contacts, 64C of diffusion capacitance (big C) Discharged slowly through small transistors (small I) Sense amplifiers are triggered on small voltage swing (reduce DV) 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 13

14 Twisted Bitlines Sense amplifiers also amplify noise Coupling noise is severe in modern processes Try to couple equally onto bit and bit_b Done by twisting bitlines b0 b0_b b1 b1_b b2 b2_b b3 b3_b 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 14

15 Column Multiplexing Recall that array may be folded for good aspect ratio Ex: 2 kword x 16 folded into 256 rows x 128 columns Must select 16 output bits from the 128 columns Requires 16 8:1 column multiplexers 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 15

16 Tree Decoder Mux Column mux can use pass transistors Use nmos only, precharge outputs One design is to use k series transistors for 2 k :1 mux No external decoder logic needed A0 A0 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 A1 A1 A2 A2 Y to sense amps and write circuits Y 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 16

17 Large SRAMs Large SRAMs are split into subarrays for speed Ex: UltraSparc 512KB cache KB subarrays Each have 16 8KB banks 256 rows x 256 cols / bank 60% subarray area efficiency Also space for tags & control [Shin05] 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 17

18 DRAM Uses capacitor to store data C is charged => Logic 1 C is discharged => Logic 0 Uses a single access transistor Bit line precharged to VDD/2 Needs to be regularly refreshed Data can be kept for only ms Charge is lost because of leakage Copyright 2011 Pearson Education, Inc. Publishing as Pearson Addison-Wesley

19 DRAM Cell 1T1C Structure Copyright 2011 Pearson Education, Inc. Publishing as Pearson Addison-Wesley

20 DRAM Array Much denser (>10x) than SRAM, but slower Copyright 2011 Pearson Education, Inc. Publishing as Pearson Addison-Wesley

21 Read-Only Memories Read-Only Memories are nonvolatile Retain their contents when power is removed Mask-programmed ROMs use one transistor per bit Presence or absence determines 1 or 0 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 21

22 ROM Example 4-word x 6-bit ROM Represented with dot diagram Dots indicate 1 s in ROM A1 A0 weak pseudo-nmos pullups Word 0: Word 1: Word 2: Word 3: :4 DEC ROM Array Y5 Y4 Y3 Y2 Y1 Y0 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 22

23 ROM Array Layout Unit cell is 12 x 8 l (about 1/10 size of SRAM) Unit Cell 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 23

24 Complete ROM Layout Address Invertors Bitline PMOS Decoder ROM Array Output Buffer 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 24

25 PROMs and EPROMs Programmable ROMs Build array with transistors at every site Burn out fuses to disable unwanted transistors Electrically Programmable ROMs Use floating gate to turn off unwanted transistors EPROM, EEPROM, Flash Source Gate Drain Polysilicon Floating Gate Thin Gate Oxide (SiO 2) n+ n+ p bulk Si 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 25

26 Flash Programming Charge on floating gate determines V t Logic 1: negative V t Logic 0: positive V t Cells erased to 1 by applying a high body voltage so that electrons tunnel off floating gate into substrate Programmed to 0 by applying high gate voltage 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 26

27 NAND Flash High density, low cost / bit Programmed one page at a time Erased one block at a time Example: 4096-bit pages 16 pages / 8 KB block Many blocks / memory 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 27

28 64 Gb NAND Flash 64K cells / page 4 bits / cell (multiple V t ) 64 cells / string 256 pages / block 2K blocks / plane 2 planes [Trinh09] 10/31/2017 CSCE/ELEG 4914: Advnaced Digital Design 28