LOW- POWER ANALYSIS OF VARIOUS 1-BIT SRAM CELLS USING SPICE

Transcription

1 LOW- POWER ANALYSIS OF VARIOUS 1-BIT SRAM CELLS USING SPICE 1 Sushil Kumar Gupta Department of Electronics and Communication Engineering Madan Mohan Malaviya Engineering College Gorakhpur, India Abstract The need for low-power memory design is becoming a major issue in high-performance digital systems such as microprocessors, Digital Signal Processors (DSPs) and other applications. This paper discusses 7T, 6T, 5T & 4T SRAM configurations for the same. Six transistor (6T) SRAM Cells are the main choice for today s cache applications. The static noise margin (SNM) of 6T SRAM cell is highest in all memory, so the stability is highest in this cell. The circuit is characterised by using the 32nm technology. Delay of the 7T cell is 0.5ns and leakage power dissipation in standby mode is watts. Due to reduced threshold voltage in coming technologies, leakage power is increasing fast. The whole thesis circuit verification is done on the Tanner tool, Schematic of the SRAM cell is designed on the S-Edit and net list simulation done by using T-spice and waveforms are analyzed through the W-edit. An asymmetric configuration has been implemented to reduce this leakage power. 6T SRAM cell is the best asymmetric configuration used as caches. Keywords Low Power, 32nm Process Technology, 7T, 6T, 5T and 4T SRAM Introduction Excessive power dissipation increases temperature and with every 10 o C increase in operating temperature, approximately doubles a component s failure rate. So, the low power design is a growing class of personal computing devices, such as portable electronics and communication devices. These devices and systems require high speed, complex functionalities and real time processing capabilities. Due to these problems, circuit designers are realizing the importance of limiting power consumption at all levels of the design. Scaling of CMOS devices has provided remarkable improvement in performance of electronic circuits in the past few years. They can work at a much reduced threshold as compared to before CMOS threshold voltages. But this scaling causes leakage in the circuit. Leakage power consumption is another concern with SRAMs. Conventional 6T SRAM are the main choice for today s cache applications. Next, a simple 5T,4T SRAM are presented. Further, an intermediate bit line precharge voltage combined with a different 5T cell sizing allows correct write operation without requiring any additional cell nodes. The 5T cell has only one access transistor M5 (NMOS) and a single bit line BL. Next 4T SRAM cell 2 R.K. Chauhan Department of Electronics and Communication Engineering Madan Mohan Malaviya Engineering College Gorakhpur, India configuration reduces the SRAM cell size by approximately one third. Although conventional 6T SRAMs is easily embedded in logic LSIs owing to its compatibility with the CMOS logic process, they are not economical to be dissipation in the memories. Name of that configuration is asymmetric configuration. Since the MOSFET sub-threshold leakage current increases exponentially with a reduced threshold voltage, leakage power dissipation has grown to be a significant fraction of overall chip power dissipation in modern deep subnanometer (130nm) processes included in practical systems due to the large cell chip area. The loadless design of the 4T SRAMs requires special process to reduce the threshold voltage of PMOS in order to increase the supply current. In this paper, a special configuration is used to lower the leakage power that is responsible for the power. One can reduce leakage by using higher V TH transistors, but unfortunately using an all high-v TH transistor cell degrade performance by an unacceptable margin. Asymmetric SRAM reduce leakage while maintaining high performance based on the following approach: select a preferred state and weaken only those transistors necessary to drastically reduce leakage when the cell is in that state. Standby Mode If the word line is not asserted, the access (Pass) transistors will dis-connect the cell from the bit lines. The two cross coupled inverters formed the two inverter connected back to back reinforce each other as long as they are disconnected from the outside world. And they will retain the data which they have already stored in the memory cell. Read Mode Assume that the content of the memory is a 1, stored at node Q. The read cycle is started by precharging both the bit lines to a logical 1, then asserting the word line signal with the high voltage pulse enabling both the access transistors. The second step occurs when the values stored in Q and QB are transferred to the bit lines, one of the bit line will discharge through the driver transistor and the other bit line will be pulled up through the load transistors toward VDD, a logical 1. If the content of 697

2 the memory was a 0, the opposite would happen if the memory cell was stored the logic 1. Write Mode The start of a write cycle begins by applying the value to be written to the bit lines. If we wish to write a 0, we would apply a 0 to the bit line, i.e. setting BL to 0 and BLB to 1. This is similar to applying a set pulse to a SR-latch, which causes the flip flop to change state. 1 is written by inverting the values of the bit lines. Word Lines is then asserted and the value that is to be stored is latched in. Note that the reason this works is that the bit line inputdrivers are designed to be much stronger than the relatively weak transistors in the cell itself, so that they can easily override the previous state of the cross-coupled 2 inverters. Careful sizing of the transistors in a SRAM cell is needed to ensure proper operation. In this thesis a proposed SRAM cell, includes one more extra transistor in the pull down path of both the driver transistor. This extra transistor will break the path between GND and the driver transistor during the write operation which results out the decrease in the overall capacitance and hence the dynamic power. The proposed SRAM cell is designed and implemented with using 130 nm CMOS technology. Finally the results are compared with Conventional 6T SRAM cell which is also being characterized in this paper with the same technology. Fig.2 Schematic of 7T SRAM Cell Simulated Schematics Using Tanner Tool Fig.3 Schematic of 5T SRAM Cell Fig.1 Schematic of 7T SRAM Cell Fig.4 Schematic of 4T SRAM Cell 698

3 Waveforms of Short Circuit Power Dissipation Power Dissipation of All Symmetric Cells 7T SRAM cell shows the overall least power dissipation among all (Table 1). If area of chip is to be kept small at the cost of power dissipation, then 6T 5T and 4T SRAM are next choice. Main memory communicates with the processor through cache memory. Frequently utilized data are stored in cache memory. Most of the time, cache memory is in read/write mode. Therefore it is required that cell configuration used in the cache memory should have small chip area, small delay and very low power dissipation Fig.5 Read/Write Waveforms of 7T SRAM Cell Single Cell Analysis After the text edit has been completed, the paper is ready for the template. Duplicate the template file by using the Save As command, and use the naming convention prescribed by your conference for the name of your paper. In this newly created file, highlight all of the contents and import your prepared text file. You are now ready to style your paper; use the scroll down window on the left of the MS Word Formatting toolbar. Operat ion Power dissipation (watts) in symmetric 7T 6T 5T 4T Standby Writing Reading Fig.6 Read/Write, Power Dissipation Waveforms of 6T SRAM Cell Results and Comparative Analysis All memory are simulated using T-SPICE 7.1v. In this section, comparison based results are presented in following tables. These results have been obtained from simulation of 7T, 6T, 5T & 4T memory in symmetric and asymmetric configurations. Table1. Power dissipation (watts) in symmetric In comparison of symmetric and asymmetric configurations of SRAM, 7T and 6T show significant reduction in the standby leakage. So, we conclude that 7T asymmetric SRAM cell is the best configuration for fast cache memories. Along with power dissipation, delay is the second most important performance factor to the system on chip design. Next this factor has been given with the comparison of SRAM. Delay in Symmetric Cells 7T, 6T, 5T and 4T SRAM are faster than DRAM. For cache memories, low power dissipation and high speed are two main factors (shown in Table 3). Though, we can compromise on speed for reduced power dissipation in devices like portable battery operated electronics things, e.g., Laptops, cellphones, etc. 7T and 6T SRAM are best for cache memories. But the stability of data is more in 6T SRAM cell. 699

4 Delay in Symmetric Cells In Asymmetric cell Configurations, 6T SRAM cell is fastest and has small access delay. Although 4T ASRAM cell shows least delay in Table 4, this cell has large power dissipation in all operations. Therefore 6T cell is suitable in high speed caches. It has been concluded from both configurations (symmetric and asymmetric) that 7T ASRAM cell has least power dissipation and delay among all. So, 7T ASRAM cell is best among all to be used in cache memories. Power dissipation (watts) of asymmetric Operatio n 7T 6T 5T 4T Standby Writing Reading Table 2. Power dissipation (watts) of asymmetric Operation 7T 6T 5T 4T Writing 0.5ns 0.8 ns 3 ns 14 ns Reading 1.5ns 25 ns 4 ns 80 ns Table 3. Delay in symmetric Operation 7T 6T 5T 4T Writing 0.5ns 0.8 ns 3 ns 14 ns Reading 1.5ns 25 ns 4 ns 80 ns Table 4. Delay in asymmetric Conclusion Simulation of memory has been performed in T- SPICE (7.1v). The leakage power is minimum in 7T SRAM cell. Second performance factor is delay. Delay in write operation is least in 7T SRAM cell. Results obtained from simulation of all asymmetric memory suggest that 7T ASRAM cell shows overall least power dissipation. 7T SRAM cell shows least power dissipation in all the three operations, e.g., standby, write and read operation. In asymmetric configuration, leakage power is reduced to. Delay in write operation is least in 7T SRAM cell, i.e. 0.7 ns. However read operation delay is greater than write operation delay. Read operation delay of 6T ASRAM cell is 4 ns. Comparative analysis of SRAMs in symmetric and asymmetric configuration indicates that 7T SRAM cell and 7T ASRAM cell are best in their categories. Further, 7T ASRAM cell, i.e. asymmetric configuration is more suitable as compare to symmetric configuration of 7T SRAM cell. Acknowledgement The authors wish to thank Prof. B. S. Rai, Rohit Sharma, Mr. Anand Pandey for their help and collaboration. References [1] Jawar Singh, Dhiraj K.Pradhan, A single ended 6T SRAM cell design for ultra low voltage applications, IEICE Electronic Express, 2008, pp [2] Rajshekhar Keerthi,Henry Chen, Stability and static noise margin analysis of low power SRAM IEEE International Instrumentation & Measurement Technology Conference, Victoria Canada, May 2008,pp [3] A.P.Chandrakasan, S. Sheng, and R. W. Brod ersen, Low-power CMOS digital design. IEEE J. Solid- State Circ., vol. 27, no. 4, pp , Apr [4] J.Rabaey, Digital Integrated Circuits, A Design Perspective, Prentice Hall, Upper Saddle River,NJ, [5] Sapna Singh, Neha Arora, Meenakshi Suthar and Neha Gupta Performance Evaluation of Different SRAM Cell Structures at Different Technologies February2012 [6] Sandeep Dhariwal, Sushma, Vipin Gupta, Ritu Vijay and Vijay Lamba A Comparative Study & Performance Analysis of SRAM Cells with Symmetric & Asymmetric Configuration Journal of Communication and Computer 8 (2011) [7] Kang, Sung-Mo, Leblebici and Yusuf (1999), CMOS digital integrated circuits analysis and design, McGraw-Hill International Editions, Boston, 2nd Edition. [8] C-T. Chu, X. Zhang, L. He and T. Jing, Temperature aware microprocessor floorplanning considering application dependent power load, in Proc. of ICCAD, 2007, pp [9] Narender Hachette and Nagarajan Ranganathan, "LECTOR: A technique for leakage reduction in CMOS circuits," IEEE Trans., on VLSI Systems, vol. 12, No.2, Feb [10] Chang, L. Montoye, R.K. Nakamura, Y.Batson, K.A.Eickemeyer, R.J.Dennard, R.H. Haensch, W.Jamsek, D, An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches, Solid-State Circuits, IEEE Journal vol. 43, April 2008, Issue 4, p [11] Zhiyu Liu, Volkan Kursun, Characterization of a novel nine transistor SRAM cell, IEEE Transactions on Very Large Scale Integration Systems,vol.46, Issue 4,April 2008.pp [12] Koichi Takeda, A read static noise margin free SRAM cell for low Vdd and high speed applications, Solid-State Circuits, IEEE Journal vol. 41, Jan.2006, Issue 1, pp [13] Hiroki Noguchi, Which is the best dual port SRAM in 45nm process technology? 8T, 10T single end and 700

5 10T differential Renesas Technology corporation, [14] Rajshekhar Keerthi,Henry Chen, Stability and static noise margin analysis of low power SRAM IEEE International Instrumentation & Measurement Technology Conference, Victoria Canada, May 2008,pp [15] Simaran Kaur, Ashwani Kumar Analysis of Low Power SRAM Memory Cell using Tanner Tool IJECT Vol. 3, Issue 1, Jan. - March 2012 [16] Stevo Bailey, Kevin Linger, Roger Lorenzo, John Thomson A Low-Power 45nm 1Mb SRAM ECE4332-Fall2011 University of Virginia AUTHORS 1. Sushil Kumar Gupta has completed his B.Tech from Maharana Pratap Engineering College,Kanpur(U.P.) in 2008 with Electronics and Communication stream. Currently, he is pursuing M.Tech from Madan Mohan Malaviya Engineering College, Gorakhpur with Digital Systems stream. His areas of interest are Digital Electronics, VLSI Design, Signals and Systems, Control System. 2. Dr. R. K. Chauhan was born in Dehradoon, India in He received the B.Tech degree in Electronics & Communication Engineering, from G.B.P.U.A.T - Pantnagar, in 1989 and M.E. in Control & Instrumentation, from MNNIT-Allahabad in 1993 and Ph.D in Electronics Engineering, from IT-BHU, Varanasi, INDIA in He joined the department of ECE, Madan Mohan Malviya Engineering College, Gorakhpur, India as a lecturer, in 1993, as an Assistant Professor since 2002 and thereafter as an Associate Professor since Jan, 2006 to till date in the same institute. He also worked as a Professor in Department of ECE, Faculty of Technology, Addis Ababa University, Ethiopia between 2003 to He is reviewer of Microelectronics Journal, CSP etc. His research interests include device modeling and simulation of MOS, CMOS and HBT based circuits. He was selected as one of top 100 Engineers of 2010 by International Biographical Centre, Cambridge, England. 701