VCC CS SO WP GND HOLD SCK SI VCC HOLD CS SO NC NC SCK SI WP GND

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1 Features Serial Peripheral Interface (SPI) Compatible Supports SPI Modes (,) and 3 (,) Low-voltage and Standard-voltage Operation. (V CC = 4.V to.v). (V CC =.V to.v).8 (V CC =.8V to 3.6V) 3. MHz Clock Rate (V) 3-byte Page Mode Block Write Protection Protect /4, /, or Entire Array Write Protect (WP) Pin and Write Disable Itructio for both Hardware and Software Data Protection Self-timed Write Cycle ( ms Typical) High-reliability Endurance: One Million Write Cycles Data Retention: Years Automotive Grade and Extended Temperature Devices Available 8-pin PDIP, 8-lead JEDEC IC, and 4-lead and -lead TSP Packages Description The AT8/6/3/64 provides 89/6384/368/636 bits of serial electrically-erasable programmable read only memory (EEPROM) organized as 4/48/496/89 words of 8 bits each. The device is optimized for use in many industrial and commercial applicatio where low-power and low-voltage operation are essential. The AT8/6/3/64 is available in space saving 8-pin PDIP, 8- lead JEDEC IC, and 4-lead and -lead TSP packages. Pin Configuration Pin Name GND VCC WP HOLD DC Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Write Protect Suspends Serial Input No Connect Don t Connect WP GND WP GND 8-pin PDIP lead TSP VCC HOLD VCC HOLD WP GND WP GND DC 8-lead IC lead TSP* (continued) VCC HOLD VCC HOLD HOLD DC SPI Serial EEPROMs 8K (4 x 8) 6K (48 x 8) 3K (496 x 8) 64K (89 x 8) AT8 AT6 AT3 AT64 Note: *Pi 3, 4 and, 8 are internally connected for 4-lead TSP socket compatibility. Rev. 6F 8/

2 Absolute Maximum Ratings* The AT8/6/3/64 is enabled through the Chip Select pin () and accessed via a 3- wire interface coisting of Serial Data Input (), Serial Data Output (), and Serial Clock (). All programming cycles are completely self-timed, and no separate ERASE cycle is required before WRITE. BLOCK WRITE protection is enabled by programming the status register with one of four blocks of write protection. Separate program enable and program disable itructio are provided for additional data protection. Hardware data protection is provided via the WP pin to protect agait inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Operating Temperature... - C to + C Storage Temperature C to + C Voltage on Any Pin with Respect to Ground...-.V to +.V Maximum Operating Voltage... 6.V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. DC Output Current.... ma Block Diagram AT8/6/3/64 6F 8/

3 AT8/6/3/64 Pin Capacitance () Applicable over recommended operating range from T A = C, f =. MHz, V CC = +.V (unless otherwise noted). Symbol Test Conditio Max Units Conditio C OUT Output Capacitance () 8 pf V OUT = V C IN Input Capacitance(,,, WP, HOLD) 6 pf V IN = V Note:. This parameter is characterized and is not % tested. DC Characteristics () Applicable over recommended operating range from: T AI = -4 C to +8 C, V CC = +.8V to +.V, T AC = C to + C, V CC = +.8V to +.V (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units V CC Supply Voltage V V CC Supply Voltage.. V V CC3 Supply Voltage 4.. V I CC Supply Current V CC =.V at MHz, = Open, Read 3. ma I CC Supply Current V CC =.V at MHz, = Open, Read, Write Note:. V IL min and V IH max are reference only and are not tested.. ma I SB Standby Current V CC =.8V, = V CC.. µa I SB Standby Current V CC =.V, = V CC.. µa I SB3 Standby Current V CC =.V, = V CC.. µa I IL Input Leakage V IN = V to V CC -3. µa I OL Output Leakage V IN = V to V CC, T AC = C to C µa V IL () Input Low-voltage -.6 V CC x.3 V V IH () Input High-voltage V CC x. V CC +. V V OL Output Low-voltage 4.V V CC.V I OL = 3. ma.4 V V OH Output High-voltage I OH = -.6 ma V CC -.8 V V OL Output Low-voltage.8V V CC 3.6V I OL =. ma. V V OH Output High-voltage I OH = - µa V CC -. V 6F 8/ 3

4 AC Characteristics Applicable over recommended operating range from T A = -4 C to +8 C, V CC = As Specified, CL = TTL Gate and pf (unless otherwise noted). Symbol Parameter Voltage Min Max Units f Clock Frequency MHz t RI Input Rise Time µs t FI Input Fall Time µs t WH High Time t WL Low Time t High Time t S Setup Time t H Hold Time t SU Data In Setup Time t H Data In Hold Time t HD Hold Setup Time t CD Hold Hold Time t V Output Valid t HO Output Hold Time AT8/6/3/64 6F 8/

5 AT8/6/3/64 AC Characteristics (Continued) Applicable over recommended operating range from T A = -4 C to +8 C, V CC = As Specified, CL = TTL Gate and pf (unless otherwise noted). Symbol Parameter Voltage Min Max Units t LZ Hold to Output Low Z t HZ Hold to Output High Z t DIS Output Disable Time t WC Write Cycle Time Endurance ().V, C, Page Mode M Write Cycles Note:. This parameter is characterized and is not % tested. ms 6F 8/

6 Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin () is always an input, the AT8/6/3/64 always operates as a slave. TRANSMITTER/RECEIVER: The AT8/6/3/64 has separate pi designated for data tramission () and reception (). MSB: The Most Significant Bit (MSB) is the first bit tramitted and received. SERIAL OP-CODE: After the device is selected with going low, the first byte will be received. This byte contai the op-code that defines the operatio to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT8/6/3/64, and the serial output pin () will remain in a high impedance state until the falling edge of is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT8/6/3/64 is selected when the pin is low. When the device is not selected, data will not be accepted via the pin, and the serial output pin () will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the pin to select the AT8/6/3/64. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the pin is low. To resume serial communication, the HOLD pin is brought high while the pin is low ( may still toggle during HOLD). Inputs to the pin will be ignored while the pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operatio when held high. When the WP pin is brought low and WPEN bit is, all write operatio to the status register are inhibited. WP going low while is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is "". This will allow the user to itall the AT8/6/3/64 in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functio are enabled when the WPEN bit is set to. 6 AT8/6/3/64 6F 8/

7 AT8/6/3/64 SPI Serial Interface 6F 8/

8 Functional Description The AT8/6/3/64 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 68 and 68HC series of microcontrollers. The AT8/6/3/64 utilizes an 8-bit itruction register. The list of itructio and their operation codes are contained in Table. All itructio, addresses, and data are traferred with the MSB first and start with a high-to-low traition. Table. Itruction Set for the AT8/6/3/64 Itruction Name Itruction Format Operation WREN X Set Write Enable Latch WRDI X Reset Write Enable Latch RDSR X Read Status Register WRSR X Write Status Register READ X Read Data from Memory Array WRITE X Write Data to Memory Array WRITE ENABLE (WREN): The device will power-up in the write disable state when V CC is applied. All programming itructio must therefore be preceded by a Write Enable itruction. WRITE DISABLE (WRDI): To protect the device agait inadvertent writes, the Write Disable itruction disables all programming modes. The WRDI itruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register itruction provides access to the status register. The READY/BUSY and Write Enable status of the device can be determined by the RDSR itruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR itruction. Table. Status Register Format Bit Bit 6 Bit Bit 4 Bit 3 Bit Bit Bit WPEN X X X BP BP WEN RDY Table 3. Read Status Register Bit Definition Bit Bit (RDY) Bit (WEN) Definition Bit (BP) See Table 3. Bit 3 (BP) See Table 3. Bit = (RDY) indicates the device is READY. Bit = indicates the write cycle is in progress. Bit = indicates the device is not WRITE ENABLED. Bit = indicates the device is WRITE ENABLED. Bits 4-6 are s when device is not in an internal write cycle. Bit (WPEN) See Table. Bits - are s during an internal write cycle. 8 AT8/6/3/64 6F 8/

9 AT8/6/3/64 WRITE STATUS REGISTER (WRSR): The WRSR itruction allows the user to select one of four levels of protection. The AT8/6/3/64 is divided into four array segments. One quarter (/4), one half (/), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be READ only. The block write protection levels and corresponding status register control bits are shown in Table 4. The three bits, BP, BP, and WPEN are nonvolatile cells that have the same properties and functio as the regular memory cells (e.g. WREN, t WC, RDSR). Table 4. Block Write Protect Bits Level Status Register Bits Array Addresses Protected BP BP AT8 AT6 AT3 AT64 None None None None (/4) (/) 3(All) 3-3FF -3FF 6 -FF 4 -FF C -FFF 8 -FFF 8 -FFF -FFF The WRSR itruction also allows the user to enable or disable the write protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is. When the device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the blockprotected sectio in the memory array are disabled. Writes are only allowed to sectio of the memory which are not block-protected. NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to, as long as the WP pin is held low. Table. WPEN Operation WPEN WP WEN -3FF Protected Blocks -FF -FFF Unprotected Blocks -FFF Status Register X Protected Protected Protected X Protected Writable Writable Low Protected Protected Protected Low Protected Writable Protected X High Protected Protected Protected X High Protected Writable Writable 6F 8/ 9

10 READ SEQUEE (READ): Reading the AT8/6/3/64 via the (Serial Output) pin requires the following sequence. After the line is pulled low to select a device, the READ op-code is tramitted via the line followed by the byte address to be read (A - A, Refer to Table 6). Upon completion, any data on the line will be ignored. The data (D - D) at the specified address is then shifted out onto the line. If only one byte is to be read, the line should be driven high after the data comes out. The READ sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous READ cycle. WRITE SEQUEE (WRITE): In order to program the AT8/6/3/64, two separate itructio must be executed. First, the device must be write enabled via the Write Enable (WREN) Itruction. Then a Write (WRITE) Itruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the Block Write Protection Level. During an internal write cycle, all commands will be ignored except the RDSR itruction. A Write Itruction requires the following sequence. After the line is pulled low to select the device, the WRITE op-code is tramitted via the line followed by the byte address (A - A) and the data (D - D) to be programmed (Refer to Table 6). Programming will start after the pin is brought high. (The LOW-to-High traition of the pin must occur during the low-time immediately after clocking in the D (LSB) data bit. The READY/BUSY status of the device can be determined by initiating a READ STATUS REGISTER (RDSR) Itruction. If Bit =, the WRITE cycle is still in progress. If Bit =, the WRITE cycle has ended. Only the READ STATUS REGISTER itruction is enabled during the WRITE programming cycle. The AT8/6/3/64 is capable of a 3-byte PAGE WRITE operation. After each byte of data is received, the five low order address bits are internally incremented by one; the high order bits of the address will remain cotant. If more than 3 bytes of data are tramitted, the address counter will roll over and the previously written data will be overwritten. The AT8/6/3/64 is automatically returned to the write disable state at the completion of a WRITE cycle. NOTE: If the device is not Write enabled (WREN), the device will ignore the Write itruction and will return to the standby state, when is brought high. A new falling edge is required to re-initiate the serial communication. Table 6. Address Key Address AT8 AT6 AT3 AT64 A N A 9 - A A - A A - A A - A Don t Care Bits A - A A - A A - A A - A 3 AT8/6/3/64 6F 8/

11 AT8/6/3/64 Timing Diagrams Synchronous Data Timing (for Mode ) t V IH V IL ts t H V IH t WH t WL V IL t SU t H V IH V IL VALID IN t V t HO t DIS V OH HI-Z HI-Z V OL WREN Timing WRDI Timing 6F 8/

12 RDSR Timing INSTRUCTION DATA OUT HIGH IMPEDAE MSB WRSR Timing INSTRUCTION 6 DATA IN 4 3 HIGH IMPEDAE READ Timing INSTRUCTION BYTE ADDRESS HIGH IMPEDAE MSB 6 DATA OUT 4 3 AT8/6/3/64 6F 8/

13 AT8/6/3/64 WRITE Timing INSTRUCTION BYTE ADDRESS DATA IN HIGH IMPEDAE HOLD Timing t CD t CD t HD HO LD t HD t HZ t LZ 6F 8/ 3

14 AT8 Ordering Information t WC (max) (ms) I CC (max) (µa) I SB (max) (µa). 3 AT8-PC AT8N-SC AT8T-TC AT8T-TC 3. AT8-PC-. AT8N-SC-. AT8T-TC-. AT8T-TC-. 3. AT8-PC.8 AT8N-SC-.8 AT8T-TC-.8 AT8T-TC AT8-PI AT8N- AT8T-TI AT8T-TI 3. AT8-PI-. AT8N--. AT8T-TI-. AT8T-TI-. 3. AT8-PI-.8 AT8N--.8 AT8T-TI-.8 AT8T-TI-.8 f MAX (khz) Ordering Code Package Operation Range ( C to C) ( C to C) ( C to C) (-4 C to 8 C) (-4 C to 8 C) (-4 C to 8 C) Package Type 8-pin,.3" Wide, Plastic Dual Inline Package (PDIP) 8-lead,." Wide, Plastic Gull Wing Small Outline (JEDEC IC) 4-lead,." Wide, Thin Shrink Small Outline Package (TSP) -lead,." Wide, Thin Shrink Small Outline Package (TSP) Optio Blank Standard Device (4.V to.v) -. Low Voltage (.V to.v) -.8 Low Voltage (.8V to 3.6V) 4 AT8/6/3/64 6F 8/

15 AT8/6/3/64 AT6 Ordering Information t WC (max) (ms) I CC (max) (µa) I SB (max) (µa). 3 AT6-PC AT6N-SC AT6T-TC AT6T-TC 3. AT6-PC-. AT6N-SC-. AT6T-TC-. AT6T-TC-. 3. AT6-PC-.8 AT6N-SC-.8 AT6T-TC-.8 AT6T-TC AT6-PI AT6N- AT6T-TI AT6T-TI 3. AT6-PI-. AT6N--. AT6T-TI-. AT6T-TI-. 3. AT6-PI-.8 AT6N--.8 AT6T-TI-.8 AT6T-TI-.8 f MAX (khz) Ordering Code Package Operation Range ( C to C) ( C to C) ( C to C) (-4 C to 8 C) (-4 C to 8 C) (-4 C to 8 C) Package Type 8-pin,.3" Wide, Plastic Dual Inline Package (PDIP) 8-lead,." Wide, Plastic Gull Wing Small Outline (JEDEC IC) 4-lead,." Wide, Thin Shrink Small Outline Package (TSP) -lead,." Wide, Thin Shrink Small Outline Package (TSP) Optio Blank Standard Device (4.V to.v) -. Low Voltage (.V to.v) -.8 Low Voltage (.8V to 3.6V) 6F 8/

16 AT3 Ordering Information t WC (max) (ms) I CC (max) (µa) I SB (max) (µa). 3 AT3-PC AT3N-SC AT3-TC AT3-TC 3. AT3-PC-. AT3N-SC-. AT3-TC-. AT3-TC-.. 3 AT3-PI AT3N- AT3-TI AT3-TI 3. AT3-PI-. AT3N--. AT3-TI-. AT3-TI-. f MAX (khz) Ordering Code Package Operation Range 8S ( C to C) ( C to C) (-4 C to 8 C) (-4 C to 8 C) Package Type 8-pin,.3" Wide, Plastic Dual Inline Package (PDIP) 8-lead,." Wide, Plastic Gull Wing Small Outline (JEDEC IC) 4-lead,." Wide, Thin Shrink Small Outline Package (TSP) -lead,." Wide, Thin Shrink Small Outline Package (TSP) Optio Blank Standard Device (4.V to.v) -. Low Voltage (.V to.v) 6 AT8/6/3/64 6F 8/

17 AT8/6/3/64 AT64 Ordering Information t WC (max) (ms) I CC (max) (µa) I SB (max) (µa). 3 AT64-PC AT64N-SC AT64T-TC AT64T-TC 3. AT64-PC-. AT64N-SC-. AT64T-TC-. AT64T-TC-. 3. AT64-PC-.8 AT64N-SC-.8 AT64T-TC-.8 AT64T-TC AT64-PI AT64N- AT64T-TI AT64T-TI 3. AT64-PI-. AT64N--. AT64T-TI-. AT64T-TI-. 3. AT64-PI-.8 AT64N--.8 AT64T-TI-.8 AT64T-TI-.8 f MAX (khz) Ordering Code Package Operation Range ( C to C) ( C to C) ( C to C) (-4 C to 8 C) (-4 C to 8 C) (-4 C to 8 C) Package Type 8-pin,.3" Wide, Plastic Dual Inline Package (PDIP) 8-lead,." Wide, Plastic Gull Wing Small Outline (JEDEC IC) 4-lead,." Wide, Thin Shrink Small Outline Package (TSP) -lead,." Wide, Thin Shrink Small Outline Package (TSP) Optio Blank Standard Device (4.V to.v) -. Low Voltage (.V to.v) -.8 Low Voltage (.8V to 3.6V) 6F 8/

18 Packaging Information P3, 8-pin,.3" Wide, Plastic Dual Inline Package (PDIP) Dimeio in Inches and (Millimeters) JEDEC STANDARD MS- BA, 8-lead,." Wide, Plastic Gull Wing Small Outline (JEDEC IC) Dimeio in Inches and (Millimeters).4 (.6).3 (9.) PIN. (.8).3 (.33).8 (.).4 (6.) PIN. (3.99). (3.8).44 (6.).8 (.9).3 (.6) REF.3 (.94). (.69). (.) BSC. (.33) MAX SEATING PLANE. (3.8). (.9). (.3).8 (.3). (.8).4 (.4). (.4) BSC. (.38) MIN. (.9).4 (.36).3 (8.6).3 (.6) REF.43 (.9) MAX.96 (4.98).89 (4.8). (.4).4 (.).68 (.3).3 (.3) REF 8. (.4). (.3). (.).6 (.46), 4-lead,." Wide, Thin Shrink Small Outline Package (TSP) Dimeio in (Inches) and Millimeters*, -lead,." Wide, Thin Shrink Small Outline Package (TSP) Dimeio in (Inches) and Millimeters* PIN INDEX MARK PIN INDEX MARK 4. (.) 4.3 (.69) 6. (.6) 6. (.46) 4. (.) 4.3 (.69) 6. (.6) 6. (.46). (.) 4.9 (.93). (.4) MAX 6.6 (.6) 6.4 (.). (.4) MAX.6 (.6) BSC.3 (.).9 (.). (.6). (.) SEATING PLANE.6 (.6) BSC.3 (.).9 (.). (.6). (.) SEATING PLANE 8 REF. (.3).4 (.8). (.8).9 (.4) *Controlling dimeion: millimeters 8 REF. (.3).4 (.8) *Controlling dimeion: millimeters. (.8).9 (.4) 8 AT8/6/3/64 6F 8/

19 Atmel Headquarters Corporate Headquarters 3 Orchard Parkway San Jose, CA 93 TEL (48) 44-3 FAX (48) 48-6 Europe Atmel SarL Route des Arsenaux 4 Casa Postale 8 CH- Fribourg Switzerland TEL (4) FAX (4) Asia Atmel Asia, Ltd. Room 9 Chinachem Golden Plaza Mody Road Tsimhatsui East Kowloon Hong Kong TEL (8) -98 FAX (8) -369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg Shinkawa Chuo-ku, Tokyo 4-33 Japan TEL (8) FAX (8) Atmel Product Operatio Atmel Colorado Springs E. Cheyenne Mtn. Blvd. Colorado Springs, CO 896 TEL (9) 6-33 FAX (9) 4-9 Atmel Grenoble Avenue de Rochepleine BP 3 38 Saint-Egreve Cedex, France TEL (33) FAX (33) Atmel Heilbronn Theresietrasse POB 33 D-4 Heilbronn, Germany TEL (49) FAX (49) Atmel Nantes La Chantrerie BP Nantes Cedex 3, France TEL (33) FAX (33) Atmel Rousset Zone Industrielle 36 Rousset Cedex, France TEL (33) FAX (33) Atmel Smart Card ICs Scottish Enterprise Technology Park East Kilbride, Scotland G QR TEL (44) 3-3- FAX (44) literature@atmel.com Web Site BBS -(48) Atmel Corporation. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company s standard warranty which is detailed in Atmel s Terms and Conditio located on the Company s web site. The Company assumes no respoibility for any errors which may appear in this document, reserves the right to change devices or specificatio detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licees to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel s products are not authorized for use as critical components in life support devices or systems. ATMEL is the registered trademark of Atmel. Other terms and product names may be the trademark of others. Printed on recycled paper. 6F 8//xM

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