VCC CS SO WP GND HOLD SCK SI VCC HOLD CS SO NC NC SCK SI WP GND
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1 Features Serial Peripheral Interface (SPI) Compatible Supports SPI Modes (,) and 3 (,) Low-voltage and Standard-voltage Operation. (V CC = 4.V to.v). (V CC =.V to.v).8 (V CC =.8V to 3.6V) 3. MHz Clock Rate (V) 3-byte Page Mode Block Write Protection Protect /4, /, or Entire Array Write Protect (WP) Pin and Write Disable Itructio for both Hardware and Software Data Protection Self-timed Write Cycle ( ms Typical) High-reliability Endurance: One Million Write Cycles Data Retention: Years Automotive Grade and Extended Temperature Devices Available 8-pin PDIP, 8-lead JEDEC IC, and 4-lead and -lead TSP Packages Description The AT8/6/3/64 provides 89/6384/368/636 bits of serial electrically-erasable programmable read only memory (EEPROM) organized as 4/48/496/89 words of 8 bits each. The device is optimized for use in many industrial and commercial applicatio where low-power and low-voltage operation are essential. The AT8/6/3/64 is available in space saving 8-pin PDIP, 8- lead JEDEC IC, and 4-lead and -lead TSP packages. Pin Configuration Pin Name GND VCC WP HOLD DC Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Write Protect Suspends Serial Input No Connect Don t Connect WP GND WP GND 8-pin PDIP lead TSP VCC HOLD VCC HOLD WP GND WP GND DC 8-lead IC lead TSP* (continued) VCC HOLD VCC HOLD HOLD DC SPI Serial EEPROMs 8K (4 x 8) 6K (48 x 8) 3K (496 x 8) 64K (89 x 8) AT8 AT6 AT3 AT64 Note: *Pi 3, 4 and, 8 are internally connected for 4-lead TSP socket compatibility. Rev. 6F 8/
2 Absolute Maximum Ratings* The AT8/6/3/64 is enabled through the Chip Select pin () and accessed via a 3- wire interface coisting of Serial Data Input (), Serial Data Output (), and Serial Clock (). All programming cycles are completely self-timed, and no separate ERASE cycle is required before WRITE. BLOCK WRITE protection is enabled by programming the status register with one of four blocks of write protection. Separate program enable and program disable itructio are provided for additional data protection. Hardware data protection is provided via the WP pin to protect agait inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Operating Temperature... - C to + C Storage Temperature C to + C Voltage on Any Pin with Respect to Ground...-.V to +.V Maximum Operating Voltage... 6.V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. DC Output Current.... ma Block Diagram AT8/6/3/64 6F 8/
3 AT8/6/3/64 Pin Capacitance () Applicable over recommended operating range from T A = C, f =. MHz, V CC = +.V (unless otherwise noted). Symbol Test Conditio Max Units Conditio C OUT Output Capacitance () 8 pf V OUT = V C IN Input Capacitance(,,, WP, HOLD) 6 pf V IN = V Note:. This parameter is characterized and is not % tested. DC Characteristics () Applicable over recommended operating range from: T AI = -4 C to +8 C, V CC = +.8V to +.V, T AC = C to + C, V CC = +.8V to +.V (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units V CC Supply Voltage V V CC Supply Voltage.. V V CC3 Supply Voltage 4.. V I CC Supply Current V CC =.V at MHz, = Open, Read 3. ma I CC Supply Current V CC =.V at MHz, = Open, Read, Write Note:. V IL min and V IH max are reference only and are not tested.. ma I SB Standby Current V CC =.8V, = V CC.. µa I SB Standby Current V CC =.V, = V CC.. µa I SB3 Standby Current V CC =.V, = V CC.. µa I IL Input Leakage V IN = V to V CC -3. µa I OL Output Leakage V IN = V to V CC, T AC = C to C µa V IL () Input Low-voltage -.6 V CC x.3 V V IH () Input High-voltage V CC x. V CC +. V V OL Output Low-voltage 4.V V CC.V I OL = 3. ma.4 V V OH Output High-voltage I OH = -.6 ma V CC -.8 V V OL Output Low-voltage.8V V CC 3.6V I OL =. ma. V V OH Output High-voltage I OH = - µa V CC -. V 6F 8/ 3
4 AC Characteristics Applicable over recommended operating range from T A = -4 C to +8 C, V CC = As Specified, CL = TTL Gate and pf (unless otherwise noted). Symbol Parameter Voltage Min Max Units f Clock Frequency MHz t RI Input Rise Time µs t FI Input Fall Time µs t WH High Time t WL Low Time t High Time t S Setup Time t H Hold Time t SU Data In Setup Time t H Data In Hold Time t HD Hold Setup Time t CD Hold Hold Time t V Output Valid t HO Output Hold Time AT8/6/3/64 6F 8/
5 AT8/6/3/64 AC Characteristics (Continued) Applicable over recommended operating range from T A = -4 C to +8 C, V CC = As Specified, CL = TTL Gate and pf (unless otherwise noted). Symbol Parameter Voltage Min Max Units t LZ Hold to Output Low Z t HZ Hold to Output High Z t DIS Output Disable Time t WC Write Cycle Time Endurance ().V, C, Page Mode M Write Cycles Note:. This parameter is characterized and is not % tested. ms 6F 8/
6 Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin () is always an input, the AT8/6/3/64 always operates as a slave. TRANSMITTER/RECEIVER: The AT8/6/3/64 has separate pi designated for data tramission () and reception (). MSB: The Most Significant Bit (MSB) is the first bit tramitted and received. SERIAL OP-CODE: After the device is selected with going low, the first byte will be received. This byte contai the op-code that defines the operatio to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT8/6/3/64, and the serial output pin () will remain in a high impedance state until the falling edge of is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT8/6/3/64 is selected when the pin is low. When the device is not selected, data will not be accepted via the pin, and the serial output pin () will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the pin to select the AT8/6/3/64. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the pin is low. To resume serial communication, the HOLD pin is brought high while the pin is low ( may still toggle during HOLD). Inputs to the pin will be ignored while the pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operatio when held high. When the WP pin is brought low and WPEN bit is, all write operatio to the status register are inhibited. WP going low while is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is "". This will allow the user to itall the AT8/6/3/64 in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functio are enabled when the WPEN bit is set to. 6 AT8/6/3/64 6F 8/
7 AT8/6/3/64 SPI Serial Interface 6F 8/
8 Functional Description The AT8/6/3/64 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 68 and 68HC series of microcontrollers. The AT8/6/3/64 utilizes an 8-bit itruction register. The list of itructio and their operation codes are contained in Table. All itructio, addresses, and data are traferred with the MSB first and start with a high-to-low traition. Table. Itruction Set for the AT8/6/3/64 Itruction Name Itruction Format Operation WREN X Set Write Enable Latch WRDI X Reset Write Enable Latch RDSR X Read Status Register WRSR X Write Status Register READ X Read Data from Memory Array WRITE X Write Data to Memory Array WRITE ENABLE (WREN): The device will power-up in the write disable state when V CC is applied. All programming itructio must therefore be preceded by a Write Enable itruction. WRITE DISABLE (WRDI): To protect the device agait inadvertent writes, the Write Disable itruction disables all programming modes. The WRDI itruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register itruction provides access to the status register. The READY/BUSY and Write Enable status of the device can be determined by the RDSR itruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR itruction. Table. Status Register Format Bit Bit 6 Bit Bit 4 Bit 3 Bit Bit Bit WPEN X X X BP BP WEN RDY Table 3. Read Status Register Bit Definition Bit Bit (RDY) Bit (WEN) Definition Bit (BP) See Table 3. Bit 3 (BP) See Table 3. Bit = (RDY) indicates the device is READY. Bit = indicates the write cycle is in progress. Bit = indicates the device is not WRITE ENABLED. Bit = indicates the device is WRITE ENABLED. Bits 4-6 are s when device is not in an internal write cycle. Bit (WPEN) See Table. Bits - are s during an internal write cycle. 8 AT8/6/3/64 6F 8/
9 AT8/6/3/64 WRITE STATUS REGISTER (WRSR): The WRSR itruction allows the user to select one of four levels of protection. The AT8/6/3/64 is divided into four array segments. One quarter (/4), one half (/), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be READ only. The block write protection levels and corresponding status register control bits are shown in Table 4. The three bits, BP, BP, and WPEN are nonvolatile cells that have the same properties and functio as the regular memory cells (e.g. WREN, t WC, RDSR). Table 4. Block Write Protect Bits Level Status Register Bits Array Addresses Protected BP BP AT8 AT6 AT3 AT64 None None None None (/4) (/) 3(All) 3-3FF -3FF 6 -FF 4 -FF C -FFF 8 -FFF 8 -FFF -FFF The WRSR itruction also allows the user to enable or disable the write protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is. When the device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the blockprotected sectio in the memory array are disabled. Writes are only allowed to sectio of the memory which are not block-protected. NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to, as long as the WP pin is held low. Table. WPEN Operation WPEN WP WEN -3FF Protected Blocks -FF -FFF Unprotected Blocks -FFF Status Register X Protected Protected Protected X Protected Writable Writable Low Protected Protected Protected Low Protected Writable Protected X High Protected Protected Protected X High Protected Writable Writable 6F 8/ 9
10 READ SEQUEE (READ): Reading the AT8/6/3/64 via the (Serial Output) pin requires the following sequence. After the line is pulled low to select a device, the READ op-code is tramitted via the line followed by the byte address to be read (A - A, Refer to Table 6). Upon completion, any data on the line will be ignored. The data (D - D) at the specified address is then shifted out onto the line. If only one byte is to be read, the line should be driven high after the data comes out. The READ sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous READ cycle. WRITE SEQUEE (WRITE): In order to program the AT8/6/3/64, two separate itructio must be executed. First, the device must be write enabled via the Write Enable (WREN) Itruction. Then a Write (WRITE) Itruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the Block Write Protection Level. During an internal write cycle, all commands will be ignored except the RDSR itruction. A Write Itruction requires the following sequence. After the line is pulled low to select the device, the WRITE op-code is tramitted via the line followed by the byte address (A - A) and the data (D - D) to be programmed (Refer to Table 6). Programming will start after the pin is brought high. (The LOW-to-High traition of the pin must occur during the low-time immediately after clocking in the D (LSB) data bit. The READY/BUSY status of the device can be determined by initiating a READ STATUS REGISTER (RDSR) Itruction. If Bit =, the WRITE cycle is still in progress. If Bit =, the WRITE cycle has ended. Only the READ STATUS REGISTER itruction is enabled during the WRITE programming cycle. The AT8/6/3/64 is capable of a 3-byte PAGE WRITE operation. After each byte of data is received, the five low order address bits are internally incremented by one; the high order bits of the address will remain cotant. If more than 3 bytes of data are tramitted, the address counter will roll over and the previously written data will be overwritten. The AT8/6/3/64 is automatically returned to the write disable state at the completion of a WRITE cycle. NOTE: If the device is not Write enabled (WREN), the device will ignore the Write itruction and will return to the standby state, when is brought high. A new falling edge is required to re-initiate the serial communication. Table 6. Address Key Address AT8 AT6 AT3 AT64 A N A 9 - A A - A A - A A - A Don t Care Bits A - A A - A A - A A - A 3 AT8/6/3/64 6F 8/
11 AT8/6/3/64 Timing Diagrams Synchronous Data Timing (for Mode ) t V IH V IL ts t H V IH t WH t WL V IL t SU t H V IH V IL VALID IN t V t HO t DIS V OH HI-Z HI-Z V OL WREN Timing WRDI Timing 6F 8/
12 RDSR Timing INSTRUCTION DATA OUT HIGH IMPEDAE MSB WRSR Timing INSTRUCTION 6 DATA IN 4 3 HIGH IMPEDAE READ Timing INSTRUCTION BYTE ADDRESS HIGH IMPEDAE MSB 6 DATA OUT 4 3 AT8/6/3/64 6F 8/
13 AT8/6/3/64 WRITE Timing INSTRUCTION BYTE ADDRESS DATA IN HIGH IMPEDAE HOLD Timing t CD t CD t HD HO LD t HD t HZ t LZ 6F 8/ 3
14 AT8 Ordering Information t WC (max) (ms) I CC (max) (µa) I SB (max) (µa). 3 AT8-PC AT8N-SC AT8T-TC AT8T-TC 3. AT8-PC-. AT8N-SC-. AT8T-TC-. AT8T-TC-. 3. AT8-PC.8 AT8N-SC-.8 AT8T-TC-.8 AT8T-TC AT8-PI AT8N- AT8T-TI AT8T-TI 3. AT8-PI-. AT8N--. AT8T-TI-. AT8T-TI-. 3. AT8-PI-.8 AT8N--.8 AT8T-TI-.8 AT8T-TI-.8 f MAX (khz) Ordering Code Package Operation Range ( C to C) ( C to C) ( C to C) (-4 C to 8 C) (-4 C to 8 C) (-4 C to 8 C) Package Type 8-pin,.3" Wide, Plastic Dual Inline Package (PDIP) 8-lead,." Wide, Plastic Gull Wing Small Outline (JEDEC IC) 4-lead,." Wide, Thin Shrink Small Outline Package (TSP) -lead,." Wide, Thin Shrink Small Outline Package (TSP) Optio Blank Standard Device (4.V to.v) -. Low Voltage (.V to.v) -.8 Low Voltage (.8V to 3.6V) 4 AT8/6/3/64 6F 8/
15 AT8/6/3/64 AT6 Ordering Information t WC (max) (ms) I CC (max) (µa) I SB (max) (µa). 3 AT6-PC AT6N-SC AT6T-TC AT6T-TC 3. AT6-PC-. AT6N-SC-. AT6T-TC-. AT6T-TC-. 3. AT6-PC-.8 AT6N-SC-.8 AT6T-TC-.8 AT6T-TC AT6-PI AT6N- AT6T-TI AT6T-TI 3. AT6-PI-. AT6N--. AT6T-TI-. AT6T-TI-. 3. AT6-PI-.8 AT6N--.8 AT6T-TI-.8 AT6T-TI-.8 f MAX (khz) Ordering Code Package Operation Range ( C to C) ( C to C) ( C to C) (-4 C to 8 C) (-4 C to 8 C) (-4 C to 8 C) Package Type 8-pin,.3" Wide, Plastic Dual Inline Package (PDIP) 8-lead,." Wide, Plastic Gull Wing Small Outline (JEDEC IC) 4-lead,." Wide, Thin Shrink Small Outline Package (TSP) -lead,." Wide, Thin Shrink Small Outline Package (TSP) Optio Blank Standard Device (4.V to.v) -. Low Voltage (.V to.v) -.8 Low Voltage (.8V to 3.6V) 6F 8/
16 AT3 Ordering Information t WC (max) (ms) I CC (max) (µa) I SB (max) (µa). 3 AT3-PC AT3N-SC AT3-TC AT3-TC 3. AT3-PC-. AT3N-SC-. AT3-TC-. AT3-TC-.. 3 AT3-PI AT3N- AT3-TI AT3-TI 3. AT3-PI-. AT3N--. AT3-TI-. AT3-TI-. f MAX (khz) Ordering Code Package Operation Range 8S ( C to C) ( C to C) (-4 C to 8 C) (-4 C to 8 C) Package Type 8-pin,.3" Wide, Plastic Dual Inline Package (PDIP) 8-lead,." Wide, Plastic Gull Wing Small Outline (JEDEC IC) 4-lead,." Wide, Thin Shrink Small Outline Package (TSP) -lead,." Wide, Thin Shrink Small Outline Package (TSP) Optio Blank Standard Device (4.V to.v) -. Low Voltage (.V to.v) 6 AT8/6/3/64 6F 8/
17 AT8/6/3/64 AT64 Ordering Information t WC (max) (ms) I CC (max) (µa) I SB (max) (µa). 3 AT64-PC AT64N-SC AT64T-TC AT64T-TC 3. AT64-PC-. AT64N-SC-. AT64T-TC-. AT64T-TC-. 3. AT64-PC-.8 AT64N-SC-.8 AT64T-TC-.8 AT64T-TC AT64-PI AT64N- AT64T-TI AT64T-TI 3. AT64-PI-. AT64N--. AT64T-TI-. AT64T-TI-. 3. AT64-PI-.8 AT64N--.8 AT64T-TI-.8 AT64T-TI-.8 f MAX (khz) Ordering Code Package Operation Range ( C to C) ( C to C) ( C to C) (-4 C to 8 C) (-4 C to 8 C) (-4 C to 8 C) Package Type 8-pin,.3" Wide, Plastic Dual Inline Package (PDIP) 8-lead,." Wide, Plastic Gull Wing Small Outline (JEDEC IC) 4-lead,." Wide, Thin Shrink Small Outline Package (TSP) -lead,." Wide, Thin Shrink Small Outline Package (TSP) Optio Blank Standard Device (4.V to.v) -. Low Voltage (.V to.v) -.8 Low Voltage (.8V to 3.6V) 6F 8/
18 Packaging Information P3, 8-pin,.3" Wide, Plastic Dual Inline Package (PDIP) Dimeio in Inches and (Millimeters) JEDEC STANDARD MS- BA, 8-lead,." Wide, Plastic Gull Wing Small Outline (JEDEC IC) Dimeio in Inches and (Millimeters).4 (.6).3 (9.) PIN. (.8).3 (.33).8 (.).4 (6.) PIN. (3.99). (3.8).44 (6.).8 (.9).3 (.6) REF.3 (.94). (.69). (.) BSC. (.33) MAX SEATING PLANE. (3.8). (.9). (.3).8 (.3). (.8).4 (.4). (.4) BSC. (.38) MIN. (.9).4 (.36).3 (8.6).3 (.6) REF.43 (.9) MAX.96 (4.98).89 (4.8). (.4).4 (.).68 (.3).3 (.3) REF 8. (.4). (.3). (.).6 (.46), 4-lead,." Wide, Thin Shrink Small Outline Package (TSP) Dimeio in (Inches) and Millimeters*, -lead,." Wide, Thin Shrink Small Outline Package (TSP) Dimeio in (Inches) and Millimeters* PIN INDEX MARK PIN INDEX MARK 4. (.) 4.3 (.69) 6. (.6) 6. (.46) 4. (.) 4.3 (.69) 6. (.6) 6. (.46). (.) 4.9 (.93). (.4) MAX 6.6 (.6) 6.4 (.). (.4) MAX.6 (.6) BSC.3 (.).9 (.). (.6). (.) SEATING PLANE.6 (.6) BSC.3 (.).9 (.). (.6). (.) SEATING PLANE 8 REF. (.3).4 (.8). (.8).9 (.4) *Controlling dimeion: millimeters 8 REF. (.3).4 (.8) *Controlling dimeion: millimeters. (.8).9 (.4) 8 AT8/6/3/64 6F 8/
19 Atmel Headquarters Corporate Headquarters 3 Orchard Parkway San Jose, CA 93 TEL (48) 44-3 FAX (48) 48-6 Europe Atmel SarL Route des Arsenaux 4 Casa Postale 8 CH- Fribourg Switzerland TEL (4) FAX (4) Asia Atmel Asia, Ltd. Room 9 Chinachem Golden Plaza Mody Road Tsimhatsui East Kowloon Hong Kong TEL (8) -98 FAX (8) -369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg Shinkawa Chuo-ku, Tokyo 4-33 Japan TEL (8) FAX (8) Atmel Product Operatio Atmel Colorado Springs E. Cheyenne Mtn. Blvd. Colorado Springs, CO 896 TEL (9) 6-33 FAX (9) 4-9 Atmel Grenoble Avenue de Rochepleine BP 3 38 Saint-Egreve Cedex, France TEL (33) FAX (33) Atmel Heilbronn Theresietrasse POB 33 D-4 Heilbronn, Germany TEL (49) FAX (49) Atmel Nantes La Chantrerie BP Nantes Cedex 3, France TEL (33) FAX (33) Atmel Rousset Zone Industrielle 36 Rousset Cedex, France TEL (33) FAX (33) Atmel Smart Card ICs Scottish Enterprise Technology Park East Kilbride, Scotland G QR TEL (44) 3-3- FAX (44) literature@atmel.com Web Site BBS -(48) Atmel Corporation. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company s standard warranty which is detailed in Atmel s Terms and Conditio located on the Company s web site. The Company assumes no respoibility for any errors which may appear in this document, reserves the right to change devices or specificatio detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licees to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel s products are not authorized for use as critical components in life support devices or systems. ATMEL is the registered trademark of Atmel. Other terms and product names may be the trademark of others. Printed on recycled paper. 6F 8//xM
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Features Single-voltage Operation 5V Read 5V Reprogramming Fast Read Access Time 35 ns Internal Program Control and Timer 8K Word Boot Block with Lockout Fast Erase Cycle Time 10 seconds Word-by-word Programming
More information1-Megabit (128K x 8) Low Voltage Paged Parallel EEPROMs
Features Single 3.3V ± 10% Supply Fast Read Access Time - 200 ns Automatic Page Write Operation Internal Address and Data Latches for 128 Bytes Internal Control Timer Fast Write Cycle Time Page Write Cycle
More information4-megabit (512K x 8) Single 2.7-volt Battery-Voltage Flash Memory AT49BV040 AT49LV040
Features Single Voltage for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV) Fast Read Access Time 70 ns Internal Program Control and Timer 16K Bytes Boot Block with Lockout Fast Chip Erase Cycle Time
More informationBattery-Voltage. 256K (32K x 8) Parallel EEPROMs AT28BV256. Features. Description. Pin Configurations
Features Single 2.7V - 3.6V Supply Fast Read Access Time - 200 ns Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control Timer Fast Write Cycle Times Page Write
More information256K (32K x 8) 3-volt Only Flash Memory
Features Single Supply Voltage, Range 3V to 3.6V 3-Volt Only Read and Write Operation Software Protected Programming Low Power Dissipation 15 ma Active Current 40 µa CMOS Standby Current Fast Read Access
More informationSPI Serial EEPROM AT25010A AT25020A AT25040A. Not Recommended for New Design
Features Serial Peripheral Interface (SPI) Compatible Supports SPI Modes (,) and 3 (1,1) Data Sheet Describes Mode Operation Low-voltage and Standard-voltage Operation 2.7 (V CC = 2.7V to 5.5V) 1.8 (V
More informationDIP Top View VCC WE A17 NC A16 A15 A12 A14 A13 A8 A9 A11 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 I/O1 I/O2 GND.
Features Fast Read Access Time - 70 ns 5-volt Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 1024 Sectors (256 bytes/sector) Internal Address and Data Latches for
More informationTwo-wire Serial EEPROM Smart Card Modules 1K (128 x 8) 2K (256 x 8) 4K (512 x 8) 8K (1024 x 8) 16K (2048 x 8)
Features Low-voltage and Standard-voltage Operation, VCC = 2.7V 5.5V Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K), or 2048 x 8 (16K) Two-wire Serial Interface Schmitt Trigger,
More information4-Megabit (512K x 8) 5-volt Only 256-Byte Sector Flash Memory AT29C040A. Features. Description. Pin Configurations
Features Fast Read Access Time - 120 ns 5-Volt Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 2048 Sectors (256 bytes/sector) Internal Address and Data Latches for
More information64K (8K x 8) Parallel EEPROM with Page Write and Software Data Protection AT28C64B. Features. Description. Pin Configurations
Features Fast Read Access Time 150 ns Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Fast Write Cycle Times Page Write Cycle Time: 10 ms Maximum (Standard) 2 ms Maximum (Option)
More information64K (8K x 8) Low-voltage Parallel EEPROM with Page Write and Software Data Protection AT28LV64B. 3-Volt, 64K E 2 PROM with Data Protection
Features Single 3.3V ± 10% Supply Hardware and Software Data Protection Low-power Dissipation 15mAActiveCurrent 20 µa CMOS Standby Current Fast Read Access Time - 200 ns Automatic Page Write Operation
More information1-megabit 2.7-volt Only Serial DataFlash AT45DB011. AT45DB011 Preliminary 16- Megabit 2.7-volt Only Serial DataFlash
Features Single 2.7V - 3.6V Supply Serial Interface Architecture Page Program Operation Single Cycle Reprogram (Erase and Program) 512 Pages (264 Bytes/Page) Main Memory Optional Page and Block Erase Operations
More informationIntegrated circuit 93C56
Integrated circuit 93C56 Features Low Voltage and Standard Voltage Operation 5.0 (V CC = 4.5V to 5.5V) 2.7 (V CC = 2.7V to 5.5V) 2.5 (V CC = 2.5V to 5.5V) 1.8 (V CC = 1.8V to 5.5V) User Selectable Internal
More information1-Megabit (128K x 8) 5-volt Only Flash Memory AT29C010A. Features. Description. Pin Configurations
Features Fast Read Access Time - 70 ns 5-Volt Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 1024 Sectors (128 bytes/sector) Internal Address and Data Latches for
More information2-wire Serial EEPROM AT24C21. 2-Wire, 1K Serial EEPROM. Features. Description. Not Recommended for New Designs. Pin Configurations.
Features 2-wire Serial Interface Schmitt Trigger, Filtered Inputs For Noise Suppression DDC1 / DDC2 Interface Compliant for Monitor Identification Low-voltage Operation 2.5 (V CC = 2.5V to 5.5V) Internally
More information2-wire Serial EEPROM AT24C01A AT24C02 AT24C04 AT24C08 AT24C16
Features Low-voltage and Standard-voltage Operation 2.7(V CC =2.7Vto5.5V) 1.8(V CC =1.8Vto5.5V) Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K) 2-wire Serial
More information256 (32K x 8) High-speed Parallel EEPROM AT28HC256N. Features. Description. Pin Configurations
Features Fast Read Access Time 90 ns Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control Timer Fast Write Cycle Times Page Write Cycle Time: 3 ms or 10 ms Maximum
More informationSPI Serial EEPROMs 8K (1024 x 8) 16K (2048 x 8) AT25080B AT25160B. Preliminary
Features Serial Peripheral Interface (SPI) Compatible Supports SPI Modes (,) and 3 (,) Datasheet Describes Mode Operation Low-voltage and Standard-voltage Operation.8 (V CC =.8V to.v) MHz Clock Rate (V)
More informationAT94K Series Field Programmable System Level Integrated Circuit. Application Note. FPSLIC Baud Rate Generator
FPSLIC Baud Rate Generator Features: Generates any required baud rate High baud rates at low crystal clock frequencies Uses both internal and external clock sources Supports in both single speed and double
More informationDistributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. APPLICATION NOTE A V A I L A B L E AN61 16K X25160 2K x 8 Bit SPI Serial
More informationDIP Top View VCC A12 A14 A13 A6 A5 A4 A3 A2 A1 A0 A8 A9 A11 A10 I/O7 I/O6 I/O0 I/O1 I/O2 I/O5 I/O4 I/O3 GND. TSOP Top View Type 1 A11 A9 A8 A13 A14
Features Fast Read Access Time 70 ns 5-volt Only Reprogramming Page Program Operation Single Cycle Reprogram (Erase and Program) Internal Address and Data Latches for 64 Bytes Internal Program Control
More information32-megabit 2.7-volt Only Serial DataFlash AT45DB321. AT45DB321 Preliminary 16- Megabit 2.7-volt Only Serial DataFlash
Features Single 2.7V - 3.6V Supply Serial-interface Architecture Page Program Operation Single Cycle Reprogram (Erase and Program) 8192 Pages (528 Bytes/Page) Main Memory Optional Page and Block Erase
More information16-megabit 2.7-volt Only Serial DataFlash AT45DB161
Features Single 2.7V - 3.6V Supply Serial Interface Architecture Page Program Operation Single Cycle Reprogram (Erase and Program) 4096 Pages (528 Bytes/Page) Main Memory Optional Page and Block Erase
More informationCAT25C02/04/08/16/32 2K/4K/8K/16K/32K SPI Serial CMOS E 2 PROM FEATURES
K/K/8K/6K/K SPI Serial CMOS E PROM FEATURES 0 MHz SPI Compatible.8 to 6.0 Volt Operation Hardware and Software Protection Zero Standby Current Low Power CMOS Technology SPI Modes (0,0 &,) Commercial, Industrial
More information8-Megabit 5-volt Only Serial DataFlash AT45D081. Features. Description
Features Single 4.5V - 5.5V Supply Serial Interface Architecture Page Program Operation Single Cycle Reprogram (Erase and Program) 4096 Pages (264 Bytes/Page) Main Memory Two 264-Byte SRAM Data Buffers
More information(Serial Periphrial Interface (SPI) Synchronous Bus)
NM25C040 4K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus) General Description The NM25C040 is a 4096-bit CMOS EEPROM with an SPI compatible serial interface. The NM25C040 is
More information512K (64K x 8) 5-volt Only Flash Memory AT29C512
Features Fast Read Access Time 70 ns 5-volt Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 512 Sectors (128 Bytes/Sector) Internal Address and Data Latches for 128
More information4-megabit (512K x 8) Single 2.7-volt Battery-Voltage Flash Memory AT49BV040 AT49BV040T AT49LV040 AT49LV040T
Features Single Voltage for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV) Fast Read Access Time 70 ns Internal Program Control and Timer 16K Bytes Boot Block with Lockout Fast Chip Erase Cycle Time
More information8-bit RISC Microcontroller. Application Note. AVR 305: Half Duplex Compact Software UART
AVR 305: Half Duplex Compact Software UART Features 32 Words of Code, Only Handles Baud Rates of up to 38.4 kbps with a 1 MHz XTAL Runs on Any AVR Device Only Two Port Pins Required Does Not Use Any Timer
More information256K (32K x 8) 5-volt Only Flash Memory AT29C256
Features Fast Read Access Time 70 ns 5-volt Only Reprogramming Page Program Operation Single Cycle Reprogram (Erase and Program) Internal Address and Data Latches for 64 Bytes Internal Program Control
More information64K (8K x 8) High Speed Parallel EEPROM with Page Write and Software Data Protection AT28HC64BF
Features Fast Read Access Time 70 ns Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Fast Write Cycle Times Page Write Cycle Time: 2 ms Maximum (Standard) 1 to 64-byte Page
More informationX K x 8 Bit 64K. 5MHz SPI Serial E 2 PROM with Block Lock TM Protection
64K X25650 5MHz SPI Serial E 2 PROM with Block Lock TM Protection 8K x 8 Bit FEATURES 5MHz Clock Rate Low Power CMOS
More informationSOIC VCC RESET A11 A10 A9 A8 A7 A6 A5 A4 A12 A13 A14 A15 A16 A17 A18 A19 NC NC NC NC I/O0 RDY/BUSY I/O1 I/O7 I/O6 I/O5 I/O4 VCC I/O2 I/O3 GND GND
Features Single Voltage Operation 5V Read 5V Reprogramming Fast Read Access Time - 90 ns Internal Program Control and Timer 16K Bytes Boot Block With Lockout Fast Erase Cycle Time - 10 seconds Byte-By-Byte
More informationTwo-Wire Serial EEPROM AT24C164 (1)
Features Low Voltage and Standard Voltage Operation 2.7 (V CC = 2.7V to 5.5V) 1.8 (V CC = 1.8V to 5.5V) Internally Organized 2048 x 8 (16K) Two-Wire Serial Interface Schmitt Trigger, Filtered Inputs for
More information256K (32K x 8) 5-volt Only Flash Memory AT29C256
Features Fast Read Access Time 70 ns 5-volt Only Reprogramming Page Program Operation Single Cycle Reprogram (Erase and Program) Internal Address and Data Latches for 64 Bytes Internal Program Control
More information1-megabit (64K x 16) 3-volt Only Flash Memory AT49BV1024A AT49LV1024A
Features Single-voltage Operation Read/Write Operation: 2.7V to 3.6V (BV). 3.0V to 3.6V(LV) Fast Read Access Time 45 ns Internal Program Control and Timer 8K Word Boot Block with Lockout Fast Erase Cycle
More information2-wire Serial EEPROM AT24C01A AT24C02 AT24C04 AT24C08 AT24C16. Features. Description. Pin Configurations. 1K (128 x 8) 2K (256 x 8) 4K (512 x 8)
Features Low-voltage and Standard-voltage Operation 2.7 (V CC = 2.7V to 5.5V) 1.8 (V CC = 1.8V to 5.5V) Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K) 2-wire
More information8051 Microcontrollers. Application Note. Migration from AT89C5131 & AT89C5131A-L to AT89C5131A-M
Migration from AT89C5131 & AT89C5131A-L to AT89C5131A-M This application note is a guide to assist current AT89C5131 & AT89C5131A-L users in converting existing designs to the AT89C5131A-M devices. In
More information2-Wire Serial EEPROM 32K (4096 x 8) 64K (8192 x 8) AT24C32A AT24C64A. Features. Description. Pin Configurations
Features Low-Voltage and Standard-Voltage Operation 2.7 (V CC = 2.7V to 5.5V) 1.8 (V CC = 1.8V to 5.5V) Low-Power Devices (I SB = 6 µa @ 5.5V) Available Internally Organized 4096 x 8, 8192 x 8 2-Wire Serial
More informationAT25M01. SPI Serial EEPROM 1-Mbit (131,072 x 8) DATASHEET. Features. Description
AT25M1 SPI Serial EEPROM 1-Mbit (131,72 x 8) DATASHEET Features Serial Peripheral Interface (SPI) Compatible Supports SPI Modes (,) and 3 (1,1) Datasheet Describes Mode Operation Low-voltage Operation
More information4-megabit (512K x 8) 5-volt Only 256-byte Sector Flash Memory AT29C040A
Features Fast Read Access Time 90 ns 5-volt Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 2048 Sectors (256 Bytes/Sector) Internal Address and Data Latches for
More informationFPGA Configuration EEPROM Memory. Application Note. Programming Atmel s EEPROMs: AT17LV020(A) vs. AT17LV002(A) Introduction.
Programming Atmel s EEPROMs: AT17LV020(A) vs. AT17LV002(A) Introduction This application note provides Atmel s customers with a description of the principal differences in programming the AT17LV020(A)
More informationAT17 Series FPGA. Configuration Memory. Application Note. In-System Programming Circuits for AT17 Series Configurators with Atmel and Xilinx FPGAs
In-System Circuits for AT1 Series Configurators with Atmel and Xilinx s Atmel AT1 (1) series configurators use a simple serial-access procedure to configure one or more Field Programmable Gate Arrays (s)
More information2-wire Serial EEPROM AT24C1024. Features. Description. Pin Configurations. 1M (131,072 x 8)
Features Low-voltage Operation 2.7 (V CC = 2.7V to 5.5V) Internally Organized 3,072 x 8 2-wire Serial Interface Schmitt Triggers, Filtered Inputs for Noise Suppression Bi-directional Data Transfer Protocol
More information2-megabit (256K x 8) 3-volt Only Flash Memory AT29LV020
Features Single Voltage, Range 3V to 3.6V Supply 3-volt Only Read and Write Operation Software Protected Programming Fast Read Access Time - 100 ns Low Power Dissipation 15mAActiveCurrent 40 µa CMOS Standby
More informationSPI. 64K Bits. Serial EEPROM
GT25C64 SPI 64K Bits Serial EEPROM Copyright 2011 Giantec Semiconductor Inc. (Giantec). All rights reserved. Giantec reserves the right to make changes to this specification and its products at any time
More informationBattery-Voltage. 4-megabit (512K x 8/ 256K x 16) Single 2.7-volt. Flash Memory AT49BV4096A AT49LV4096A
Features Single-voltage Read/Write Operation: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV) Fast Read Access Time 70 ns Internal Erase/Program Control Sector Architecture One 8K Word (16K Bytes) Boot Block with
More informationTSC695. Application Note. Annulled Cycle Management on the TSC695. References
Annulled Cycle Management on the TSC695 The aim of this application note is to provide TSC695 users with an overview of the annulled cycle management on the TSC695 processor. The indication of annulled
More informationDatasheetDirect.com. Visit to get your free datasheets. This datasheet has been downloaded by
DatasheetDirect.com Your dedicated source for free downloadable datasheets. Over one million datasheets Optimized search function Rapid quote option Free unlimited downloads Visit www.datasheetdirect.com
More information256 (32K x 8) High-speed Parallel EEPROM AT28HC256
Features Fast Read Access Time 70 ns Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control Timer Fast Write Cycle Times Page Write Cycle Time: 3 ms or 10 ms Maximum
More information256K (32K x 8) Paged Parallel EEPROMs AT28C256. Features. Description
Features Fast Read Access Time - 150 ns Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control Timer Fast Write Cycle Times Page Write Cycle Time: 3 ms or 10 ms
More information1-megabit (128K x 8) 5-volt Only Flash Memory AT29C010A
Features Fast Read Access Time 70 ns 5-volt Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 1024 Sectors (128 Bytes/Sector) Internal Address and Data Latches for
More informationTSSOP CLK/IN IN IN IN IN IN IN 19 I/O I/O I/O IN IN IN IN GND. TSSOP is the smallest package of SPLD offering. DIP/SOIC CLK/IN VCC I/O
Features 3.0V to 5.5V Operating Range Lowest Power in It Class Advanced Low-voltage, Zero-power, Electrically Erasable Programmable Logic Device Zero Standby Power (25 µa Maximum) (Input Transition Detection)
More informationAT45DB Megabit 2.7-Volt Only Serial DataFlash AT45DB041. Features. Description. Pin Configurations
Features Single 2.7V - 3.6V Supply Serial Interface Architecture Page Program Operation Single Cycle Reprogram (Erase and Program) 2048 Pages (264 Bytes/Page) Main Memory Two 264-Byte Data Buffers - Allows
More informationAT91 ARM Thumb Microcontrollers. Application Note. AT91M55800A Clock Switching Considerations using Advanced Power Management Controller.
AT91M55800A Clock Switching Considerations using Advanced Power Management Controller Introduction The AT91M55800A is designed for ultra low-power applications and features an Advanced Power Management
More information2-megabit (256K x 8) 5-volt Only Flash Memory AT29C020
Features Fast Read Access Time 70 ns 5-volt Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 1024 Sectors (256 Bytes/Sector) Internal Address and Data Latches for
More information8-megabit (1M x 8/ 512K x 16) Flash Memory AT49BV008A AT49BV008AT AT49BV8192A AT49BV8192AT AT49LV8192A
Features Single-voltage Read/Write Operation: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV) Fast Read Access Time 90 ns Internal Erase/Program Control Sector Architecture One 8K Word (16K Bytes) Boot Block with
More information2-megabit 5-volt Only Serial DataFlash AT45D021A
Features 100% Compatible to AT45D021 Single 4.5V - 5.5V Supply Serial Interface Architecture Page Program Operation Single Cycle Reprogram (Erase and Program) 1024 Pages (264 Bytes/Page) Main Memory Optional
More information32-megabit 2.7-volt Only Serial DataFlash AT45DB321B
Features 100% Compatible to AT45DB321 Single 2.7V - 3.6V Supply Serial Interface Architecture Page Program Operation Single Cycle Reprogram (Erase and Program) 8192 Pages (528 Bytes/Page) Main Memory Optional
More information1-megabit (128K x 8) 5-volt Only Flash Memory AT49F001A AT49F001AN AT49F001AT AT49F001ANT. Features. Description. Pin Configurations
Features Single-voltage Operation 5V Read 5V Reprogramming Fast Read Access Time 45 ns Internal Program Control and Timer Sector Architecture One 16K Bytes Boot Block with Programming Lockout Two 8K Bytes
More informationSection 1 ATAVRAUTOEK1 Getting Started
Section 1 ATAVRAUTOEK1 Getting Started 1.1 Unpacking the system Kit contents: 1 ATAVRAUTO100 V1.0 board 1 ATAVRAUTO102 V1.0 board 1 ATAVRAUTO200 V1.0 board 1 ATAVRAUTO300 V1.0 board 1 ATAVRAUTO900 V1.0
More informationDIP Top View * RESET A16 A15 A12 VCC A17 A14 A13 A8 A9 A11 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 A10 I/O7 I/O6 I/O5 I/O4 I/O3 I/O1 I/O2 GND
Features Single-voltage Operation 5V Read 5V Reprogramming Fast Read Access Time 55 ns Internal Program Control and Timer Sector Architecture One 16K Bytes Boot Block with Programming Lockout Two 8K Bytes
More informationAT89C5131 Starter Kit... Software User Guide
AT89C5131 Starter Kit... Software User Guide Table of Contents Section 1 Introduction... 1-1 1.1 Abbreviations...1-1 Section 2 Getting Started... 2-3 2.1 Hardware Requirements...2-3 2.2 Software Requirements...2-3
More information4-megabit (512K x 8) 3-volt Only 256-byte Sector Flash Memory AT29LV040A
Features Single Voltage, Range 3V to 3.6V Supply 3-volt Only Read and Write Operation Software Protected Programming Fast Read Access Time 150 ns Low Power Dissipation 15 ma Active Current 40 µa CMOS Standby
More informationSPI Serial. Electrically Erasable and Programmable Read-only Memory
Features Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) Data Sheet Describes Mode 0 Operation Low-voltage and Standard-voltage Operation 1.8 (V CC = 1.8V to.v) 0MHz
More information1-megabit (128K x 8) Single 2.7-volt. Flash Memory AT49BV001A AT49BV001AN AT49BV001AT AT49BV001ANT. Battery-Voltage. Features.
Features Single Supply for Read and Write: 2.7 to 3.6V Fast Read Access Time 55 ns Internal Program Control and Timer Sector Architecture One 16K Bytes Boot Block with Programming Lockout Two 8K Bytes
More informationhex file. The example described in this application note is written for the AT94K using the FPSLIC Starter Kit. Creating a New Project
Getting Started with C for the Family Using the IAR Compiler Features How to Open a New Project Description of Option Settings Linker Command File Examples Writing and Compiling the C Code How to Load
More informationISSI Preliminary Information January 2006
2K-BIT/4K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM January 2006 FEATURES Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) Low-voltage Operation Vcc = 1.8V to 5.5V Low
More informationDIP Top View VCC RESET A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND A14 A13 A8 A9 A11 A10 I/O7 I/O6 I/O5 I/O4 I/O3
Features Single Supply for Read and Write: 2.7 to 3.6V (BV), 3.0 to 3.6V (LV) Fast Read Access Time - 70 ns Internal Program Control and Timer Sector Architecture One 16K Byte Boot Block with Programming
More information8-bit Microcontroller. Application Note. AVR031: Getting Started with ImageCraft C for AVR
AVR031: Getting Started with ImageCraft C for AVR Features How to Open a New Project Description of Option Settings Writing and Compiling the C Code How to Load the Executable File into the STK200 Starter
More informationFPGA Configuration EEPROM Memory AT17C65A AT17LV65A AT17C128A AT17LV128A AT17C256A AT17LV256A
Features Serial EEPROM Family for Configuring Altera FLEX Devices In-System Programmable via 2-wire Bus Simple Interface to SRAM FPGAs EE Programmable 64K, 128K and 256K Bits Serial Memories Designed to
More informationAT89STK-09 Starter Kit for AT83C26... User Guide
AT89STK-09 Starter Kit for AT83C26... User Guide Section 1 Introduction... 1-2 1.1 Acronyms...1-2 1.2 Features...1-2 Section 2 Hardware... 2-6 2.1 Power Supply...2-6 2.2 Jumper Configuration...2-6 2.3
More informationGT25C256 SPI. 256K Bits. Serial EEPROM
GT25C256 SPI 256K Bits Serial EEPROM Copyright 2013 Giantec Semiconductor Inc. (Giantec). All rights reserved. Giantec reserves the right to make changes to this specification and its products at any time
More informationFPGA Configuration EEPROM Memory AT17C65 AT17LV65 AT17C128 AT17LV128 AT17C256 AT17LV256
Features EE Programmable 65,536 x 1-, 131,072 x 1-, and 262,144 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) In-System Programmable via 2-wire
More informationCAN Microcontrollers. Application Note. Migrating from T89C51CC01 to AT89C51CC03. Feature Comparison
Migrating from T89C51CC01 to AT89C51CC03 This application note is a guide to assist T89C51CC01 users in converting existing designs to the AT89C51CC03 devices. In addition to the functional changes, the
More information2-wire Serial EEPROM AT24C01A AT24C02 AT24C04 AT24C08 (1) AT24C16 (2) Features. Description. Pin Configurations. 1K (128 x 8) 2K (256 x 8)
Features Low-voltage and Standard-voltage Operation 2.7 (V CC = 2.7V to 5.5V) 1.8 (V CC = 1.8V to 5.5V) Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K) 2-wire
More informationMARC4. Application Note. Hints and Tips for Hard- and Software Developments with MARC4 Microcontrollers
Hints and Tips for Hard- and Software Developments with MARC4 Microcontrollers Programming Hints Use of the SLEEP Instruction Oscillator Selection Access to Subport Registers Access to AU Registers Unused
More informationAT17(A) Series FPGA Configuration Memory. Application Note
Cascaded Programming Circuits using AT1(A) Configurators with Atmel, Xilinx and Altera FPGAs Atmel AT1A (1) series configurators use a simple serial-access procedure to configure one or more Field Programmable
More informationTSSOP CLK/IN IN IN IN IN IN IN IN IN IN IN GND VCC IN I/O I/O I/O I/O I/O I/O I/O I/O IN OE/IN CLK/IN 1 VCC
* Features Industry Standard Architecture Emulates Many 24-pin PALs Low-cost Easy-to-use Software Tools High-speed Electrically-erasable Programmable Logic Devices 7.5 ns Maximum Pin-to-pin Delay Several
More information8-bit Microcontroller. Application Note. AVR320: Software SPI Master
AVR320: Software SPI Master Features Up to 444Kb/S Throughput @ 10 MHz Directly Supports Large Block Writes Easily Expandable for Multiple SPI Slaves Operates in SPI Mode 0 16-bit Data, Easily Modified
More information4-megabit (512K x 8) Single 2.7-volt Battery-Voltage Flash Memory AT49BV040A
Features Single Supply for Read and Write: 2.7 to 3.6V Fast Read Access Time 70 ns Internal Program Control and Timer Sector Architecture One 16K Bytes Boot Block with Programming Lockout Two 8K Bytes
More informationAVR32 UC3 Software Framework... User Manual
... User Manual Section 1 AVR32 UC3 Software Framework 1.1 Features Drivers for each AVR 32 UC3 peripheral Software libraries optimized for AVR32 Hardware components drivers Demo applications that use
More information512K (64K x 8) 5-volt Only Flash Memory AT49F512
Features Single Voltage Operation 5V Read 5V Reprogramming Fast Read Access Time 55 ns Internal Program Control and Timer 8K Bytes Boot Block With Lockout Fast Erase Cycle Time 10 Seconds Byte-by-byte
More information