These three counters can be programmed for either binary or BCD count.

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1 S5 KTU 1 PROGRAMMABLE TIMER 8254/8253 The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for microprocessors to perform timing and counting functions using three 16-bit registers. Each counter has 2 input pins, i.e. Clock & Gate, and 1 pin for OUT output. To operate a counter, a 16-bit count is loaded in its register. Features of 8253 / 54 The most prominent features of 8253/54 are as follows It has three independent 16-bit down counters. It can handle inputs from DC to 10 MHz. These three counters can be programmed for either binary or BCD count. It is compatible with almost all microprocessors has a powerful command called READ BACK command, which allows the user to check the count value, the programmed mode, the current mode, and the current status of the counter Architecture In the figure, there are three counters, a data bus buffer, Read/Write control logic, and a control register. Each counter has two input signals - CLOCK & GATE, and one output signal - OUT. Data Bus Buffer It is a tri-state, bi-directional, 8-bit buffer, which is used to interface the 8253/54 to the system data bus. It has three basic functions Programming the modes of 8253/54. Loading the count registers. Reading the count values. Read/Write Logic It includes 5 signals, i.e. RD, WR, CS, and the address lines A 0 & A 1. In the peripheral I/O mode, the RD and WR signals are connected to IOR and IOW, respectively. In the memory mapped I/O mode, these are connected to MEMR and MEMW. 8254/53 Module 6

2 S5 KTU 2 Address lines A 0 & A 1 of the CPU are connected to lines A 0 and A 1 of the 8253/54, and CS is tied to a decoded address. The control word register and counters are selected according to the signals on lines A 0 & A Pin Description Here is the pin diagram of /53 Module 6

3 S5 KTU 3 Pin functions A0, A1: The address inputs select one of the four internal registers within the A1 A0 Function 0 0 Counter Counter Counter Control Word D0-D7: Bidirectional three state data bus lines connected to system data bus. CLK : The clock input is the timing source for each of the internal counters. This input is often connected to the PCLK signal from the microprocessor system bus controller. CLK0 Clock input of counter 0 CLK1 Clock input of counter 1 CLK2 Clock input of counter 2 OUT: A counter output is where the waveform generated by the counter is available. OUT 0 Output of counter 0 OUT 1 Output of counter 1 OUT 2 Output of counter 2 : Read causes data to be read from the 8254 and often connected to the signal. : Write causes data to be written to the 8254 and often connects to the write strobe ( ) 8254/53 Module 6

4 S5 KTU 4 : Chip select enables the 254 for programming and for reading or writing a counter. Vcc: Power connects to the +5V power supply. GND: Ground connects to the system ground bus GATE : The gate input controls the operation of the counter in some modes of operation. GATE 0 Gate input of counter 0 GATE 1 Gate input of counter 1 GATE 2 Gate input of counter 2 Control Word Format 8254 Write operation 8254/53 Module 6

5 S5 KTU 5 For each Counter, the Control Word must be written before the initial count is written. The initial count must follow the count format specified in the Control Word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). With a clock and an appropriate gate signal to one of the counters, the above steps should start the counter and provide appropriate output according to the control word Read Operations There are three possible methods for reading the counters: A simple read operation The Counter Latch Command, and The Read-Back Command. This operation read the counter after stopping. To read the Counter, which is selected with the A1, A0 inputs, the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic. Two I/O read operation are performed by the MPU. The first I/O operation reads the low order byte. The second I/O operation reads high order byte. Simple Read Operation Counter Latch Command This allows reading the contents of the Counters on running without affecting counting in progress. The selected Counter's output latch (OL) latches the count at the time the Counter Latch Command is received. Counter Latch Commands do not affect the programmed Mode of the Counter in any way 8254/53 Module 6

6 S5 KTU 6 Fig: Counter Latching Command Format Read-Back Command This command is used to read several counters at a time. It eliminates the need of writing separate counter-latch commands for different counters. It allows the user to check the count value, programmed Mode, and current states of the OUT pin and Null Count flag of the selected counter/ counters. The read back command is written to the Control Word Register. 8254/53 Module 6

7 S5 KTU 7 The command is written into the Control Word Register and has the format shown in Figure. The read-back command may be used to latch multiple counter output latches (OL) by setting the COUNT bit D5 =0 and selecting the desired counter(s). Each counter's latched count is held in the output latches (OL )until it is read (or the counter is reprogrammed). The read-back command may also be used to latch status information of selected counter(s) by setting STATUS bit D4 = 0. Status must be latched to be read; status of a counter is accessed by a read from that counter. The counter status format is shown in Figure below. Bit D7 D6 D5,D4 D3,D2,D1 D0 Description Level of output Pin 1 indicate that the counter value is zero Status of read write operation 01 read/write LSB only 10 - read/write MSB only 11 - read/write LSB first and then MSB Modes of operation Type of counter 1-BCD and 0- binary 8254/53 Module 6

8 S5 KTU 8 OUTPUT bit D7 contains the current state of the OUT pin. This allows the user to monitor the counter's output via software, possibly eliminating some hardware from a system. Modes of Operation Mode 0: Interrupt on terminal count. Mode 1: Hardware Retriggerable One-Shot. Mode 2: Rate Generator. Mode 3: Square Wave Mode. Mode 4: Software Triggered Mode. Mode 5: Hardware Triggered Mode Mode 0: Interrupt on terminal count. Mode 0 is typically used for event counting. After the Control Word is written, OUT is initially low, and will remain low until the Counter reaches zero. OUT then goes high and remains high until a new count or a new Mode 0 Control Word is written into the Counter. After the Control Word and initial count are written to a Counter, the initial count will be loaded on the next CLK pulse. This CLK pulse does not decrement the count, so for an initial count of N, OUT does not go high until N +1 CLK pulses after the initial count is written. GATE =1 enables counting; GATE = 0 disables counting. 8254/53 Module 6

9 S5 KTU 9 GATE has no effect on OUT. If G becomes a logic 0 in the middle of the count, the counter will remain stop until G again becomes a logic 1. If a new count is written to the Counter, it will be loaded on the next CLK pulse and counting will continue from the new count Mode 1: Hardware Retriggerable One-Shot. Causes the counter to function as a retriggerable, monostable multivibrator (one-shot). OUT is initially (after loading CW) high. Also remain high when count is written. When gate is triggered, OUT goes low and will remain low until the Counter reaches zero. On completion of count OUT goes high again. If the GATE input occurs within the duration of counting, the counter is again reloaded with the count and start counting from the beginning. At the rising edge of WR(CW) OUT becomes high. 8254/53 Module 6

10 S5 KTU 10 At the first falling edge of clock after first rising edge of GATE counter starts counting. Mode 2: Rate Generator Allows the counter to generate a series of continuous pulses that are one clock pulse wide. The separation between pulses is determined by the count. If count N is loaded then, output will remain high for (N-1) clock period and low for 1 clock period. For example, for a count of 10, the output is a logic 1 for nine clock period and low for 1 clock period. This cycle is repeated until the counter is programmed with a new count or until G pin is placed at a logic 0 level. 8254/53 Module 6

11 S5 KTU 11 The Gate input must be logic 1 for this mode to generate a continuous series of pulses. In mode 2, a COUNT of 1 is illegal. Mode 3: Square Wave Mode. Generates a continuous square wave at the out connection. Mode 3 is similar to Mode 2 except for the duty cycle of OUT. 8254/53 Module 6

12 S5 KTU 12 If the count (N) is even, the output is high for one half (N/2) of the count and low for one half (N/2) of the count. If the count (N) is odd, the output is high for one clocking period longer than it is low i.e. high for (N+1)/2 clock pulses and low for (N-1)/2 clock pulses. For example, if the count is programmed for a count of 5, the output is high for three clocks and low for two clocks. Gate should be maintained at logic 1 always (GATE =1 enables counting; GATE =0 disables counting. If GATE goes low while OUT is low, OUT is set high immediately; no CLK pulse is required). Mode 4: Software Triggered One-shot. Allows the counter to produce a single pulse at the output. If count of N is loaded, then OUT will be high for N clock cycles and low for one clock cycle at the end. The cycle does not begin until the counter is loaded again. 8254/53 Module 6

13 S5 KTU 13 Mode 5: Hardware Triggered Mode. A hardware triggered one-shot that function as mode 4, except that it is started by a trigger pulse on the G pin instead of by software. When the GATE pulse is triggered from low to high the count begins. At the end of the count OUT goes low for one clock period. This mode is also called hardware triggered strobe (retriggerable) 8254/53 Module 6

14 Introduction Interrupt is one of the most important features in the microcontroller/processor applications. Consider a microprocessor system receiving data and change in status from I/O port or device. There are two methods available to obtain input: Polling & Interrupts. In INTERRUPT method, whenever any device needs service from microprocessor, the device notifies to processor by sending signal called interrupt. Upon receiving an interrupt signal, the microprocessor holds whatever it is doing and serves the corresponding device. The program associated with the interrupt is called the interrupt service routine (ISR) or interrupt handler. In POLLING method, the microprocessor continuously monitors the status of a given device; when the status condition is met, it performs the service. After that, it moves on to the next device until each one is serviced. Although polling can monitor the status of several devices and serve each of them if certain conditions are met.. Interrupt An INTERRUPT is a condition that causes the microprocessor to temporarily work on a different task and then return to its previous task. Interrupt is an event or signal that request to attention of CPU. Whenever an interrupt occurs the processor completes the execution of the current instruction and starts the execution of an Interrupt Service Routine (ISR) or Interrupt Handler. ISR is a program that tells the processor what to do when the interrupt occurs. After the execution of ISR, control returns back to the main routine where it was interrupted. Whenever an interrupt is occurred, it will be acknowledged by the processor at the end of the current memory cycle. The processor then services the interrupt by branching to a special service routine written to handle that particular interrupt. Upon servicing the device, the processor is then instructed to continue with what it was doing previously by use of the IRET (return from interrupt) instruction.. S5 1 KTU

15 The status of the program being executed must be saved first. The processors registers and the program counter will be saved on the stack. Preserving those registers which are not saved will be the responsibility of the interrupt service routine. Once the program counter has been saved, the processor will branch to the address of the service routine. Figure: Interrupt processing flow Purpose of Interrupts The Microprocessor can serve several devices. There are two ways to offer service: Interrupts and Polling. S5 2 KTU

16 The advantage of interrupts is that the microprocessor can serve many devices (not all at the same time, of course); each device can get the attention of the microprocessor based on the priority assigned to it. The polling method cannot assign priority because it checks all devices in a round-robin fashion. More importantly, in the interrupt method the microprocessor can also ignore (mask) a device request for service. This is not possible with the polling method. The most important reason that the interrupt method is preferable is that the polling method wastes much of the microprocessor s time by polling devices that do not need service. So interrupts are used to avoid tying down the microprocessor. Consider this example. The polling method is very much similar to a salesperson. The salesman goes door-to-door requesting to buy his product. Like processor keeps monitoring the flags or signals one by one for all devices. Interrupt is very similar to a shopkeeper. Whosever needs a service or product goes to him and approaches him. Like, when the flags or signals are received, they notify the processor that they need its service.. Interrupts are useful when interfacing I/O devices with low data-transfer rates, like a keyboard or a mouse, in which case polling the device wastes valuable processing time Above time line shows typing on a keyboard, a printer removing data from memory, and a program executing. The keyboard interrupt service procedure, called by the keyboard interrupt, and the printer interrupt service procedure each take little time to execute. S5 3 KTU

17 Sources of Interrupts in 8086 In general there are two types of Interrupts: Internal (or) Software Interrupts are triggered by a software instruction and operate similarly to a jump or branch instruction. External (or) Hardware Interrupts are caused by an external hardware module. An interrupt in 8086 can come from one of the following three sources. 1. HARDWARE INTERRUPTS One source is from an external signal applied to NMI or INTR input pin of the processor. The interrupts initiated by applying appropriate signals to these input pins are called hardware interrupts. Hardware interrupts are generated by hardware devices when something unusual happens; this could be a key-press or a mouse move or any other action. Maskable Interrupts : The processor can inhibit certain types of interrupts by use of a special interrupt mask bit. This mask bit is part of the flags/condition code register, or a special interrupt register. In the 8086 microprocessor if this bit is clear, and an interrupt request occurs on the Interrupt Request input, it is ignored. Non-Maskable Interrupts: There are some interrupts which cannot be masked out or ignored by the processor. These are associated with high priority tasks which cannot be ignored (like memory parity or bus faults). In general, most processors support the Non-Maskable Interrupt (NMI). This interrupt has absolute priority, and when it occurs, the processor will finish the S5 4 KTU

18 current memory cycle, then branch to a special routine written to handle the interrupt request. 2. SOFTWARE INTERRUPTS A second source of an interrupt is execution of the interrupt instruction "INT n", where n is the type number. The interrupts initiated by "INT n" instructions are called software interrupts. Examples: DOS INT 21H, BIOS INT 10H. INT 00 (divide error) INT 01 (single step) INT 03 (breakpoint) INT 04 (overflow) 3. The third source of an interrupt is from some condition produced in the 8086 by the execution of an instruction. An example of this type of interrupt is divide by zero interrupt. Program execution will be automatically interrupted if you attempt to divide an operand by zero. Such conditional interrupts are also known as exceptions. Interrupt Service Routine For every interrupt, there must be an interrupt service routine (ISR), or interrupt handler. When an interrupt is invoked, the microprocessor runs the interrupt service routine. For every interrupt, there is a fixed location in memory that holds the address of its ISR. The group of memory locations set aside to hold the addresses of ISRs is called the interrupt vector table. When an interrupt is occurred, the microprocessor stops execution of current instruction. It transfers the content of program counter into stack. It also stores the current status of the interrupts internally but not on stack. After this, it jumps to the memory location specified by Interrupt Vector Table (IVT). After that the code written on that memory area will execute. Interrupt Vector Table The first 1Kbyte of memory of 8086 (00000 to003ff) is set aside as a table for storing the starting addresses of Interrupt Service Procedures(ISP).Since 4-bytes are required for storing starting addresses of ISPs, the table can hold 256 Interrupt procedures. The starting address of an S5 5 KTU

19 ISP is often called the Interrupt Vector or Interrupt Pointer. Therefore the table is referred as Interrupt Vector Table. In this table, IP value is put in as low word of the vector & CS is put in high vector Interrupts An 8086 interrupt can come from any one of three sources. 1. An external signal applied to the non-maskable interrupt (NMI) input pin or to the interrupt input pin (HARDWARE INTERRUPT). 2. Execution of the interrupt instruction (SOFTWARE INTERRUPT) 3. Some error condition produced in the 8086 by the execution of an instruction. S5 6 KTU

20 Example:If you attempt to divide an operand by zero, the 8086 will automatically interrupt the currently executing program. At the end of each instruction cycle, the 8086 checks to see if any interrupts have been requested. If an interrupt has been requested, the 8086 responds to the interrupt by stepping through the following series of major actions: It decrements the stack pointer by 2 and pushes the flag register on the stack. It disables the 8086 INTR interrupt input by clearing the interrupt flag in the flag register. It resets the trap flag in the flag register. It decrements the stack pointer by 2 and pushes the current code segment register contents on the stack. It decrements the stack pointer again by 2 and pushes the current instruction pointer contents on the stack. The processor fetches the ISR address Divide-By-Zero Interrupt-Type 0: The 8086 will automatically do a type 0 interrupt if the result of a DIV operation or an IDIV operation is too large to fit in the destination register. For a type 0 interrupt, the 8086 pushes the flag register on the stack, resets IF and TF and pushes the return addresses on the stack. Single Step Interrupt-Type 1: The use of single step execution feature is found in some of the monitor & debugger programs. When we tell a system to single step, it will execute one instruction and stop. We can then examine the contents of registers and memory locations. In other words, when in single step mode a system will stop after it executes each instruction and wait for further direction from user. The 8086 trap flag and type 1 interrupt response make it quite easy to implement a single step feature direction. Non-maskable Interrupt-Type 2: The 8086 will automatically do a type 2 interrupt response when it receives a low to high transition on its NMI pin. When it does a type 2 interrupt, the 8086 will push the flags on the stack, reset TF and IF, and push the CS value and the IP value for the next instruction on the stack. It will then get the CS value for the start of the type 2 interrupt service procedure from address 0000AH and the IP value for the start of the procedure from address 00008H. S5 7 KTU

21 Breakpoint Interrupt-Type 3: The type 3 interrupt is produced by execution of the INT3 instruction. The main use of the type 3 interrupt is to implement a breakpoint function in a system. Unlike the single-step feature which stops execution after each instruction, the breakpoint feature executes all the instructions up to the inserted breakpoint and then stops execution. The mnemonic for the instruction is INT3. Whenever we insert a breakpoint, the system executes the instructions up to the breakpoint and then goes to the breakpoint procedure. The execution of INT3 instruction results in the following. 1. Flag register value is pushed on to the Stack. 2. CS value of the return address and IP value of the return address are pushed onto the Stack. 3. IP is loaded from the contents of the word location 3x4 = 0000CH. 4. CS is loaded from the contents of the next word location. 5. Interrupt Flag and Trap Flag are reset to 0. Overflow Interrupt-Type4: The 8086 overflow flag will be set if the signed result of an arithmetic operation on two signed numbers is too large to be represented in the destination register or memory location. There are two ways to detect and respond to an overflow error in a program. One way is to put the jump if overflow instruction, JO, immediately after the arithmetic instruction. If the overflow flag is Set, execution will jump to the address specified in the JO instruction. At this address an error routine may be put which respond to the overflow. The second way is to put them INTO instruction immediately after the arithmetic Instruction in the program. The mnemonic for the instruction is INTO. Example: If we add the 8 bit signed number and the 8 bit signed number , the result will be This would be the correct result if we were adding unsigned binary numbers, but it is not the correct signed result. 1.Flag register values are pushed on to the Stack. S5 8 KTU

22 2. CS value of the return address and IP value of the return address and IP value of the return address are pushed on to the stack. 3. IP is loaded from the contents of word location 4x4 = 00010H. 4. CS is loaded from the contents of next word location. 5. Interrupt flag and Trap flag are reset to 0. Software Interrupts-Type O through 255: The 8086 INT instruction can be used to trigger the 8086 to do any one of the 256 possible interrupt types. The desired interrupt type is specified as part of the instruction. The instruction INT32, for example will cause the 8086 to do a type 32 interrupt response. The 8086 will push the flag register on the stack, reset TF and IF, and push the CS and IP values of the next instruction on the stack. INTR Interrupts-Types 0 through 255: The 8086 INTR input allows some external signal to interrupt execution of a program. Unlike the NMI input, however, INTR can be masked so that it cannot cause an interrupt. If the interrupt flag is cleared, then the INTR input is disabled. IF can be cleared at any time with CLEAR instruction. Figure: 8086 Interrupt Instructions. S5 9 KTU

23 Interrupt Priority If two or more interrupts occur at the same time then the highest priority interrupt will be serviced first, and then the next highest priority interrupt will be serviced. Example: If suppose that the INTR input is enabled, the 8086 receives an INTR signal during the execution of a divide instruction, and the divide operation produces a divide by zero interrupt. Since the internal interrupts-such as divide error, INT, and INTO have higher priority than INTR the 8086 will do a divide error interrupt response first. The interrupt that has a lower address, has a higher priority. For example, the address of external interrupt 0 is 2, while the address of external interrupt 2 is 6; thus, external interrupt 0 has a higher priority, and if both of these interrupts are activated at the same time, extern al interrupt 0 is served first Interrupt Pins and Timing INTR: Interrupt Request. Activated by a peripheral device to interrupt the processor. o Level triggered. Activated with a logic 1. INTA: Interrupt Acknowledge. Activated by the processor to inform the interrupting device the interrupt request (INTR) is accepted. o Level triggered. Activated with a logic 0. NMI: Non-Maskable Interrupt. Used for major system faults such as parity errors and power failures. o o o o Edge triggered. Activated with a positive edge (0 to 1) transition. Must remain at logic 1, until it is accepted by the processor. Before the 0 to 1 transition, NMI must be at logic 0 for at least 2 clock cycles. No need for interrupt acknowledgement. S5 10 KTU

24 INTEL 8259A Programmable Interrupt Controller The 8259A is a programmable interrupt controller designed to work with Intel microprocessors like 8085, 8086 etc The 8259 A interrupt controller can : 1) Handle eight interrupt inputs. This is equivalent to providing eight interrupt pins on the processor in place of one INTR/INT pin. 2) Vector an interrupt request anywhere in the memory map. However, all the eight interrupt are spaced at the interval of either four or eight location. This eliminates the major drawback, 8085 interrupt, in which all interrupts are vectored to memory location on page 00H. 3) Resolve eight levels of interrupt priorities in a variety of modes. 4) Mask each interrupt request individually. 5) Read the status of pending interrupts, in service interrupts, and masked interrupts. 6) Be set up to accept either the level triggered or edge triggered interrupt request. 7) 8259 as can be cascade in a master slave configuration to handle 64 interrupt inputs. The 8259 A is contained in a 28-element in line package that requires only a compatible with The main difference between the two is that the 8259 A can be used with Intel 8086/8088 processor. It also induces additional features such as level triggered mode, buffered mode and automatic end of interrupt mode. The pin diagram and interval block diagram is shown below: S5 11 KTU

25 The pins are defined as follows: CS: Chip select To access this chip,cs is made low. A LOW on this pin enables RD & WR communication between the CPU and the 8259A. This pin is connected to address bus through the decoder logic circuits. INTA functions are independent of CS. WR : A low on this pin. When CS is low enables the 8259 A to accept command words from CPU. RD :A low on this pin when CS is low enables these 8259 A to release status on to the data bus for the CPU. D7-D0:Bidirectional data bus used to transfer commands to 8259 and read status of This bus is connected to bidirectional data bus of S5 12 KTU

26 CAS0-CAS2: Cascade lines: The CAS lines form a private 8259A bus to control a multiple 8259A structure ie to identify a particular slave device. These pins are outputs of a master 8259A and inputs for a slave 8259A. : Salve program/enable buffer: This is a dual function pin. It is used as an input to determine whether the 8259A is to a master ( = 1) or as a slave ( = 0). It is also used as an output to disable the data bus transceivers when data are being transferred from the 8259A to the CPU. When in buffered mode, it can be used as an output and when not in the buffered mode it is used as an input. INT: This pin goes high whenever a valid interrupt request is asserted. It is used to interrupt the CPU, thus it is connected to the CPU s interrupt pin (INTR). Interrupt Acknowledge. This pin is used to enable 8259A interrupt vector data on the data bus by a sequence of interrupt request pulses issued by the CPU. IR0-IR7:Interrupt Requests: Asynchronous interrupt inputs. An interrupt request is executed by raising an IR input (low to high), and holding it high until it is acknowledged. (Edge triggered mode). A0: A0 address line: This pin acts in conjunction with the RD, WR & CS pins. It is used by the 8259A to send various command words from the CPU and to read the status. If is connected to the CPU A0 address line. Two addresses must be reserved in the I/O address space for each 8259 in the system. S5 13 KTU

27 Functional Description: The 8259 A has eight interrupt request inputs, TR2 IR0. The 8259 A uses its INT output to interrupt the 8085A via INTR pin. The 8259A receives interrupt acknowledge pulses from the microprocessor at its INTA input. Vector address used by the 8086 A to transfer control to the service subroutine of the interrupting device, is provided by the 8259 A on the data bus. The 8259A is a programmable device that must be initialized by command words sent by the After initialization the 8259 A mode of operation can be changed by operation command words from the The descriptions of various blocks are, Data bus buffer: This 3- state, bidirectional 8-bit buffer is used to interface the 8259A to the system data bus. Control words and status information are transferred through the data bus buffer. S5 14 KTU

28 Read/Write & control logic: The function of this block is to accept OUTPUT commands from the CPU. It contains the initialization command word (ICW) register and operation command word (OCW) register which store the various control formats for device operation. This function block also allows the status of 8159A to be transferred to the data bus. Interrupt request register (IRR): IRR stores all the interrupt inputs that are requesting service.basically, it keeps track of which interrupt inputs are asking for service. If an interrupt input is unmasked, and has an interrupt signal on it, then the corresponding bit in the IRR will be set. Interrupt mask register (IMR): The IMR is used to disable (Mask) or enable (Unmask) individual interrupt inputs. Each bit in this register corresponds to the interrupt input with the same number. The IMR operation on the IRR. Masking of higher priority input will not affect the interrupt request lines of lower priority. To unmask any interrupt the corresponding bit is set 0. In service register (ISR): The in service registers keeps tracks of which interrupt inputs are currently being serviced. For each input that is currently being serviced the corresponding bit will be set in the in service register.each of these 3-reg can be read as status reg. Priority Resolver: This logic block determines the priorities of the set in the IRR. The highest priority is selected and strobed into the corresponding bit of the ISR during pulse. Cascade buffer/comparator: This function blocks stores and compare the IDS of all 8259A s in the reg. The associated 3-I/O pins (CAS0-CAS2) are outputs when 8259A is used a master. Master and are inputs when 8259A is used as a slave. As a master, the 8259A sends the ID of the interrupting slave device onto the S5 15 KTU

29 cas2-cas0. The slave thus selected will send its pre-programmed subroutine address on to the data bus during the next one or two successive pulses. S5 16 KTU

30 Question Bank 1. Define interrupt. 2. Define Interrupt service routine 3. Define interrupt vector table. 4. Explain different types of interrupts in What are the steps followed by 8086 to execute an interrupt service routine? 6. What are the sources of interrupts in Differentiate between polling and interrupt 8. Differentiate between hardware interrupts and software interrupts. 9. Define the following i. YPE 0 Interrupt. ii. TYPE 1 Interrupt iii. TYPE 2 Interrupt iv. TYPE 3 Interrupt v. TYPE 4 Interrupt 10. Explain the block diagram of 8259 interrupt controller with neat diagram. S5 17 KTU

31 WORK SHEET 1. Define interrupt vector table. 2. Explain different types of interrupts in 8086 S5 18 KTU

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33 3. Define the following i. YPE 0 Interrupt. ii. TYPE 1 Interrupt iii. TYPE 2 Interrupt iv. TYPE 3 Interrupt v. TYPE 4 Interrupt S5 20 KTU

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35 4.Explain the block diagram of 8259 interrupt controller with neat diagram. S5 22 KTU