SoC. CoreSight. Technical Reference Manual. Revision: r1p0. Copyright ARM. All rights reserved. ARM DDI 0480B (ID042612)

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1 CoreSight SoC Revision: r1p0 Technical Reference Manual Copyright ARM. All rights reserved. ARM DDI 0480B ()

2 CoreSight SoC Technical Reference Manual Copyright ARM. All rights reserved. Release Information Change history Date Issue Confidentiality Change 04 November 2011 A First release for r0p0 16 April 2012 B First release for r1p0. Proprietary Notice Words and logos marked with or are registered trademarks or trademarks of ARM in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product. Where the term ARM is used it means ARM or any of its subsidiaries as appropriate. Confidentiality Status This document is. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to. Product Status The information in this document is final, that is for a developed product. Web Address ARM DDI 0480B Copyright ARM. All rights reserved. ii

3 Contents CoreSight SoC Technical Reference Manual Preface About this book... vii Feedback... xi Chapter 1 Chapter 2 Chapter 3 Introduction 1.1 About the CoreSight SoC CoreSight block summary Typical CoreSight debugging environment Product revisions Functional Overview 2.1 DAP components Advanced Trace Bus interconnect components Timestamp components Trigger components Trace sink components Authentication and event bridges Granular Power Requestor (GPR) Programmers Model 3.1 About the programmers model GPR register summary GPR register descriptions APB interconnect register summary APB interconnect register descriptions ATB funnel register summary ATB funnel register descriptions ATB replicator register summary ATB replicator register descriptions ARM DDI 0480B Copyright ARM. All rights reserved. iii

4 3.10 ETB register summary ETB register descriptions CTI register summary CTI register descriptions TPIU register summary TPIU register descriptions DAP register summary DAP register descriptions Timestamp generator register summary Timestamp generator register description Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Debug Access Port 4.1 About the Debug Access Port SWJ-DP JTAG-DP SW-DP DAPBUS interconnect interfaces DAP asynchronous bridge DAP synchronous bridge Common debug port features and registers Access ports JTAG-AP AXI-AP AHB-AP APB-AP APB Interconnect APB asynchronous bridge APB synchronous bridge Auxiliary Access Port Authentication requirements for Debug Access Port Clocks, power, and resets ATB Interconnect Components 5.1 ATB replicator ATB funnel ATB upsizer ATB downsizer ATB asynchronous bridge ATB synchronous bridge Timestamp Components 6.1 About the timestamp components Timestamp solution Embedded Cross Trigger 7.1 About the ECT ECT programmers model ECT connectivity recommendations ECT authentication requirements Trace Port Interface Unit 8.1 About the Trace Port Interface Unit Trace Out Port Miscellaneous connections TPIU trace port sizes TPIU triggers Other TPIU design considerations Authentication requirements for TPIUs TPIU pattern generator ARM DDI 0480B Copyright ARM. All rights reserved. iv

5 8.9 TPIU formatter and FIFO Configuration options Example configuration scenarios Chapter 9 Chapter 10 Appendix A Appendix B Embedded Trace Buffer 9.1 About the ETB ETB clocks, resets, and synchronization ETB trace capture and formatting Flush assertion Triggers Write address generation for trace data storage Trace data storage APB configuration and RAM access Trace RAM Authentication requirements for CoreSight ETBs ETB RAM support Granular Power Requestor 10.1 Granular Power Requestor interfaces Signal Descriptions A.1 Debug Access Port signals... A-2 A.2 Advanced Trace Bus interconnect signals... A-16 A.3 Timestamp component signals... A-23 A.4 Trigger component signals... A-29 A.5 Trace sink signals... A-32 A.6 Authentication and event bridges... A-35 A.7 Granular power requestor signals... A-37 Revisions ARM DDI 0480B Copyright ARM. All rights reserved. v

6 Preface This preface introduces the CoreSight SoC Technical Reference Manual. It contains the following sections: About this book on page vii Feedback on page xi. ARM DDI 0480B Copyright ARM. All rights reserved. vi

7 Preface About this book This is the Technical Reference Manual (TRM) for the CoreSight components. Product revision status The rnpn identifier indicates the revision status of the products described in this book, where: rn Identifies the major revision of the product. pn Identifies the minor revision or modification status of the product. Intended audience This book is written for the following audiences: Hardware and software engineers who want to incorporate a CoreSight SoC into their design and produce real-time instruction and data trace information from an ASIC. Software engineers writing tools to use CoreSight SoC. This book assumes that readers are familiar with AMBA bus design and JTAG methodology. Using this book This book is organized into the following chapters: Chapter 1 Introduction Read this for an overview of the CoreSight components. Chapter 2 Functional Overview Read this for a description of the major functional blocks and the operation of the CoreSight SoC. Chapter 3 Programmers Model Read this for a description of the memory map and registers. Chapter 4 Debug Access Port Read this for a description of the Debug Access Port (DAP) components. Chapter 5 ATB Interconnect Components Read this for a description of the AMBA Trace Bus (ATB) interconnect components. Chapter 6 Timestamp Components Read this for a description of the timestamp components. Chapter 7 Embedded Cross Trigger Read this for a description of the Embedded Cross Trigger (ECT) components. Chapter 8 Trace Port Interface Unit Read this for a description of the Trace Port Interface Unit (TPIU) components. Chapter 9 Embedded Trace Buffer Read this for a description of the Embedded Trace Buffer (ETB) components. Chapter 10 Granular Power Requestor Read this for a description of the Granular Power Requester (GPR) components. ARM DDI 0480B Copyright ARM. All rights reserved. vii

8 Preface Appendix A Signal Descriptions Read this for a description of the CoreSight SoC component signals. Appendix B Revisions Read this for a description of the technical changes between released issues of this book. Glossary The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning. See ARM Glossary, Conventions Conventions that this book can use are described in: Typographical Timing diagrams Signals on page ix. Typographical The typographical conventions are: italic bold monospace monospace monospace italic monospace bold Highlights important notes, introduces special terminology, denotes internal cross-references, and citations. Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate. Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code. Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name. Denotes arguments to monospace text where the argument is to be replaced by a specific value. Denotes language keywords when used outside example code. < and > Enclose replaceable terms for assembler syntax where they appear in code or code fragments. For example: Timing diagrams MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2> The figure named Key to timing diagram conventions on page ix explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams. Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation. ARM DDI 0480B Copyright ARM. All rights reserved. viii

9 Preface Clock HIGH to LOW Transient HIGH/LOW to HIGH Bus stable Bus to high impedance Bus change High impedance to stable bus Key to timing diagram conventions Signals The signal conventions are: Signal level Lower-case n The level of an asserted signal depends on whether the signal is active-high or active-low. Asserted means: HIGH for active-high signals LOW for active-low signals. At the start or end of a signal name denotes an active-low signal. Additional reading This section lists publications by ARM and by third parties. See Infocenter, for access to ARM documentation. ARM publications This document contains information that is specific to the CoreSight components. See the following documents for other relevant information: CoreSight SoC Implementation Guide (ARM DII 0267) CoreSight SoC User Guide (ARM DUI 0563) CoreSight Technology System Design Guide (ARM DGI 0012) CoreSight Architecture Specification (ARM IHI 0029) CoreLink TrustZone Address Space Controller TZC-380 Technical Reference Manual (ARM DDI 0431) AMBA AHB Trace Macrocell (HTM) Technical Reference Manual (ARM DDI 0328) Systems IP ARM11 AMBA (Rev 2.0) AHB Extensions (ARM IHI 0023) AMBA 3 APB Protocol Specification (ARM IHI 0024) ARM Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2 (ARM IHI 0031) ARM DDI 0480B Copyright ARM. All rights reserved. ix

10 Preface Other publications This section lists relevant documents published by third parties: IEEE IEEE Standard Test Access Port and Boundary Scan Architecture (JTAG). ARM DDI 0480B Copyright ARM. All rights reserved. x

11 Preface Feedback ARM welcomes feedback on this product and its documentation. Feedback on this product If you have any comments or suggestions about this product, contact your supplier and give: The product name. The product revision or version. An explanation with as much information as you can provide. Include symptoms and diagnostic procedures if appropriate. Feedback on content If you have comments on content then send an to Give: the title the number, ARM DDI 0480B the page numbers to which your comments apply a concise explanation of your comments. ARM also welcomes general suggestions for additions and improvements. Note ARM tests the PDF only in Adobe Acrobat and Acrobat Reader, and cannot guarantee the quality of the represented document when used with any other PDF reader. ARM DDI 0480B Copyright ARM. All rights reserved. xi

12 Chapter 1 Introduction This chapter introduces the CoreSight SoC. It contains the following sections: About the CoreSight SoC on page 1-2 CoreSight block summary on page 1-4 Typical CoreSight debugging environment on page 1-6 Product revisions on page 1-7. ARM DDI 0480B Copyright ARM. All rights reserved. 1-1

13 Introduction 1.1 About the CoreSight SoC The CoreSight SoC is a set of highly configurable components that you can use to: graphically configure all acceptable configuration options of components build systems that integrate CoreSight SoC components and processors Note You can also integrate other CoreSight components like System Trace Macrocell (STM) and Trace Memory Controller (TMC) that are licensed separately. run the design rule checks to ensure that the configurations match the compliance limitations create a testbench infrastructure to run system-level tests to certify the debug and trace system operation CoreSight SoC features The CoreSight SoC has the following features for system-wide trace: configurability debug and trace visibility of whole systems cross triggering support between SoC subsystems multi-source trace in a single stream higher data compression than previous solutions standard programmers models for standard tools support open interfaces for third-party cores low pin count low silicon overhead Structure of the CoreSight SoC The CoreSight SoC includes the following: Control and access components Configure, access, and control the generation of trace. They do not generate trace, and process the trace data. Examples include: DAP. See Chapter 4 Debug Access Port. Sources Links Sinks Generates trace data for output through the AMBA Trace Bus (ATB). Examples include: AHB Trace Macrocell (HTM), documented separately. See Additional reading on page ix. CoreSight Embedded Trace Macrocells (ETMs), documented separately. See Additional reading on page ix. Provides connection, triggering, and flow of trace data. Examples include: Synchronous 1:1 ATB bridge Replicator Trace funnel. End points for trace data on the SoC. Examples include: TPIU for output of trace data off-chip ARM DDI 0480B Copyright ARM. All rights reserved. 1-2

14 Introduction ETB for on-chip storage of trace data in RAM Serial Wire Output (SWO) for output of System Trace Macrocell (STM) trace through a single pin. ARM DDI 0480B Copyright ARM. All rights reserved. 1-3

15 Introduction 1.2 CoreSight block summary Table 1-1 shows the CoreSight blocks and their current versions. Table 1-1 CoreSight block summary Block name Description Block version Revision in programmers model CSCTI Cross trigger interface r0p4 4 CSCTM Cross trigger matrix r0p3 - CSETB Embedded trace buffer r0p3 3 CXATBREPLICATOR ATB replicator r1p0 1 CXAUTHREPLICATOR Authentication replicator r0p0 - CXEVENTASYNCBRIDGE Event asynchronous bridge r0p0 - CXTSREPLICATOR Timestamp replicator r0p0 - CXATBFUNNEL Trace funnel r2p0 2 CSTPIU Trace port interface unit r0p4 4 CXATBUPSIZER ATB upsizer r0p0 - CXATBDOWNSIZER ATB downsizer r0p0 - CXATBASYNCBRIDGE ATB asynchronous bridge r0p0 - CXATBSYNCBRIDGE ATB synchronous bridge r0p0 - CXAPBASYNCBRIDGE APB asynchronous bridge r0p0 - CXAPBSYNCBRIDGE APB synchronous bridge r0p0 - CXAUTHASYNCBRIDGE Authentication asynchronous bridge r0p0 - CXAUTHSYNCBRIDGE Authentication synchronous bridge r0p0 - CXTSGEN Master timestamp generator r0p0 0 CXTSE Timestamp encoder r0p0 - CXNTSREPLICATOR Narrow timestamp replicator r0p0 - CXNTSASYNCBRIDGE Narrow timestamp asynchronous bridge r0p0 - CXNTSAYNCBRIDGE Narrow timestamp synchronous bridge r0p0 - CXTSD Timestamp decoder r0p0 - Debug Access Port blocks CXDAPAHBAP AHB access port r0p6 6 CXDAPAPBAP APB access port r0p4 4 CXAPBIC APB interconnect r0p0 - CXDAPJTAGAP JTAG access port r0p2 2 CXDAPASYNCBRIDGE DAPBUS asynchronous bridge r0p0 - CXDAPSYNCBRIDGE DAPBUS synchronous bridge r0p0 - ARM DDI 0480B Copyright ARM. All rights reserved. 1-4

16 Introduction Table 1-1 CoreSight block summary (continued) Block name Description Block version Revision in programmers model CXDAPAXIAP AXI access port r0p1 1 CXDAPBUSIC DAPBUS interconnect r0p0 - CXDAPSWJDP Serial wire and JTAG debug port: DAPSWDP DAPJTAGDP - r1p2 r0p5-5 5 Note For blocks with a programmers model, the block version can be checked using the revision field of the identification registers. ARM DDI 0480B Copyright ARM. All rights reserved. 1-5

17 Introduction 1.3 Typical CoreSight debugging environment Figure 1-1 shows an example of CoreSight components in a debugging environment. Bus matrix Cross Trigger Matrix (CTM) JTAG port DAP ARM processor ETM Cross Trigger Interface (CTI) ARM processor ETM CTI DSP ETM DSP CTI HTM Debug APB ATB Trace funnel STM ETF Replicator Replicator SWO ETB TPIU Output port Trace port Figure 1-1 CoreSight debugging environment ARM DDI 0480B Copyright ARM. All rights reserved. 1-6

18 Introduction 1.4 Product revisions This section describes the differences in functionality between product revisions: r0p0 First release. r0p0 - r1p0 Two new components added: Granular Power Requestor Timestamp Interpolator. ARM DDI 0480B Copyright ARM. All rights reserved. 1-7

19 Chapter 2 Functional Overview This chapter introduces the components available for building a CoreSight SoC trace and debug infrastructure. It describes the basic function of each block and its I/O signals. The configurable parameters that affect some block level signals. These are shown so that an accurate pinout is reflected for all signals that are external to the block. This is not an exhaustive list, or description of all available product customizations. See the CoreSight SoC User Guide for full details of all configurable and programmable features. This chapter contains the following sections: DAP components on page 2-2 Advanced Trace Bus interconnect components on page 2-9 Timestamp components on page 2-14 Trigger components on page 2-18 Trace sink components on page 2-20 Authentication and event bridges on page 2-22 Granular Power Requestor (GPR) on page ARM DDI 0480B Copyright ARM. All rights reserved. 2-1

20 Functional Overview 2.1 DAP components The Debug Access Port (DAP) is a sub-system that provides access to various classes of on-chip debug resources. The components that form the DAP are: Serial Wire or JTAG - Debug Port (SWJ-DP) DAP bus interconnect DAP asynchronous bridge on page 2-3 DAP synchronous bridge on page 2-3 JTAG - Access Port on page 2-4 Advanced extensible Interface - Access Port (AXI-AP) on page 2-4 Advanced High-performance Bus - Access Port (AHB-AP) on page 2-5 Advanced Peripheral Bus Access Port (APB-AP) on page 2-6 APB InterConnect (APBIC) with ROM table on page 2-6 APB asynchronous bridge on page 2-7 APB synchronous bridge on page Serial Wire or JTAG - Debug Port (SWJ-DP) The SWJ-DP connects either a Serial Wire Debug or JTAG probe to the CoreSight SoC debug system. This is the entry point into the debug infrastructure from the external debugger through the Debug Port. Figure 2-1 shows the external connections on the SWJ-DP. See Chapter 4 Debug Access Port for more information. Clock and reset JTAG control dapclk dapclken dapresetn jtagnsw jtagtop dapready dapsel dapenable dapwrite dapcaddr[15:2] dapwdata[31:0] dapprdata[31:0] Example master access port Serial Wire and JTAG port SW multidrop swdo swdoen tdo ntdoen ntrst npotrst swclktck swditms tdi targetid[31:0] instanceid[3:0] SWJ-DP dapslverr dapabort cdbgpwrupreq cdbgpwrupack csyspwrupreq csyspwrupack cdbgrstreq cdbgrstack Debug power on request System power on request Debug reset request Figure 2-1 SWJ - DP block diagram DAP bus interconnect The DAPBUS interconnect connects a debug port to a configurable number of access ports. The DAPBUS interconnect operates in a single clock domain. Use asynchronous bridges to connect other components that are not synchronous to the DAPBUS interconnect. The SoC designer must configure the number of master ports within the range The required number of master ports is instantiated and suffixed with an interface number. ARM DDI 0480B Copyright ARM. All rights reserved. 2-2

21 Functional Overview Figure 2-2 shows the external connections on the DAPBUS interconnect.the interface number of each master port is represented using <x>. Clock and reset clk resetn Slave access port dapreadys dapsels dapenables dapwrites dapcaddrs[15:2] dapwdatas[31:0] daprdatas[31:0] dapslverrs dapaborts DAP bus interconnect dapreadym<x> dapselm<x> dapenablem<x> dapwritem<x> dapcaddrm<x>[7:2] dapwdatam<x>[31:0] dapprdatam<x>[31:0] dapslverrm<x> dapabortm<x> Example master access port Figure 2-2 DAPBUS interconnect block diagram DAP asynchronous bridge The DAP asynchronous bridge enables data transfer between two asynchronous clock domains within the DAP sub-system. Figure 2-3 shows the external connections on the DAP asynchronous bridge. The AMBA compliant Low Power Interface LPI is optional on the DAP asynchronous bridge. DAP asynchronous bridge Clock and reset dapclks dapclkens dapresetsn dapclkm dapclkenm dapresetmn Clock and reset dapwrites dapwdatas[31:0] dapaddrs[31:0] dapreadys dapenables dapsels dapaborts dapslverrs daprdatas[31:0] Slave interface Master interface dapwritem dapwdatam[31:0] dapaddrm[31:0] dapreadym dapenablem dapabortm dapselm dapslverrm daprdatam[31:0] Low power interface csysack csysreq cactive Figure 2-3 DAP asynchronous bridge block diagram DAP synchronous bridge The DAP synchronous bridge enables data transfer between two synchronous clock domains within the DAP sub-system. Figure 2-4 on page 2-4 shows the external connections on the DAP synchronous bridge. The AMBA compliant Low Power Interface (LPI) is optional on the DAP synchronous bridge. ARM DDI 0480B Copyright ARM. All rights reserved. 2-3

22 Functional Overview DAP synchronous bridge Clock and reset dapclk dapclens dapresetn dapclkenm dapwrites dapwdatas[31:0] dapaddrs[31:0] dapreadys dapenables dapsels dapaborts dapslverrs daprdatas[31:0] Slave interface Master interface dapwritem dapwdatam[31:0] dapaddrm[31:0] dapreadym dapenablem dapselm dapabortm dapslverrm daprdatam[31:0] Figure 2-4 DAP synchronous bridge block diagram JTAG - Access Port The JTAG-AP provides a dedicated on-chip JTAG access to components from the DAP (independent of the off-chip JTAG or SW connection). See Chapter 4 Debug Access Port for more information. Figure 2-5 shows the external connections on the JTAG-AP. Clock and reset Debug access port dapclk dapclken dapresetn dapwrite dapwdata[31:0] dapabort dapready dapenable dapsel daprdata[31:0] dapaddr[7:2] JTAG-AP csrtck[7:0] srstconnected[7:0] portconnected[7:0] portenabled[7:0] cstdo[7:0] nsrstout[7:0] ncstrst[7:0] cstck[7:0] cstdi[7:0] cstms[7:0] Connections to JTAG slave Figure 2-5 JTAG-Access Port block diagram Advanced extensible Interface - Access Port (AXI-AP) The AXI-AP connects a DAP to an AXI component or system. You must configure the AXI-AP during implementation, with the following parameters: AXI_ADDR_WIDTH, 32-bit or 64-bit (shown as aw in Figure 2-6 on page 2-5). AXI_DATA_WIDTH, 32-bit or 64-bit (shown as dw in Figure 2-6 on page 2-5). See Chapter 4 Debug Access Port for more information. Figure 2-6 on page 2-5 shows the external connections on the AXI-AP. ARM DDI 0480B Copyright ARM. All rights reserved. 2-4

23 Functional Overview Clock and reset Authentication Debug access port clk resetn dbgen spiden dapwrite dapwdata[31:0] dapabort dapready dapenable dapsel dapslverr daprdata[31:0] dapaddr[31:0] awaddr[aw:0] awlen[3:0] awsize[2:0] awburst[1:0] awlock[1:0] awcache[3:0] awprot[2:0] awvalid awready araddr[aw:0] arlen[3:0] arsize[2:0] arburst[1:0] arlock[1:0] arcache[3:0] arprot[2:0] arvalid arready Write address channel Read address channel AXI-AP wdata[dw:0] wstrb[dw/8:0] wlast wvalid wready Write data channel bresp[1:0] bvalid bready Write response channel rdata[dw:0] rresp[1:0] rlast rvalid rready awdomain[1:0] awsnoop[3:0] awbar[1:0] ardomain[1:0] arsnoop[3:0] arbar[1:0] Read data channel Write address channel ACE-Lite Read address channel ACE-Lite Figure 2-6 Advanced extensible Interface - Access Port block diagram Advanced High-performance Bus - Access Port (AHB-AP) The AHP-AP connects a DAP to an AHB system bus. The AHB-AP has no configurable features. See Chapter 4 Debug Access Port for more information. Figure 2-7 on page 2-6 shows the external connections on the AHB-AP. ARM DDI 0480B Copyright ARM. All rights reserved. 2-5

24 Functional Overview Clock and reset dapclk dapclken dapresetn Authentication Debug access port dbgen spiden dapwrite dapwdata[31:0] dapabort dapready dapenable dapsel dapslverr daprdata[31:0] dapcaddr[7:2] AHB-AP hreadym hrespm hrdatam[31:0] hwritem hlockm htransm[1:0] hsizem[2:0] hburstm[2:0] hbstrbm[3:0] hprotm[6:0] haddrm[31:0] hwdatam[31:0] AHB port Figure 2-7 Advanced High-performance Bus - Access Port block diagram Advanced Peripheral Bus Access Port (APB-AP) The APB-AP connects a DAP to an APB system bus. The APB-AP has no configurable features. See Chapter 4 Debug Access Port for more information. Figure 2-8 shows the external connections on the APB-AP. Clock and reset Slave access port dapclk dapclken dapresetn dapready dapsel dapenable dapwrite dapcaddr[7:2] dapwdata[31:0] daprdata[31:0] dapslverr dapabort APB-AP paddr31 pwrite psel penable paddr[31:2] pwdata[31:0] pready pselveer prdata[31:0] pdbgswen APB master port deviceen Figure 2-8 Advanced Peripheral Bus - Access Port block diagram APB InterConnect (APBIC) with ROM table The APBIC with ROM table connects multiple APB masters to multiple slaves. The APBIC implements a ROM table that contains information about the components in a CoreSight system. The APBIC operates in a single clock domain. Use asynchronous bridges to connect other components that are not synchronous. ARM DDI 0480B Copyright ARM. All rights reserved. 2-6

25 Functional Overview The following configurable options must be set for the APBIC: SLAVE_INTF_ADDR_WIDTH, see saw in Figure 2-9) MASTER_INTF_ADDR_WIDTH see maw in Figure 2-9) Figure 2-9 shows the external connections on the APBIC. <x> in the figure denotes an automatically-generated numeric interface number. clk resetn dbgswen targetid[31:0] APB slave port paddr31s0 pwrites0 psels0 penables0 paddrs0[saw:2] pwdatas0[31:0] preadys0 pslverrs0 prdatas0[31:0] APB interconnect paddr31m<x> pwritem<x> pselm<x> penablem<x> paddrm<x>[maw:2] pwdatam<x>[31:0] preadym<x> pselveerm<x> prdatam<x>[31:0] Example APB master port Figure 2-9 APB interconnect with ROM table block diagram For information about the user programmable registers for the APBIC, see Chapter 3 Programmers Model. Cascading APBICs Systems that require more than the maximum configurable number of slaves can use a cascading approach. You can connect two or more APBICs to implement a hierarchy of APB peripherals APB asynchronous bridge The APB asynchronous bridge enables data transfer between two asynchronous clock domains. The AMBA compliant Low Power Interface (LPI) is optional on the APB asynchronous bridge. Figure 2-10 on page 2-8 shows the external connections to the APB asynchronous bridge. ARM DDI 0480B Copyright ARM. All rights reserved. 2-7

26 Functional Overview APB asynchronous bridge Clock and reset pclks presetsn pcklens pclkm presetmn pclkenm Clock and reset APB slave port pwrites psels penables paddrs[31:0] pwdatas[31:0] preadys pslverrs prdatas[31:0] Slave interface Master interface pwritem pselm penablem paddrm[31:0] pwdatam[31:0] preadym pslverrm prdatam[31:0] APB master port Low power interface csysack csysreq cactive Figure 2-10 APB asynchronous bridge block diagram APB synchronous bridge The APB synchronous bridge enables data transfer between two synchronous clock domains. The AMBA compliant Low Power Interface (LPI) is optional on the APB synchronous bridge. Figure 2-11 shows the external connections on the APB synchronous bridge. Clock and reset pclk pclkens presetn pclkenm APB slave port paddrs[31:0] pwrites pwdatas[31:0] psels penables preadys prdatas[31:0] pslverrs APB synchronous bridge paddrm[31:0] pwritem pwdatam[31:0] pselm penablem preadym prdatam[31:0] pslverrm APB master port Low power interface csysack csysreq cactive Figure 2-11 APB synchronous bridge block diagram ARM DDI 0480B Copyright ARM. All rights reserved. 2-8

27 Functional Overview 2.2 Advanced Trace Bus interconnect components The Advanced Trace Bus (ATB) interconnect facilitates the transfer of trace data around the CoreSight debug system. A custom generated interconnect infrastructure also uses these componentsto provide aditional functionality as required by your system architecture: ATB replicator ATB funnel on page 2-10 ATB upsizer on page 2-10 ATB downsizer on page ATB asynchronous bridge on page 2-11 ATB synchronous bridge on page 2-12 See Chapter 5 ATB Interconnect Components for more information about these components ATB replicator The ATB replicator propagates data from a single master to two slaves. Figure 2-12 shows the external connections on the ATB replicator. You can specify an optional APB configuration interface. The following parameter must be supplied and is used to implement the ATB replicator: ATB_DATA_WIDTH of 8, 16, 32, or 64, see dw in Figure 2-12 where dw=atb_data_width-1. Note In Figure 2-12 bw is generated automatically from the parameter ATB_DATA_WIDTH. Clock and reset clk resetn ATB slave port atvalids atreadys atids[6:0] atbytess[bw:0] atdatas[dw:0] afvalids afreadys atvalidm0 atreadym0 atidm0[6:0] atbytesm0[bw:0] atdatam0[dw:0] afvalidm0 afreadym0 ATB master port 0 syncreqs ATB replicator syncreqm0 Optional APB port prdatadbg[31:0] preadydbg pslverrdbg paddrdbg[11:2] pwritedbg pwdatadbg[31:0] pseldbg penabledbg pclkendbg paddrdbg31 atvalidm1 atreadym1 atidm1[6:0] atbytesm1[bw:0] atdatam1[dw:0] afvalidm1 afreadym1 syncreqm1 ATB master port 1 Figure 2-12 ATB replicator block diagram ARM DDI 0480B Copyright ARM. All rights reserved. 2-9

28 Functional Overview ATB funnel The ATB funnel merges the trace from multiple ATB buses and sends the data to a single ATB bus. Figure 2-13 shows the external connections on the ATB funnel. The <x> denotes the auto-generated interface number of the specific ATB interface. You can specify an optional APB configuration interface. The following parameter must be supplied and is used to implement the ATB replicator: CXFUNNEL_ATB_DATA_WIDTH of 8, 16, 32, or 64, see dw in Figure 2-13 where dw=cxfunnel_atb_data_width-1. Note In Figure 2-13 bw is generated automatically from the parameter CXFUNNEL_ATB_DATA_WIDTH. Clock and reset clk resetn Example ATB slave port atvalidsx atreadysx atidsx[6:0] atbytessx[bw:0] atdatasx[dw:0] afvalidsx afreadysx atvalidm atreadym atidm[6:0] atbytesm[bw:0] atdatam[dw:0] afvalidm afreadym ATB master port syncreqsx ATB funnel syncreqm Optional APB port prdatadbg[31:0] preadydbg pslverrdbg paddrdbg[11:2] pwritedbg pwdatadbg[31:0] pseldbg penabledbg pclkendbg paddrdbg31 Figure 2-13 ATB funnel block diagram ATB upsizer The ATB upsizer converts the trace data on a narrower ATB bus on to a wider bus. Figure 2-14 on page 2-11 shows the external connections to the ATB upsizer. The following parameters must be supplied and is used to implement the ATB replicator: ATB_DATA_WIDTH_SLAVE of 8, 16, 32, or 64, see sdw in Figure 2-14 on page 2-11 where sdw=atb_data_width_slave-1. ATB_DATA_WIDTH_MASTER of 8, 16, 32, or 64, see mdw in Figure 2-14 on page 2-11 where mdw=atb_data_width_master-1. ARM DDI 0480B Copyright ARM. All rights reserved. 2-10

29 Functional Overview Note In Figure 2-14 sbw and mbw are generated automatically from the parameter ATB_DATA_WIDTH_SLAVE and ATB_DATA_WIDTH_MASTER respectively. Clock and reset clk resetn ATB slave port atvalids atreadys atids[6:0] atbytess[sbw:0] atdatas[sdw:0] afvalids afreadys ATB upsizer atvalidm atreadym atidm[6:0] atbytesm[mbw:0] atdatam[mdw:0] afvalidm afreadym ATB master port syncreqs syncreqm Figure 2-14 ATB upsizer block diagram ATB downsizer The ATB downsizer converts the trace data on a wider ATB bus onto a narrower width bus. Figure 2-15 shows the external connections on the ATB downsizer. The following parameters must be supplied and is used to implement the ATB replicator: ATB_DATA_WIDTH_SLAVE of 8, 16, 32, or 64, see sdw in Figure 2-14 where sdw=atb_data_width_slave-1. ATB_DATA_WIDTH_MASTER of 8, 16, 32, or 64, see mdw in Figure 2-14 where mdw=atb_data_width_master-1. Note In Figure 2-15 sbw and mbw are generated automatically from the parameter ATB_DATA_WIDTH_SLAVE and ATB_DATA_WIDTH_MASTER respectively. Clock and reset clk resetn ATB slave port atvalids atreadys atids[6:0] atbytess[sbw:0] atdatas[sdw:0] afvalids afreadys ATB downsizer atvalidm atreadym atidm[6:0] atbytesm[mbw:0] atdatam[mdw:0] afvalidm afreadym ATB master port syncreqs syncreqm Figure 2-15 ATB downsizer block diagram ATB asynchronous bridge The ATB asynchronous bridge enables data transfer between two asynchronous clock domains. Figure 2-16 on page 2-12 shows the external connections to the ATB asynchronous bridge. ARM DDI 0480B Copyright ARM. All rights reserved. 2-11

30 Functional Overview The following parameter must be supplied and is used to implement the ATB replicator: ATB_DATA_WIDTH of 8, 16, 32, or 64, see dw in Figure 2-16 where dw=atb_data_width-1. Note In Figure 2-16 bw is generated automatically from the parameter ATB_DATA_WIDTH. ATB asynchronous bridge Clock and reset resetsn clks clkens resetmn clkm clkenm Clock and reset ATB slave port atvalids atreadys atids[6:0] atbytess[bw:0] atdatas[dw:0] afvalids afreadys Slave interface Master interface atvalidm atreadym atidm[6:0] atbytesm[bw:0] atdatam[dw:0] afvalidm afreadym syncreqm ATB master port syncreqs csysreq csysack cactive Low power interface Figure 2-16 ATB asynchronous bridge block diagram ATB synchronous bridge The ATB synchronous bridge enables data transfer between two synchronous clock domains. Figure 2-17 on page 2-13 shows the external connections to the ATB synchronous bridge. The following parameter must be supplied and is used to implement the ATB replicator: ATB_DATA_WIDTH of 8, 16, 32, or 64, see dw in Figure 2-17 on page 2-13 where dw=atb_data_width-1. Note In Figure 2-17 on page 2-13 bw is generated automatically from the parameter ATB_DATA_WIDTH. ARM DDI 0480B Copyright ARM. All rights reserved. 2-12

31 Functional Overview Clock and reset resetn clk clkens clkenm ATB slave port atvalids atreadys atids[6:0] atbytess[bw:0] atdatas[dw:0] afvalids afreadys ATB synchronous bridge atvalidm atreadym atidm[6:0] atbytesm[bw:0] atdatam[dw:0] afvalidm afreadym ATB master port syncreqs syncreqm csysreq csysack cactive Low power interface Figure 2-17 ATB synchronous bridge block diagram ARM DDI 0480B Copyright ARM. All rights reserved. 2-13

32 Functional Overview 2.3 Timestamp components The timestamp components generate and distribute a consistent timestamp value for multiple processors and other blocks within a SoC. The components available to build this system are: Timestamp generator Timestamp encoder Narrow timestamp replicator on page 2-15 Narrow timestamp asynchronous bridge on page 2-15 Narrow timestamp synchronous bridge on page 2-16 Timestamp decoder on page 2-16 Timestamp interpolator on page 2-17 See Chapter 6 Timestamp Components for more information Timestamp generator The timestamp generator generates a timestamp value that provides a consistent view of time for multiple processors and other blocks in a SoC. The timestamp generator has no configurable features. For more informaiton on the timestamp generator. See on page 6-1. Also for information on the timestamp generators register description. See on page 3-1. Figure 2-18 shows the external connections on the timestamp generator. Clock and reset clk resetn hltdbg Control APB3 interface paddrctrl[11:2] pselctrl penablectrl pwritectrl pwdatactrl[31:0] preadyctrl prdatactrl[31:0] psvlerrctrl Timestamp generator tsvalueb[63:0] tsforcesync Wide timestamp interface Read APB3 interface paddrread[11:2] pselread penableread pwriteread pwdataread[31:0] preadyread prdataread[31:0] pslverrread Figure 2-18 Timestamp generator block diagram Timestamp encoder The timestamp encoder converts the 64-bit timestamp value from the timestamp generator to a 7-bit encoded value. This is called a narrow timestamp. It also encodes and sends the timestamp value over a 2-bit synchronization channel. ARM DDI 0480B Copyright ARM. All rights reserved. 2-14

33 Functional Overview The timestamp encoder has no configurable features. Figure 2-19 shows the external connections on the timestamp encoder. Clock and reset Timestamp interface tsclk tsresetn tsforcesync tsvalue[63:0] Timestamp encoder tsbit[6:0] tssync[1:0] tssyncready Narrow timestamp interface Figure 2-19 Timestamp encoder block diagram Narrow timestamp replicator The narrow timestamp replicator distributes the encoded timestamp and synchronization data to multiple slave bridges. You can configure the number of slave bridges to be connected to the narrow timestamp replicator. Figure 2-20 shows the external connections on the narrow timestamp replicator. Narrow timestamp interface clk resetn ts_bit_valid_qualify tsbits[6:0] tssyncs[1:0] tssyncreadys Narrow timestamp replicator tsbitmn[6:0] tssyncmn[1:0] tssyncreadymn Narrow timestamp interface Figure 2-20 Narrow timestamp replicator block diagram Narrow timestamp asynchronous bridge The narrow timestamp asynchronous bridge enables the transfer of timestamp information across different clock domains. Figure 2-21 on page 2-16 shows the external connections on the narrow timestamp asynchronous bridge. ARM DDI 0480B Copyright ARM. All rights reserved. 2-15

34 Functional Overview Narrow timestamp asynchronous bridge Clock and reset clks resetsn clkm resetmn Clock and reset Narrow timestamp interface Low power interface tsbits[6:0] tssyncs[1:0] tssyncreadys csysreq csysack cactive Slave interface Master interface tsbitmn[6:0] tssyncmn[1:0] tssyncreadym lp_req_m lp_ack_m Narrow timestamp interface Low power handshake Low power handshake lp_req_s lp_ack_s Figure 2-21 Narrow timestamp asynchronous bridge block diagram Narrow timestamp synchronous bridge The narrow timestamp synchronous bridge enables the transfer of timestamp information across clock domains that have individual clock enables. Figure 2-22 shows the external connections on the narrow timestamp synchronous bridge. Clock and reset clk resetn clkens clkenm Narrow timestamp interface tsbits[6:0] tssyncs[1:0] tssyncreadys Narrow timestamp synchronous bridge tsbitm[6:0] tssyncm[1:0] tssyncreadym Narrow timestamp interface Lowpower interface csysreq csysack cactive Figure 2-22 Narrow timestamp synchronous bridge block diagram Timestamp decoder The timestamp decoder converts the encoded timestamp and synchronization data back to a 64-bit value, this is the format that the CoreSight trace component require their timestamp. Figure 2-23 on page 2-17 shows the external connections on the timestamp decoder. ARM DDI 0480B Copyright ARM. All rights reserved. 2-16

35 Functional Overview Clock and reset Narrow timestamp interface clk resetn tsbit[6:0] tssync[1:0] tssyncready Timestamp decoder tsvalue[63:0] Timestamp interface Figure 2-23 Timestamp decoder block diagram Timestamp interpolator CoreSight components require timestamp values that allow software to correlate events. A timestamp generator generates timestamp values. This is typically at a clock rate that is much slower than the operating frequency of CoreSight components. The timestamp interpolator uses the timestamp values from the timestamp generator as reference and generates timestamp values at a rate required by CoreSight components. Figure 2-24 shows the external connections on the timestamp interpolator. Clock and reset Timestamp slave interface clk resetn tsvalueb[63:0] Timestamp interpolator tsvalueintpb[63:0] Timestamp master interface Figure 2-24 Timestamp interpolator block diagram ARM DDI 0480B Copyright ARM. All rights reserved. 2-17

36 Functional Overview 2.4 Trigger components CoreSight SoC contains the following trigger components to control the logging of debug information: Cross Trigger Interface (CTI) Cross Trigger Matrix (CTM). The CTI and CTM form the Embedded Cross Trigger (ECT) sub-system that enables the ARM Embedded Trace Macrocell (ETM) subsystems to interact, that is cross trigger, with each other. The main function of the ECT is to pass debug events from one processor to another. For example, the ECT can communicate debug state information from one processor to the others, so that program execution on one or more processors can be stopped at the same time if required Cross Trigger Interface (CTI) The CTI combines and maps the trigger requests, and broadcasts them to all other interfaces on the ECT sub-system. When the CTI receives a trigger request it maps this onto a trigger output. This enables the ETM subsystems to cross trigger with each other. Figure 2-25 shows the external connections on the CTI. Block clock and reset APB clock and reset CTICLK CTICLKEN nctireset PCLKDBG PCLKENDBG PRESETDBGn TISBYPASSIN TISBYPASSACK CTITRIGIN[7:0] CTITRIGOUTACK[7:0] CTITRIGOUT[7:0] CTITRIGINACK[7:0] CTM link Trigger interface General control Sync by-pass control Handshake bypass Debug enable masking SE CTIAPBSBYPASS CISBYPASS ASICCTL[7:0] CTIAPBSBYPASS[7:0] CISBYPASS[3:0] CIHSBYPASS[3:0] TIHSBYPASS[7:0] TINIDENSEL[7:0] TODBGENSEL[7:0] Cross Trigger Interface (CTI) CTICHIN[3:0] CTICHOUTACK[3:0] CTICHOUT[3:0] CTICHINACK[3:0] PADDRDBG[11:2] PWRITEDBG PWDATADBG[31:0] PSELDBG PENABLEDBG PCLKENDBG PADDRDBG31 PRDATADBG[31:0] PREADYDBG Channel interface Optional APB port Figure 2-25 Cross Trigger Interface block diagram Cross Trigger Matrix (CTM) This block controls the distribution of trigger requests. It connects to at least two CTIs and to other CTMs where required in a design. Figure 2-26 on page 2-19 shows the external connections on the CTM block. The CTM must be configured with the following parameter that defines the width of some ports of the block: ECTCHANNELWIDTH see CW in Figure 2-26 on page 2-19 where CW=ECTCHANNELWIDTH-1. ARM DDI 0480B Copyright ARM. All rights reserved. 2-18

37 Functional Overview Clock and reset Sync by-pass control Handshake bypass CTMCLK CTMCLKEN nctmreset SE CISBYPASS0 CISBYPASS1 CISBYPASS2 CISBYPASS3 CIHSBYPASS0[CW:0] CIHSBYPASS1[CW:0] CIHSBYPASS2[CW:0] CIHSBYPASS3[CW:0] Cross Trigger Matrix (CTM) CTMCHIN0[CW:0] CTMCHOUTACK0[CW:0] CTMCHOUT0[CW:0] CTMCHINACK0[CW:0] CTMCHIN1[CW:0] CTMCHOUTACK1[CW:0] CTMCHOUT1[CW:0] CTMCHINACK1[CW:0] CTMCHIN2[CW:0] CTMCHOUTACK2[CW:0] CTMCHOUT2[CW:0] CTMCHINACK2[CW:0] CTMCHIN3[CW:0] CTMCHOUTACK3[CW:0] CTMCHOUT3[CW:0] CTMCHINACK3[CW:0] Channel interface 0 Channel interface 1 Channel interface 2 Channel interface 3 Figure 2-26 Cross Trigger Matrix block diagram ARM DDI 0480B Copyright ARM. All rights reserved. 2-19

38 Functional Overview 2.5 Trace sink components CoreSight SoC contains the following components for receiving debug information and looking after its transmission onto the main debug infrastructure. The trace sink components are: Trace Port Interface Unit (TPIU) Embedded Trace Buffer (ETB) Trace Port Interface Unit (TPIU) The Trace Port Interface Unit (TPIU) provides connectivity from an Advanced Trace Bus (ATB) to an external trace port. Figure 2-27 shown the external connections on the TPIU. Trace bus clock and reset ATCLK ATCLKEN ATRESETn TRACECLK TRACECTL TRACEDATA[31:0] Trace output APB clock and reset Trace source clock and reset PCLKDBG PCLKENDBG PRESETDBGn TRACECLKIN TRESETn SE PRDATADBG[31:0] PREADYDBG PADDRDBG[11:2] PWRITEDBG PWDATADBG[31:0] PSELDBG PENABLEDBG PADDRDBG31 APB programming port Tie-off configuration pins ATB slave port TPCTL TPMAXDATASIZE[4:0] ATVALIDS ATREADYS ATIDS[6:0] ATBYTESS[1:0] ATDATAS[31:0] AFVALIDS AFREADYS Trace Port Interface Unit (TPIU) Trigger and flushing EXTCTLIN EXTCTLOUT[7:0] TRIGIN TRIGINACK FLUSHIN FLUSHINACK Figure 2-27 Trace Port Interface Unit block diagram Embedded Trace Buffer (ETB) The Embedded Trace Buffer (ETB) stores trace data while waiting for transmission out into the CoreSight system. Figure 2-28 on page 2-21 shows the external connections on the ETB. The ETB must be configured with the following parameter that defines the width of the MBIST address for trace RAM testing: CSETB_RAM_ADRW see AW in Figure 2-28 on page 2-21 where AW=CSETB_RAM_ADRW-1. ARM DDI 0480B Copyright ARM. All rights reserved. 2-20

39 Functional Overview Clock and reset APB clock and reset ATCLK ATCLKEN ATRESETn PCLKDBG PCLKENDBG PRESETDBGn MTESTON MBISTCE MBISTWE MBISTADDR[AW:0] MBISTDIN[31:0] MBISTDOUT[31:0] APB programming port ATB slave port SE ATVALIDS ATREADYS ATIDS[6:0] ATBYTESS[1:0] ATDATAS[31:0] AFVALIDS AFREADYS Embedded Trace Buffer (ETB) PRDATADBG[31:0] PREADYDBG PADDRDBG[11:2] PWRITEDBG PWDATADBG[31:0] PSELDBG PENABLEDBG PADDRDBG31 APB programming port Trigger and flushing FULL ACQCOMP TRIGIN TRIGINACK FLUSHIN FLUSHINACK Figure 2-28 Embedded Trace Buffer block diagram ARM DDI 0480B Copyright ARM. All rights reserved. 2-21

40 Functional Overview 2.6 Authentication and event bridges The additional bridges are: Authentication asynchronous bridge Authentication synchronous bridge Event asynchronous bridge on page The authentication bridges provide authenticated debug control links in security enabled CoreSight systems. These components are not required if this security is not required Authentication asynchronous bridge The authentication asynchronous bridge enables transfers of authentication signals between two asynchronous clock domains. You must configure the authentication asynchronous bridge during implementation, with the authentication signals that are present. Figure 2-29 shows the external connections on the authentication asynchronous bridge. Authentication asynchronous bridge Clock and reset clks resetsn clkm resetmn Clock and reset Slave port dbgens nidens spidens spnidens dbgswens Slave interface Master interface dbgenm nidenm spidenm spnidenm dbgswenm Master port Figure 2-29 Authentication asynchronous bridge block diagram Authentication synchronous bridge The authentication synchronous bridge enables the transfers of authentication signals between two synchronous clock domains. It can also be used as a register slice to break long timing paths. You must configure the authentication synchronous bridge during implementation, with the authentication signals that are present. Figure 2-30 shows the external connections on the authentication synchronous bridge. Clock and reset clk resetn Slave port dbgens nidens spidens spnidens dbgswens Authentication synchronous bridge dbgenm nidenm spidenm spnidenm dbgswenm Master port Figure 2-30 Authentication synchronous bridge block diagram ARM DDI 0480B Copyright ARM. All rights reserved. 2-22

41 Functional Overview Event asynchronous bridge The event asynchronous bridge is a fixed component that synchronizes events on a single channel from the master domain to the slave domain. The event acknowledge from the slave domain is synchronized and presented to the master domain. It follows a 4-phase handshake mechanism: When a clks event is asserted, it is synchronized as clkm, and presented to the slave domain When a clkm event is asserted, it is synchronized as clks, and presented to the master domain. It can also be used as an event bridge, when the master device ignores the acknowledge from the slave device. If the event is a pulse, the bridge internally stretches the event until it receives an acknowledge from the slave device. In this mode of operation, none of the events from the master device are recognized. Figure 2-31 shows the external connections on the event asynchronous bridge. Event asynchronous bridge Slave clock and reset Event slave port clks clkens resetsn events eventacks Slave interface Master interface clkm clkenm resetmn eventm eventackm Master clock and reset Event master port Figure 2-31 Event asynchronous bridge block diagram ARM DDI 0480B Copyright ARM. All rights reserved. 2-23

42 Functional Overview 2.7 Granular Power Requestor (GPR) The Granular Power Requester (GPR) enables a debugger to control powerup and power-down of specific components within a CoreSight system. Without the GPR, the CoreSight DAP components only support system level power-up and powerdown of the entire CoreSight system. The finer granularity provided by the GPR enables implementation of power strategies during both debug and ATPG testing. Figure 2-32 shows the external connections on the GPR. You must configure the GPR during implementation with the following parameters: NUM_CPWRUPM see Figure Clock and reset clk resetn APB control interface pseldbg penabledbg pwritedbg paddrdbg[11:2] paddrdbg31 pwdatadbg[31:0] pslverrdbg preadydbg prdatadbg[31:0] Granular Power Requestor (GPR) cpwrupreq[num_cpwrupm-1:0] cpwrupack[num_cpwrupm-1:0] System power on request The GPR has the following properties: Figure 2-32 Granular Power Requestor block diagram the interfaces comply with the APB3 AMBA protocol and CoreSight architecture specification the GPR operates in a single debug power domain up to 32 power domains are supported. ARM DDI 0480B Copyright ARM. All rights reserved. 2-24