Hi Hsiao-Lung Chan Dept Electrical Engineering Chang Gung University, Taiwan

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1 Interrupts and Resets Hi Hsiao-Lung Chan Dept Electrical Engineering Chang Gung University, Taiwan

2 Interrupts An event that will cause the CPU to stop the normal program execution and provide some service to the event. External interrupt Generated when the external hardware asserts an interrupt signal to the CPU Internal interrupt Generated by the hardware circuitry inside the chip Caused by software errors. Illegal opcodes, divide-by-zero, etc. Also called traps and exceptions 2

3 Applications of interrupts Coordinate I/O activities Prevent CPU from being tied up during the data transfer process Perform time-critical operation Provide a graceful way to exit from the application when a software error occurred Remind the CPU to perform routine tasks: Keep track of time of day Periodic data acquisition Task switching in a multi-tasking t operating system 3

4 Interrupt maskability Maskable interrupt Some interrupts are not desirable under some situations and should be ignored by the CPU. Nonmaskable interrupts Events that the CPU shouldn t ignore and must take immediate action. A program can disable (mask) an interrupt by setting or clearing a bit for most processors. An interrupt is pending when it is active but not serviced by the CPU. 4

5 Interrupt priority More than one interrupt source can be pending at the same time. The CPU needs to decide which one of the pending interrupts to service. The interrupt at the higher priority will be attended before the interrupt at the lower priority. Interrupt priority can be implemented by the hardware or software. The PIC18 supports two-level interrupt priority only and let the software to decide which pending interrupt to service. 5

6 Interrupt service The CPU provides service to an interrupt by executing an interrupt service routine (ISR). Complete interrupt service cycle Saving the program counter in the stack Saving the CPU status in the stack (optional for some processor) Identifying the interrupt source Resolving the starting address of the corresponding ISR Executing the interrupt service routine Restoring the CPU status from the stack Restoring the program counter from the stack Resuming the interrupted program 6

7 Interrupt vector The starting address of the ISR How to determine the interrupt vector Predefined (Microchip) Fetch vector from a predefined memory location (interrupt vector table) (Motorola) Execute an interrupt vector acknowledge cycle to fetch a vector number to locate the interrupt t vector (Intel Pentium) 7

8 Interrupt programming g Step 1. Write the service routine org ox08 ; interrupt service for high priority interrupts retfie org 0x18 ; interrupt service for low priority interrupts retfie Step 2. Initialize the interrupt vector table (not needed for PIC18) Step 3. Enable interrupts to be serviced 8

9 The PIC18 interrupts Interrupt sources Four edge-triggered INT pin (INT0 INT3) interrupts Port B pins change (any one of the upper four Port B pins) On-chip peripheral function interrupts Registers related to interrupts RCON, INTCON, INTCON2, INTCON3 PIR1, PIR2, and PIR3 PIE1, PIE2, and PIE3 IPR1, IPR2, and IPR3 Each interrupt source has three bits to control its operation Afl flag bit: indicating whether an interrupt t has occurred An enable bit: enabling or disabling the interrupt source A priority bit: selecting high priority or low priority 9

10 RCON register 10

11 Interrupt control register (INTCON) 11

12 INTCON2 12

13 INTCON3 13

14 PIR1 (individual flag bits for peripheral interrupts) 14

15 PIR2 15

16 PIR3 16

17 PIE1 (individual enable bits for peripheral interrupts) 17

18 PIE2 18

19 PIE3 19

20 IPR1 (Interrupt priority register) (individual priority bits for peripheral interrupts) 20

21 IPR2 21

22 IPR3 22

23 PIC18 interrupt operation Core group Interrupt sources INT0 INT3 pin interrupts TMR0 overflow interrupt PORTB input pin (RB7 RB4) change interrupts High-priority interrupts under the control of a two-level interrupt enabling mechanism Peripheral group Low-priority interrupts are under the control of a three-level interrupt enabling scheme 23

24 PIC18 interrupt without setting priority Clear interrupt priority enable (IPEN) bit in the RCON register Enable interrupt sources in the core group by setting GIE bit (INTCON<7>) corresponding enable bit of the interrupt source Set TMR0IE to enable TMR0 interrupt (INTCON<5>) Enable interrupts in the peripheral group by setting GIE bit PEIE bit (INTCON<6>) Associated interrupt enable bit Set ADIE to enable A/D interrupt (PIE1<6>) All interrupt sources share the common interrupt vector at 0x08. Check each individual interrupt flag bit (PIR1~PIR3 registers) to identify the cause of interrupt 24

25 PIC18 interrupt with priority enabled Set the IPEN bit in the RCON register Enable a high-priority interrupt by setting GIEH bit (INTCON<7>) Corresponding interrupt enable bit Enable a low-priority interrupt by setting GIEH bit GIEL bit (INTCON<6>) Associated interrupt enable bit in the IPR register All low-priority interrupt sources share the same interrupt vector at 0x18; 0x08 for high-priority interrupts. The pending interrupts in the high-priority group is served before the interrupts in the low-priority group. Interrupt flags must be cleared in the interrupt service routine to avoid recursive interrupts. 25

26 PIC18 interrupt operation When an interrupt is responded GIE bit is automatically cleared to disable further interrupt Return address is pushed onto return address stack PC is loaded with the interrupt vector 26

27 Core group interrupts INT0 INT3 Edge-triggered. INTEDG0~INTEDG3 in the INTCON2 register 0 and 1 for falling and rising edge, respectively Port B pins input change The RB7 RB4 pins must be configured for input. Set RBIE (INTCON<3>): interrupt enable it An input change on pins RB7 RB4 sets the flag bit RBIF (INTCON<0>) TMR0 overflow 8-bit mode TMROL counts from 0xFF to 0x00, triggering an interrupt 16-bit mode. TMROH:TMROL counts from 0xFFFF to 0x0000, triggering an interrupt 27

28 Demo program: press button to increment the content of register at 0x05 and display the result by LEDs #include <p18f452.inc> 全亮 : 按鈕按一下 : 兩下 : 十下 : 十一下 : 二十下 :.. 以此類推 ACC equ 0x05 org 0x00 goto Main_Program org 0x08 goto INT0_ISR retfie org 0x18 retfie Main_Program clrf TRISD ; set PORTD for output port bsf RCON, IPEN, A ; enable interrupt priority bsf INTCON, GIE, A ; enable global interrupt bsf INTCON, INT0IE, A ; enable INT0 interrupt bcf INTCON2, INTEDG0, A ; set falling-edge trigger bcf INTCON, INT0IF, A ; clear interrupt flag of INT0 28

29 clrf ACC ; clear accumulator setf LATD ; set all LEDs on forever nop goto forever INT0_ISR bcf INTCON, INT0IF, A ; clear interrupt flag of INT0 movlw 0x01 addwf ACC,F movff ACC,LATD retfie end 29

30 Context saving during interrupts When an interrupt occurs, the PIC18 MCU saves WREG, BSR, and STATUS in the fast register stack. The user can use the retfie fast instruction to retrieve these registers before returning from the ISR. Context saving by user Save additional registers in the stack if the interrupt service needs to modify these registers These registers must be restored before returning from the ISR 30

31 Write an assembly program to handle the INT0 interrupt 31

32 #include <p18f8680.inc> count equ 0x00 org 0x00 goto start org 0x08 goto ISR_hi org 0x18 retfie start setf count ; count down from 255 clrf TRISD ; configure port D for output movff count,portd ; output count to LEDs bsf RCON,IPEN ; enable priority interrupt movlw 0x90 ; enable INT0 interrupt movwf INTCON ; and clear INT0IF flag forever nop bra nop ISR_hi btfss INTCON,INT0IF ; check interrupt source retfie ; not caused by INT0, return decf count,f movff count,portd ; output count to LEDs retfie 32

33 Resets Reset service routine has a fixed starting address and is stored in the read only memory. The PIC18 can differentiate various kinds of reset: Power-on on reset (POR) MCLR pin reset during normal operation MCLR pin reset during sleep mode Watchdog timer (WDT) reset (during normal operation) Programmable brown-out reset (BOR) RESET instruction Stack full reset Stack underflow reset 33

34 Reset circuitry 34

35 Reference Han-Way Huang, PIC Microcontroller: An Introduction to Software and Hardware Interfacing, Thomson Delmar Learning,

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