CPEG300 Embedded System Design. Lecture 6 Interrupt System

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1 CPEG300 Embedded System Design Lecture 6 Interrupt System Hamad Bin Khalifa University, Spring 2018

2 Correction Lecture 3, page 18: Only direct addressing mode is allowed for pushing or popping the stack: PUSH A is invalid; Pushing the accumulator onto the stack must be coded as PUSH 0E0H Now stack also supports register addressing in the architecture e.g. PUSH A POP PCL 2

3 Review Levels of Programming Languages Advantages of Assembly Language Elements of Assembly Language Label, Opcode, Operands, Comments Basic Syntax Assembler Directives ORG, END, EQU, BIT, DB Program structure Sequence, branching, repetition, subroutine 3

4 What is Interrupt? An interrupt is the occurrence of a condition that causes a temporary suspension of a program while the condition is serviced by another (sub) program Interrupts are important because they allow a system to respond asynchronously to an event and deal with the event while in the middle of performing another task An interrupt driven system gives the illusion of doing many things simultaneously The (sub) program that deals with an interrupt is called an interrupt service routine (ISR) or interrupt handler When an interrupt occurs, the main program temporarily suspends execution and branches to the ISR The ISR executes, performs the desired operation, and terminates with a return from interrupt (RETI) instruction The RETI instruction is different from the normal RET instruction 4

5 Why Interrupt? Polling vs. Interrupt Polling o The microcontroller continuously monitors the status of a given device. o When the conditions are met, it performs the service. o After that, it moves on to monitor the next device until every one is serviced. Polling can monitor the status of several devices and serve each of them as certain conditions are met. o The polling method is not efficient, since it wastes much of the microcontroller s time by polling devices that do not need service. Interrupts o Whenever any device needs its service, the device notifies the microcontroller by sending it an interrupt signal. o Upon receiving an interrupt signal, the microcontroller interrupts whatever it is doing and serves the device. 5

6 Continue to Execute Master Program Master Program Interrupt Process or Interrupt Service Break Point Interrupt Service Routine (ISR) or Interrupt Handler 6

7 Interrupt Process Flow Interrupt execution flow after receiving the interrupt request from the interrupt source Reset Push PC on Stack Finishes current instruction and saves the PC on stack. Jumps to a fixed location in memory (IVT) depending on the type of interrupt. Timer Overflow Interrupt Occurs At This Time Execute Main Code Push Registers on Stack Execute ISR Code Starts to execute the interrupt service routine until RETI (return from interrupt) Pop Registers from Stack Upon executing the RETI the microcontroller returns to the place where it was interrupted. Get POP PC from stack. Continue to Execute Main Code Pop PC from Stack 7

8 Types of Interrupts Two types of interrupt: Hardware interrupt: o hardware interrupts are implemented using electronic alerting signals that are sent to the processor from an external device, which is either a part of the computer itself, such as a disk controller, or an external peripheral. Software interrupt: o software interrupt is caused either by an exceptional condition in the processor itself, or a special instruction in the instruction set which causes an interrupt when it is executed. Major interrupt signals: Level-triggered Edge-triggered Hybrid Message-signaled: a short coded/modulated pulse 8

9 8051 Interrupt System 8051 has a total of five interrupt sources: two external interrupts (INT0 and INT1), two timer interrupts (Timers 0 and 1), and the serial port interrupt. * Typical STM32 MCU can support 84 interrupts. Interrupt system in

Interrupt Sources External hardware interrupt- INT0 External hardware interrupt- INT1 Timer 0 overflow interrupt- TF0 Timer 1 overflow interrupt- TF1 Serial communication interrupt- RI/TI Interrupt

10 Interrupt Sources External hardware interrupt- INT0 External hardware interrupt- INT1 Timer 0 overflow interrupt- TF0 Timer 1 overflow interrupt- TF1 Serial communication interrupt- RI/TI Interrupt source External interrupt INT0 Timer/counter T0 External interrupt INT1 Timer/counter T1 Serial communication interrupt Interrupt Vector Table (IVT) 0003H 000BH 0013H 001BH 0023H Interrupt Vector Table 10

11 IE Register IE: Interrupt Enable register, address A8H (in SFR); D7 D6 D5 D4 D3 D2 D1 D0 A8H IE EA - - ES ET1 EX1 ET0 EX0 Bit Address AFH - - ACH ABH AAH A9H A8H Function Name Function Example EA (IE.7) Enable or disable interrupts, it is the overall switch CLR IE.7 EX0/EX1 (IE.0/2) Enable or disable external interrupt 0/1 SETB EX0 ET0/ET1 (IE.1/3) Enable or disable Timer 0/1 overflow interrupt CLR ET0 ES Enable or disable serial port interrupt SETB ES IE is 00H after reset and all the interrupts are disabled. e.g To use External interrupt 0 (INT0/), both the EA bit and EX0 bit should be 1 to enable the interrupt function. 11

12 IE Register - Example IE: e.g enable internal timer interrupt and disable all other interrupts D7 D6 D5 D4 D3 D2 D1 D0 A8H IE EA - - ES ET1 EX1 ET0 EX0 Bit Address AFH - - ACH ABH AAH A9H A8H Assembly implementation: Or: CLR ES CLR EX1 CLR EX0 SETB ET0 SETB ET1 SETB EA MOV IE, #8AH ;

13 TCON Register TCON: Timer control register, address 88H (in SFR); it is 00H after reset. D7 D6 D5 D4 D3 D2 D1 D0 88H TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Address 8FH - 8DH - 8BH 8AH 89H 88H Function Name Function Example IT0/IT1 (TCON.0/2) IE0/IE1 (TCON.1/3) TF0/TF1 (TCON.5/7) Used for external Interrupts, when IT0/IT1=1 specifies interrupt on falling edge (at least longer than one machine cycle) and when IT0/IT1=0 it specifies interrupt on low level. Used for external Interrupts, when IE0/IE1 = 0, there s no interrupt request; if IE0/IE1=1, there s interrupt request and CPU goes to ISR, IE0/IE1 will be then cleared by hardware. Timer 0/1 overflow flag, when it is 1, it means timer is over flow and issue the interrupt request. Once the CPU goes to the corresponding ISR, TF0/TF1 will be then cleared by hardware. It can also be cleared using software (not a must). SETB IT0 - CLR TF0 13

14 SCON Register SCON: Serial port control register, address 98H (in SFR); it is 00H after reset. D7 D6 D5 D4 D3 D2 D1 D0 SCON TI RI Bit Address H 98H 98H Function Name Function Example RI (SCON.0) TI (SCON.1) RI is Receive Interrupt flag, When 8051 receive data via RxD pin(port1 pin 0), it get rid of the start and stop bits and places the byte in the SBUF. Then it raises the RI flag ( 1 ) to indicate that a byte has been received and should be picked up before it is lost. TI is Transmit Interrupt flag, When 8051 micro controller finishes the transfer of 8-bit character, it raises the TI flag ( 1 ) to indicate that it is ready to transfer another byte. No hardware clear for RI and TI, the interrupt flags must be cleared using software in the ISR

15 Interrupt Priorities What if two interrupt sources interrupt at the same time? 8051 has two levels of priority: 0 represents low-priority interrupts 1 represents high-priority interrupts The interrupt with the highest priority gets serviced first. All interrupts have a power on default priority order (polling sequence) o External interrupt 0 (INT0) o Timer interrupt0 (TF0) o External interrupt 1 (INT1) o Timer interrupt1 (TF1) o Serial communication (RI+TI) Priority can also be changed to high or low by IP register. * Typical STM32 MCU have 16 levels of interrupt priority. HIGH LOW 15

16 Interrupt Priorities Interrupt nesting Master Program RETI RETI Low-IP ISR High-IP ISR Principle: Low-priority interrupts can be interrupted by high-priority interrupts; Interrupt will not be interrupted by another interrupt with the same priority. 16

17 IP Register IP: Interrupt Priority register, address B8H (in SFR); it is 00H after reset. D7 D6 D5 D4 D3 D2 D1 D0 B8H IP PS PT1 PX1 PT0 PX0 Bit Address BCH BBH BAH B9H B8H Function Name Function Example PX0/PX1 (IP.0/2) External interrupt 0/1 priority (0 - low; 1 - high) SETB PX0 PT0/PT1 (IP.1/3) Timer 0/1 overflow interrupt priority (0 - low; 1 - high) CLR PT0 PS (IP.4) Serial port interrupt priority (0 - low; 1 - high) CLR IP.4 If multiple interrupts with the same IP level are received at the same time, the interrupts are handled based on the polling sequence. 17

18 Interrupt Response The following conditions must be met in order for the CPU to respond the interrupt request: The EA bit in IE register is 1 (enable interrupt); e.g EA=1; The interrupt resource enable bit is 1 (enable the specific interrupt); e.g. EX0=1; The interrupt flag of the interrupt source is set; e.g. IE0=1; With the above conditions, the request can not be handled as well if one of the following conditions exists: There are ISRs with the same or higher IP-level currently running in the CPU. CPU is executing instructions like RETI, configure IE or IP. In this case, the CPU should firstly finish the RETI, IE/IP access instructions. Then execute one more instruction before it can handle the request. It is not the last machine cycle of the current instruction being executed by CPU. The CPU should finish current instruction first. Handling procedures: 1. A subroutine call instruction will be generated by the CPU LCALL addr16 2. Place an IP-flag on this response (0 low, 1 - high) 3. CPU goes to execute the instruction 1) Push current PC to stack 2) Load the IVT to PC 4. Return to main process 18

19 Interrupt Response Time Minimum: 3 machine cycles Interrupt flag enquiry 1 machine cycle Jump to ISR with LCALL to the IVT 2 machine cycles Maximum: 8 machine cycles When the interrupt occurs, the CPU is processing RETI, IE/IP access. The CPU should finish this instruction maximum 2 machine cycles The CPU should execute another instruction maximum 4 machine cycles (MUL/DIV) Jump to ISR with LCALL to the IVT 2 machine cycles So the interrupt response time is within 3 ~ 8 machine cycles (3 ~ 8us with 12MHz system clock). 19

20 Clear Interrupt Request (1/2) Before/After the interrupt request, the interrupt flag should be cleared, otherwise the CPU will execute the ISR again and again. How to clear: For timer overflow interrupts, once the CPU goes to execute ISR, TF0/TF1 will be cleared ( 0 ) by hardware; For serial communication interrupt, the flag need to be cleared by software in the ISR code: CLR TI or CLR RI External interrupt: o Like timer interrupts, edge-triggered external interrupts are cleared automatically (the trigger will disappear). o For level-triggered interrupts, the flags IE0/IE1 are cleared ( 0 ) once ISR is called. However, after the ISR execution, if the trigger signal is still 0, it will set IE0, IE1 again and trigger the interrupts continuously. 20

21 Clear Interrupt Request (2/2) Clear level-triggered interrupt External interrupt Can add an extra DFF (rising-edge triggered, if SD=0, Q=0; if SD=1, Q=D when there s a negative-edge on CP). When the external signal changes from 1 0, D = 0 will be loaded to INT0/ and trigger the interrupt. After ISR execution, a negative pulse can be produced on Pin P1.0 (just an example) to set Q to 1. The following code can be added to the ISR: CLR P1.0 ;set Q=1 SETB P1.0 ;enable next interrupt 21

22 Program with Interrupt Example 1 Write a program to use external interrupt 0, when there s an interrupt request from INT0/, shift R2 to the left by 1-bit and send the result to Port 1. Assembly implementation: ORG 0000H LJMP MAIN ORG 0003H LJMP INP0 ORG 0030H MAIN: MOV SP, #6FH SETB IT0 CLR PX0 SETB EX0 SETB EA.. SJMP $ INP0: PUSH ACC MOV A,R2 RL A MOV P1,A XCH A,R2 POP A RETI END ; IVT for INT0 ; IVT not enough to store the ISR, jump to ; another address location ; Master program ; INT0/ is edge-triggered ; INT0/ is with low-priority ; Enable INT0/ interrupt ; Enable the system interrupt ; Field protection ; Interrupt function process ; Store the new data ; Field recovery ; Return to master program 22

23 External Interrupt Extension Only 2 external interrupts in 8051, what if more devices are connected and all of them need to trigger the CPU to request service? Use an OR gate to connect all the interrupt sources to trigger an interrupt, then use the Port to decide which device is the real source. ORG 0013H ;INT1 IVT LJMP INT1 INT1: PUSH PSW ;Field protection PUSH ACC JB P1.0,IR1 ;P0.0 high,ir1 is the source JB P1.1,IR2 ;P0.1 high,ir1 is the source JB P1.2,IR3 ;P0.2 high,ir1 is the source JB P1.3,IR4 ;P0.3 high,ir1 is the source INTIR: POP ACC ;Field recovery POP PSW IR1: IR2: IR3: IR4: RETI IR1 ISR AJMP INTIR IR2 ISR AJMP INTIR IR3 ISR AJMP INTIR IR4 ISR AJMP INTIR ;Return 23

24 Typical Program with Interrupts ORG 0000H LJMP MAIN ORG IVT LJMP INTP ORG XXXXH MAIN: Master Program INTP: ISR ; program to process the interrupt 24

25 Program with Interrupt Example 2 Figure on the right is a fault display system. When there s no faults, X1~X3 are Low and the LED1~LED3 are off. Once fault happens, the corresponding signal of X1~X3 will be high. Please write a program to light up the corresponding LED for the fault channel. Assembly implementation: ORG 0000H SJMP MAIN ORG 0003H SJMP INT0P ;ISR ORG 0030H MAIN: SETB EX0 ;Enable INT0/ SETB IT0 ;Negative edge trigger SETB EA ;Enable interrupt system SJMP $ ;Wait for interrupt INT0P: JNB P1.0,L1 ;X1 no fault, goes to L1 CLR P1.3 ;if X1 fault, LED1 on AJMP N1 L1: SETB P1.3 ;X1 no fault, LED1 off N1: JNB P1.1,L2 ;X2 no fault, goes to L2 CLR P1.4 ;if X2 fault, LED2 on AJMP N2 L2: SETB P1.4 ;X2 no fault, LED2 off N2: JNB P1.2,L3 ;X3 no fault, goes to L3 CLR P1.5 ;if X3 fault, LED3 on AJMP N3 L3: SETB P1.5 ;X3 no fault, LED3 off N3: RETI END 25

8051 Interrupt Organization

Interrupt Interrupts of 8051 Introduction 8051 Interrupt organization Processing Interrupts Program Design Using Interrupts Timer Interrupts Serial Port Interrupts External Interrupts Interrupt Timings