Am29LV116D. 16 Megabit (2 M x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS

Transcription

1 Am29LV116D 16 Megabit (2 M x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS Single power supply operation 2.7 to 3.6 volt read and write operations for battery-powered applications Manufactured on 0.23 µm process technology Compatible with and replaces Am29LV116B device High performance Access times as fast as 70 ns Ultra low power consumption (typical values at 5MHz) 200 na Automatic Sleep mode current 200 na standby mode current 9 ma read current 15 ma program/erase current Flexible sector architecture One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-one 64 Kbyte sectors Supports full chip erase Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors Unlock Bypass Program Command Reduces overall programming time when issuing multiple program command sequences Top or bottom boot block configurations available Embedded Algorithms Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors Embedded Program algorithm automatically writes and verifies data at specified addresses Minimum 1,000,000 write cycle guarantee per sector 20-year data retention at 125 C Reliable operation for the life of the system Package option 40-pin TSOP CFI (Common Flash Interface) compliant Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices Compatibility with JEDEC standards Pinout and software compatible with singlepower supply Flash Superior inadvertent write protection Data# Polling and toggle bits Provides a software method of detecting program or erase operation completion Ready/Busy# pin (RY/BY#) Provides a hardware method of detecting program or erase cycle completion Erase Suspend/Erase Resume Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation Hardware reset pin (RESET#) Hardware method to reset the device to reading array data This Data Sheet states AMD s current technical specifications regarding the Product described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# Rev: E Amendment/+1 Issue Date: November 7, 2000

2 GENERAL DESCRIPTION The Am29LV116D is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes. The device is offered in a 40-pin TSOP package. The byte-wide (x8) data appears on DQ7 DQ0. All read, program, and erase operations are accomplished using only a single power supply. The device can also be programmed in standard EPROM programmers. The standard device offers access times of 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. 2 Am29LV116D

3 TABLE OF CONTENTS Product Selector Guide Connection Diagrams Pin Configuration Logic Symbol Ordering Information Standard Products... 7 Device Bus Operations Table 1. Am29LV116D Device Bus Operations...8 Requirements for Reading Array Data... 8 Writing Commands/Command Sequences... 8 Program and Erase Operation Status... 9 Standby Mode... 9 Automatic Sleep Mode... 9 RESET#: Hardware Reset Pin... 9 Output Disable Mode... 9 Table 2. Am29LV116DT Top Boot Sector Address Table...10 Table 3. Am29LV116DB Bottom Boot Sector Address Table...11 Autoselect Mode Table 4. Am29LV116D Autoselect Codes (High Voltage Method)..12 Sector Protection/Unprotection Temporary Sector Unprotect Figure 1. In-System Sector Protect/Unprotect Algorithms Figure 2. Temporary Sector Unprotect Operation Hardware Data Protection Low V CC Write Inhibit Write Pulse Glitch Protection Logical Inhibit Power-Up Write Inhibit Common Flash Memory Interface (CFI) Table 5. CFI Query Identification String...15 Table 6. System Interface String...15 Table 7. Device Geometry Definition...16 Table 8. Primary Vendor-Specific Extended Query...16 Command Definitions Reading Array Data Reset Command Autoselect Command Sequence Byte Program Command Sequence Unlock Bypass Command Sequence Figure 3. Program Operation Chip Erase Command Sequence Sector Erase Command Sequence Erase Suspend/Erase Resume Commands Figure 4. Erase Operation Command Definitions Table 9. Am29LV116D Command Definitions...21 Write Operation Status DQ7: Data# Polling Figure 5. Data# Polling Algorithm RY/BY#: Ready/Busy# DQ6: Toggle Bit I DQ2: Toggle Bit II Reading Toggle Bits DQ6/DQ DQ5: Exceeded Timing Limits DQ3: Sector Erase Timer Figure 6. Toggle Bit Algorithm Table 10. Write Operation Status Absolute Maximum Ratings Figure 7. Maximum Negative Overshoot Waveform Figure 8. Maximum Positive Overshoot Waveform Operating Ranges DC Characteristics CMOS Compatible Zero Power Flash Figure 9. I CC1 Current vs. Time (Showing Active and Automatic Sleep Currents) Figure 10. Typical I CC1 vs. Frequency Test Conditions Figure 11. Test Setup Table 11. Test Specifications Key to Switching Waveforms Figure 12. Input Waveforms and Measurement Levels AC Characteristics Read Operations Figure 13. Read Operations Timings Hardware Reset (RESET#) Figure 14. RESET# Timings Erase/Program Operations Figure 15. Program Operation Timings Figure 16. Chip/Sector Erase Operation Timings Figure 17. Data# Polling Timings (During Embedded Algorithms). 34 Figure 18. Toggle Bit Timings (During Embedded Algorithms) Figure 19. DQ2 vs. DQ Temporary Sector Unprotect Figure 20. Temporary Sector Unprotect Timing Diagram Figure 21. Sector Protect/Unprotect Timing Diagram Figure 22. Alternate CE# Controlled Write Operation Timings Erase and Programming Performance Latchup Characteristics TSOP Pin Capacitance Data Retention Physical Dimensions TS Pin Standard TSOP TSR Pin Reverse TSOP Revision Summary Revision A (October 1997) Revision B (October 1997) Revision C (December 1997) Revision C+1 (January 1998) Revision C+2 (March 1998) Revision C+3 (August 1998) Revision D (January 1999) Revision E (February 2, 2000) Revision E+1 (November 7, 2000) Am29LV116D 3

4 PRODUCT SELECTOR GUIDE Family Part Number Am29LV116D Speed Options V CC = V Max access time, ns (t ACC ) Max CE# access time, ns (t CE ) Max OE# access time, ns (t OE ) Note: See AC Characteristics for full specifications. BLOCK DIAGRAM V CC V SS RESET# RY/BY# Sector Switches Erase Voltage Generator DQ0 DQ7 Input/Output Buffers WE# State Control CE# OE# Command Register PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch STB Y-Decoder Y-Gating A0 A20 V CC Detector Timer Address Latch X-Decoder Cell Matrix 4 Am29LV116D

5 Am29LV116D 5 CONNECTION DIAGRAMS A16 A5 A15 A14 A13 A12 A11 A9 A8 WE# RESET# NC RY/BY# A18 A7 A6 A4 A3 A2 A1 A17 DQ0 V SS A20 A19 A10 DQ7 DQ6 DQ5 OE# V SS CE# A0 DQ4 V CC V CC NC DQ3 DQ2 DQ A16 A5 A15 A14 A13 A12 A11 A9 A8 WE# RESET# NC RY/BY# A18 A7 A6 A4 A3 A2 A1 A17 DQ0 V SS A20 A19 A10 DQ7 DQ6 DQ5 OE# V SS CE# A0 DQ4 V CC V CC NC DQ3 DQ2 DQ1 40-Pin Reverse TSOP 40-Pin Standard TSOP

6 PIN CONFIGURATION LOGIC SYMBOL A0 A20 = 21 addresses DQ0 DQ7 = 8 data inputs/outputs CE# = Chip enable 21 A0 A20 DQ0 DQ7 8 OE# = Output enable WE# = Write enable CE# RESET# = Hardware reset pin, active low OE# RY/BY# = Ready/Busy output WE# V CC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) RESET# RY/BY# V SS = Device ground NC = Pin not connected internally 6 Am29LV116D

7 ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am29LV116D T -70 E C TEMPERATURE RANGE C = Commercial (0 C to +70 C) I = Industrial ( 40 C to +85 C) PACKAGE TYPE E = 40-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 040) F = 40-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR040) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top Sector B = Bottom Sector DEVICE NUMBER/DESCRIPTION Am29LV116D 16 Megabit (2 M x 8-Bit) CMOS Flash Memory 3.0 Volt-only Read, Program and Erase Am29LV116DT-70, Am29LV116DB-70 Am29LV116DT-90, Am29LV116DB-90 Valid Combinations EC, EI, FC, FI Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29LV116DT-120, Am29LV116DB-120 Am29LV116D 7

8 DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. Am29LV116D Device Bus Operations Operation CE# OE# WE# RESET# Addresses DQ0 DQ7 Read L L H H A IN D OUT Write L H L H A IN D IN Standby V CC ± V X X CC ± 0.3 V 0.3 V X High-Z Output Disable L H H H X High-Z Reset X X X L X High-Z Sector Addresses, Sector Protect (See Note) L H L V ID A6 = L, A1 = H, A0 = L D IN, D OUT Sector Unprotect (See Note) L H L V ID Sector Addresses A6 = H, A1 = H, A0 = L D IN, D OUT Temporary Sector Unprotect X X X V ID A IN D IN Legend: L = Logic Low = V IL, H = Logic High = V IH, V ID = 12.0 ± 0.5 V, X = Don t Care, A IN = Address In, D IN = Data In, D OUT = Data Out Note: The sector protect and sector unprotect functions may also be implemented via programming equipment. See the Sector Protection/Unprotection section. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to V IL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at V IH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See Reading Array Data for more information. Refer to the AC Read Operations table for timing specifications and to Figure 13 for the timing diagram. I CC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to V IH. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a byte, instead of four. The Byte Program Command Sequence section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A sector address consists of the address bits required to uniquely select a sector. The Command Definitions section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7 DQ0. Standard read cycle timings apply in this 8 Am29LV116D

9 mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information. I CC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7 DQ0. Standard read cycle timings and I CC read specifications apply. Refer to Write Operation Status for more information, and to AC Characteristics for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at V IH, but not within V CC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE ) for read access when the device is in either of these standby modes, before it is ready to read data. The device also enters the standby mode when the RE- SET# pin is driven low. Refer to the next section, RE- SET#: Hardware Reset Pin. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. I CC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I CC5 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RE- SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS ±0.3 V, the device draws CMOS standby current (I CC4 ). If RESET# is held at V IL but not within V SS ±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is 1 ), the reset operation is completed within a time of t READY (not during Embedded Algorithms). The system can read data t RH after the RE- SET# pin returns to V IH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 14 for the timing diagram. Output Disable Mode When the OE# input is at V IH, output from the device is disabled. The output pins are placed in the high impedance state. Am29LV116D 9

10 Table 2. Am29LV116DT Top Boot Sector Address Table Sector A20 A19 A18 A17 A16 A15 A14 A13 Sector Size (Kbytes) Address Range (in hexadecimal) SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X 64 0A0000 0AFFFF SA X X X 64 0B0000 0BFFFF SA X X X 64 0C0000 0CFFFF SA X X X 64 0D0000 0DFFFF SA X X X 64 0E0000 0EFFFF SA X X X 64 0F0000 0FFFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X 64 1A0000 1AFFFF SA X X X 64 1B0000 1BFFFF SA X X X 64 1C0000 1CFFFF SA X X X 64 1D0000 1DFFFF SA X X X 64 1E0000 1EFFFF SA X X 32 1F0000 1F7FFF SA F8000 1F9FFF SA FA000 1FBFFF SA X 16 1FC000 1FFFFF 10 Am29LV116D

11 Table 3. Am29LV116DB Bottom Boot Sector Address Table Sector A20 A19 A18 A17 A16 A15 A14 A13 Sector Size (Kbytes) Address Range (in hexadecimal) SA X FFF SA FFF SA FFF SA X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X 64 0A0000 0AFFFF SA X X X 64 0B0000 0BFFFF SA X X X 64 0C0000 0CFFFF SA X X X 64 0D0000 0DFFFF SA X X X 64 0E0000 0EFFFF SA X X X 64 0F0000 0FFFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X FFFF SA X X X 64 1A0000 1AFFFF SA X X X 64 1B0000 1BFFFF SA X X X 64 1C0000 1CFFFF SA X X X 64 1D0000 1DFFFF SA X X X 64 1E0000 1EFFFF SA X X X 64 1F0000 1FFFFF Am29LV116D 11

12 Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7 DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires V ID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 4. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Tables 2 and 3). Table 4 shows the remaining address bits that are don t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 9. This method does not require V ID. See Command Definitions for details on using the autoselect mode. Table 4. Am29LV116D Autoselect Codes (High Voltage Method) Description CE# OE# WE# A20 to A13 A12 to A10 A9 A8 to A7 A6 A5 to A2 A1 A0 DQ7 to DQ0 Manufacturer ID: AMD L L H X X V ID X L X L L 01h Device ID: Am29LV116D (Top Boot Block) Device ID: Am29LV116D (Bottom Boot Block) L L H X X V ID X L X L H C7h L L H X X V ID X L X L H 4Ch Sector Protection Verification L L H SA X V ID X L X H L 01h (protected) (unprotected) L = Logic Low = V IL, H = Logic High = V IH, SA = Sector Address, X = Don t care. Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented via two methods. The primary method requires V ID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 1 shows the algorithms and Figure 21 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The alternate method intended only for programming equipment requires V ID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only AMD flash devices. Publication number contains further details; contact an AMD representative to request a copy. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD s ExpressFlash Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode for details. Temporary Sector Unprotect This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RE- SET# pin to V ID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once V ID is removed from the RE- SET# pin, all the previously protected sectors are protected again. Figure 2 shows the algorithm, and Figure 20 shows the timing diagrams, for this feature. 12 Am29LV116D

13 START START Temporary Sector Unprotect Mode No PLSCNT = 1 RESET# = V ID Wait 1 µs First Write Cycle = 60h? Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address PLSCNT = 1 RESET# = V ID Wait 1 µs First Write Cycle = 60h? No Temporary Sector Unprotect Mode Yes Yes Set up sector address Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 No All sectors protected? Yes Set up first sector address Increment PLSCNT Wait 150 µs Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Reset PLSCNT = 1 Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0 Wait 15 ms No Read from sector address with A6 = 0, A1 = 1, A0 = 0 Increment PLSCNT Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0 PLSCNT = 25? Yes Device failed No Data = 01h? Yes Protect another sector? Yes No PLSCNT = 1000? No Read from sector address with A6 = 1, A1 = 1, A0 = 0 Data =? Set up next sector address No Yes Yes Remove V ID from RESET# Device failed Last sector verified? No Write reset command Yes Sector Protect Algorithm Sector Protect complete Sector Unprotect Algorithm Remove V ID from RESET# Write reset command Sector Unprotect complete Figure 1. In-System Sector Protect/Unprotect Algorithms Am29LV116D 13

14 Figure 2. START RESET# = V ID (Note 1) Perform Erase or Program Operations RESET# = V IH Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again. Temporary Sector Unprotect Operation Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 9 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low V CC Write Inhibit When V CC is less than V LKO, the device does not accept any write cycles. This protects data during V CC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until V CC is greater than V LKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than V LKO. Write Pulse Glitch Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = V IL, CE# = V IH or WE# = V IH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = V IL and OE# = V IH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 5 8. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 5 8. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at Alternatively, contact an AMD representative for copies of these documents. 14 Am29LV116D

15 Table 5. CFI Query Identification String Addresses Data Description 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 51h 52h 59h 02h 40h Query Unique ASCII string QRY Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set ( = none exists) Address for Alternate OEM Extended Table ( = none exists) Table 6. System Interface String Addresses Data Description 1Bh 1Ch 27h 36h V CC Min. (write/erase) D7 D4: volt, D3 D0: 100 millivolt V CC Max. (write/erase) D7 D4: volt, D3 D0: 100 millivolt 1Dh V PP Min. voltage ( = no V PP pin present) 1Eh V PP Max. voltage ( = no V PP pin present) 1Fh 04h Typical timeout per single byte/word write 2 N µs 20h Typical timeout for Min. size buffer write 2 N µs ( = not supported) 21h 0Ah Typical timeout per individual block erase 2 N ms 22h Typical timeout for full chip erase 2 N ms ( = not supported) 23h 05h Max. timeout for byte/word write 2 N times typical 24h Max. timeout for buffer write 2 N times typical 25h 04h Max. timeout per individual block erase 2 N times typical 26h Max. timeout for full chip erase 2 N times typical ( = not supported) Am29LV116D 15

16 Table 7. Device Geometry Definition Addresses Data Description 27h 15h Device Size = 2 N byte 28h 29h 2Ah 2Bh Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2 N ( = not supported) 2Ch 04h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 40h 01h 20h 80h 1Eh 01h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 2 Information Erase Block Region 3 Information Erase Block Region 4 Information Table 8. Primary Vendor-Specific Extended Query Addresses Data Description 40h 41h 42h 50h 52h 49h Query-unique ASCII string PRI 43h 31h Major version number, ASCII 44h 30h Minor version number, ASCII 45h 46h 47h 02h 01h Address Sensitive Unlock 0 = Required, 1 = Not Required Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 01h Sector Temporary Unprotect: 00 = Not Supported, 01 = Supported 49h 04h Sector Protect/Unprotect scheme 01 = 29F040 mode, 02 = 29F016 mode, 03 = 29F400 mode, 04 = 29LV800A mode 4Ah Simultaneous Operation: 00 = Not Supported, 01 = Supported 4Bh Burst Mode Type: 00 = Not Supported, 01 = Supported 4Ch Page Mode Type: 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 16 Am29LV116D

17 COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 9 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the AC Characteristics section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See Erase Suspend/Erase Resume Commands for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the Reset Command section, next. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read Operations table provides the read parameters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don t care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table 9 shows the address and data requirements. This method is an alternative to that shown in Table 4, which is intended for PROM programmers and requires V ID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h returns 01h if that sector is protected, or if it is unprotected. Refer to Tables 2 and 3 for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Byte Program Command Sequence The device programs one byte of data for each program operation. The command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 9 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See Write Operation Status for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Byte Program command se- Am29LV116D 17

18 quence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a 0 back to a 1. Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still 0. Only erase operations can convert a 0 to a 1. Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 9 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data. Addresses are don t cares for both cycles. The device then returns to reading array data. Figure 3 illustrates the algorithm for the program operation. See the Erase/Program Operations table in AC Characteristics for parameters, and to Figure 15 for timing diagrams Increment Address Embedded Program algorithm in progress Note: See Table 9 for program command sequence. Figure 3. No START Write Program Command Sequence Data Poll from System Verify Data? Program Operation Chip Erase Command Sequence Yes Last Address? Yes Programming Completed Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 9 shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. No 18 Am29LV116D

19 The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Write Operation Status for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in AC Characteristics for parameters, and to Figure 16 for timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table 9 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the DQ3: Sector Erase Timer section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to Write Operation Status for information on these status bits.) Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the AC Characteristics section for parameters, and to Figure 16 for timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the time-out period 50 µs during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are don t-cares when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device erase suspends all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7 DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation Status for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the Am29LV116D 19

20 device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence for more information. The system must write the Erase Resume command (address bits are don t care ) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. No START Write Erase Command Sequence Data Poll from System Data = FFh? Embedded Erase algorithm in progress Yes Erasure Completed Notes: 1. See Table 9 for erase command sequence. 2. See DQ3: Sector Erase Timer for more information. Figure 4. Erase Operation 20 Am29LV116D

21 Command Definitions Autoselect (Note 7) Cycles Table 9. Am29LV116D Command Definitions Bus Cycles (Notes 2 4) Command Sequence (Note 1) First Second Third Fourth Fifth Sixth Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read (Note 5) 1 RA RD Reset (Note 6) 1 XXX F0 Manufacturer ID AA 2AA X00 01 Device ID, C7 Top Boot Block AA 2AA X01 Device ID, 4C Bottom Boot Block Sector Protect SA AA 2AA Verify (Note 8) X02 01 CFI Query (Note 9) Byte Program AA 2AA A0 PA PD Unlock Bypass AA 2AA Unlock Bypass Program (Note 10) 2 XXX A0 PA PD Unlock Bypass Reset (Note 11) 2 XXX 90 XXX 00 Chip Erase AA 2AA AA 2AA Sector Erase AA 2AA AA 2AA 55 SA 30 Erase Suspend (Note 12) 1 XXX B0 Erase Resume (Note 13) 1 XXX 30 Legend: X = Don t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE# or CE# pulse. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# pulse. SA = Address of the sector to be erased or verified. Address bits A20 A13 uniquely select any sector. Notes: 1. See Table 1 for descriptions of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all bus cycles are write operations. 4. Address bits A20 A11 are don t care for unlock and command cycles, except when PA or SA is required. 5. No unlock or command cycles required when device is in read mode. 6. The Reset command is required to return to the read mode when the device is in the autoselect mode or if DQ5 goes high. 7. The fourth cycle of the autoselect command sequence is a read cycle. 8. The data is for an unprotected sector and 01h for a protected sector. 9. Command is valid when device is ready to read array data or when device is in autoselect mode. 10. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 11. The Unlock Bypass Reset command is required to return to reading array data when the device is in the Unlock Bypass mode. 12. The system may read and program functions in nonerasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 13. The Erase Resume command is valid only during the Erase Suspend mode. Am29LV116D 21