32-megabit (2M x 16/4M x 8) 3-volt Only Flash Memory AT49BV322D AT49BV322DT

Transcription

1 Features Single Voltage Read/Write Operation: 2.65V to 3.6V Access Time 70 ns Sector Erase Architecture Sixty-three 32K Word (64K Bytes) Sectors with Individual Write Lockout Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout Fast Word Program Time 10 µs Fast Sector Erase Time 100 ms Suspend/Resume Feature for Erase and Program Supports Reading and Programming from Any Sector by Suspending Erase of a Different Sector Supports Reading Any Byte/Word in the Non-suspending Sectors by Suspending Programming of Any Other Byte/Word Low-power Operation 10 ma Active 15 µa Standby Data Polling, Toggle Bit, Ready/Busy for End of Program Detection VPP Pin for Write Protection and Accelerated Program Operation RESET Input for Device Initialization Sector Lockdown Support TSOP and CBGA Package Options Top or Bottom Boot Block Configuration Available 128-bit Protection Register Minimum 100,000 Erase Cycles Common Flash Interface (CFI) 32-megabit (2M x 16/4M x 8) 3-volt Only Flash Memory AT49BV322D AT49BV322DT 1. Description The is a 2.7-volt 32-megabit Flash memory organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. The x16 data appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 71 sectors for erase operations. The device is offered in a 48-lead TSOP and a 48-ball CBGA package. The device has CE and OE control signals to avoid any bus contention. This device can be read or reprogrammed using a single power supply, making it ideally suited for in-system programming. The device powers on in the read mode. Command sequences are used to place the device in other operation modes such as program and erase. The device has the capability to protect the data in any sector (see Sector Lockdown on page 7). To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend feature. This feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the memory. The end of a program or an erase cycle is detected by the READY/BUSY pin, Data Polling or by the toggle bit.

2 The VPP pin provides data protection. When the V PP input is below 0.4V, the program and erase functions are inhibited. When V PP is at 1.65V or above, normal program and erase operations can be performed. With V PP at 10.0V, the program (Dual-word Program command) operation is accelerated. A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement of entering the three-byte program sequence is offered to further improve programming time. After entering the six-byte code, only single pulses on the write control lines are required for writing into the device. This mode (Single Pulse Byte/Word Program) is exited by powering down the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing it back to V CC. Erase, Erase Suspend/Resume and Program Suspend/Resume commands will not work while in this mode; if entered they will result in data being programmed into the device. It is not recommended that the six-byte code reside in the software of the final product but only exist in external programming code. The BYTE pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE pin is set at logic 1, the device is in word configuration, I/O0 - I/O15 are active and controlled by CE and OE. If the BYTE pin is set at logic 0, the device is in byte configuration, and only data I/O pins I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14 are tri-stated, and the I/O15 pin is used as an input for the LSB (A-1) address function. 2

3 2. Pin Configurations Pin Name A0 - A20 CE OE WE RESET RDY/BUSY VPP I/O0 - I/O14 I/O15 (A-1) BYTE NC Function Addresses Chip Enable Output Enable Write Enable Reset READY/BUSY Output Write Protection Data Inputs/Outputs I/O15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode) Selects Byte or Word Mode No Connect 2.1 TSOP Top View (Type 1) A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET NC VPP RDY/BUSY A18 A17 A7 A6 A5 A4 A3 A2 A A16 BYTE GND I/O15/A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE GND CE A0 2.2 CBGA Top View (Ball Down) A B A3 A7 RDY/BUSY WE A9 A13 C A4 A17 VPP RST A8 A12 D A2 A6 A18 NC A10 A14 E A1 A5 A20 A19 A11 A15 F A0 I/O0 I/O2 I/O5 I/O7 A16 G CE I/O8 I/O10 I/O12 I/O14 BYTE H OE I/O9 I/O11 VCC I/O13 I/015/A-1 VSS I/O1 I/O3 I/O4 I/O6 VSS 3

4 3. Block Diagram I/O0 - I/O15/A-1 OUTPUT BUFFER INPUT BUFFER A0 - A20 INPUT BUFFER ADDRESS LATCH OUTPUT MULTIPLEXER IDENTIFIER REGISTER STATUS REGISTER DATA REGISTER COMMAND REGISTER CE WE OE RESET BYTE Y-DECODER DATA COMPARATOR Y-GATING WRITE STATE MACHINE PROGRAM/ERASE VOLTAGE SWITCH RDY/BUSY VPP X-DECODER MAIN MEMORY VCC GND 4. Device Operation 4.1 Command Sequences When the device is first powered on, it will be reset to the read or standby mode, depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definition Table on page 13 (I/O8 - I/O15 are don t care inputs for the command codes). The command sequences are written by applying a low pulse on the WE orce input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. 4.2 Read 4 The is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the out-

5 puts. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. 4.3 Reset 4.4 Erase Chip Erase Sector Erase A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high impedance state. When a high level is reasserted on the RESET pin, the device returns to the read or standby mode, depending upon the state of the control inputs. Before a byte/word can be reprogrammed, it must be erased. The erased state of memory bits is a logical 1. The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase command. The entire device can be erased at one time by using the six-byte chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erase the chip is t EC. If the sector lockdown has been enabled, the chip erase will not erase the data in the sector that has been locked out; it will erase only the unprotected sectors. After the chip erase, the device will return to the read or standby mode. As an alternative to a full chip erase, the device is organized into 71 sectors (SA0 - SA70) that can be individually erased. The Sector Erase command is a six-bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched on the rising edge of WE. The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. The maximum time to erase a sector is t SEC. When the sector programming lockdown feature is not enabled, the sector will erase (from the same Sector Erase command). An attempt to erase a sector that has been protected will result in the operation terminating immediately. 4.5 Byte/Word Programming Once a memory block is erased, it is programmed (to a logical 0 ) on a byte-by-byte or on a word-by-word basis. Programming is accomplished via the internal device command register and is a four-bus cycle operation. The device will automatically generate the required internal program pulses. Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data 0 cannot be programmed back to a 1 ; only erase operations can convert 0 s to 1 s. Programming is completed after the specified t BP cycle time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a program cycle. If the erase/program status bit is a 1, the device was not able to verify that the erase or program operation was performed successfully. 5

6 4.6 VPP Pin The circuitry of the is designed so that the device cannot be programmed or erased if the V PP voltage is less that 0.4V. When V PP is at 1.65V or above, normal program and erase operations can be performed. The VPP pin cannot be left floating. 4.7 Program/Erase Status The device provides several bits to determine the status of a program or erase operation: I/O2, I/O3, I/O5, I/O6 and I/O7. The Status Bit Table on page 12 and the following four sections describe the function of these bits. To provide greater flexibility for system designers, the contains a programmable configuration register. The configuration register allows the user to specify the status bit operation. The configuration register can be set to one of two different values, 00 or 01. If the configuration register is set to 00, the part will automatically return to the read mode after a successful program or erase operation. If the configuration register is set to a 01, a Product ID Exit command must be given after a successful program or erase operation before the part will return to the read mode. It is important to note that whether the configuration register is set to a 00 or to a 01, any unsuccessful program or erase operation requires using the Product ID Exit command to return the device to read mode. The default value (after power-up) for the configuration register is 00. Using the four-bus cycle Set Configuration Register command as shown in the Command Definition Table on page 13, the value of the configuration register can be changed. Voltages applied to the RESET pin will not alter the value of the configuration register. The value of the configuration register will affect the operation of the I/O7 status bit as described below Data Polling Toggle Bit The features Data Polling to indicate the end of a program cycle. If the status configuration register is set to a 00, during a program cycle an attempted read of the last byte/word loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to read the device will give a 0 on I/O7. Once the program or erase cycle has completed, true data will be read from the device. Data Polling may begin at any time during the program cycle. Please see Status Bit Table on page 12 for more details. If the status bit configuration register is set to a 01, the I/O7 status bit will be low while the device is actively programming or erasing data. I/O7 will go high when the device has completed a program or erase operation. Once I/O7 has gone high, status information on the other pins can be checked. The Data Polling status bit must be used in conjunction with the erase/program and V PP status bit as shown in the algorithm in Figures 4-1 and 4-2 on page 10. In addition to Data Polling the provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the memory will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. Please see Status Bit Table on page 12 for more details. The toggle bit status bit should be used in conjunction with the erase/program and V PP status bit as shown in the algorithm in Figures 4-3 and 4-3 on page 11. 6

7 4.7.3 Erase/Program Status Bit The device offers a status bit on I/O5, which indicates whether the program or erase operation has exceeded a specified internal pulse count limit. If the status bit is a 1, the device is unable to verify that an erase or a byte/word program operation has been successfully performed. If a program (Sector Erase) command is issued to a protected sector, the protected sector will not be programmed (erased). The device will go to a status read mode and the I/O5 status bit will be set high, indicating the program (erase) operation did not complete as requested. Once the erase/program status bit has been set to a 1, the system must write the Product ID Exit command to return to the read mode. The erase/program status bit is a 0 while the erase or program operation is still in progress. Please see Status Bit Table on page 12 for more details VPP Status Bit The provides a status bit on I/O3, which provides information regarding the voltage level of the VPP pin. During a program or erase operation, if the voltage on the VPP pin is not high enough to perform the desired operation successfully, the I/O3 status bit will be a 1. Once the V PP status bit has been set to a 1, the system must write the Product ID Exit command to return to the read mode. On the other hand, if the voltage level is high enough to perform a program or erase operation successfully, the V PP status bit will output a 0. Please see Status Bit Table on page 12 for more details. 4.8 Sector Lockdown Each sector has a programming lockdown feature. This feature prevents programming of data in the designated sectors once the feature has been enabled. These sectors can contain secure code that is used to bring up the system. Enabling the lockdown feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; any sector s usage as a write-protected region is optional to the user. At power-up or reset, all sectors are unlocked. To activate the lockdown for a specific sector, the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked down, the contents of the sector is read-only and cannot be erased or programmed Sector Lockdown Detection A software method is available to determine if programming of a sector is locked down. When the device is in the software product identification mode (see Software Product Identification Entry/Exit sections on page 26), a read from address location 00002H within a sector will show if programming the sector is locked down. If the data on I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program lockdown feature has been enabled and the sector cannot be programmed. The software product identification exit code should be used to return to standard operation. 7

8 4.8.2 Sector Lockdown Override The only way to unlock a sector that is locked down is through reset or power-up cycles. After power-up or reset, the content of a sector that is locked down can be erased and reprogrammed. 4.9 Erase Suspend/Erase Resume The Erase Suspend command allows the system to interrupt a sector or chip erase operation and then program or read data from a different sector within the memory. After the Erase Suspend command is given, the device requires a maximum time of 15 µs to suspend the erase operation. After the erase operation has been suspended, the system can then read data or program data to any other sector within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the system must write the Erase Resume command. The Erase Resume command is a one-bus cycle command. The device also supports an erase suspend during a complete chip erase. While the chip erase is suspended, the user can read from any sector within the memory that is protected. The command sequence for a chip erase suspend and a sector erase suspend are the same Program Suspend/Program Resume The Program Suspend command allows the system to interrupt a programming operation and then read data from a different byte/word within the memory. After the Program Suspend command is given, the device requires a maximum of 20 µs to suspend the programming operation. After the programming operation has been suspended, the system can then read data from any other byte/word that is not contained in the sector in which the programming operation was suspended. An address is not required during the program suspend operation. To resume the programming operation, the system must write the Program Resume command. The program suspend and resume are one-bus cycle commands. The command sequence for the erase suspend and program suspend are the same, and the command sequence for the erase resume and program resume are the same Product Identification The product identification mode identifies the device and manufacturer as Atmel. It is accessed using a software operation. For details, see Operating Modes on page 19 or Software Product Identification Entry/Exit sections on page bit Protection Register The contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number. The data in block B is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the four-bus cycle Program Protection Register command must be used as shown in the Command Definition Table on page 13. To lock out block B, the four-bus cycle Lock Protection Register command must be used as shown in the Command Definition Table. Data bit D1 must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are don t cares. To determine whether block B is locked out, the Product ID Entry command is given followed by a read operation from address 80H. If data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be reprogrammed. Please see the Protection Register 8

9 Addressing Table (1)(2)(3) on page 14 for the address locations in the protection register. To read the protection register, the Product ID Entry command is given followed by a normal read operation from an address within the protection register. After determining whether block B is protected or not, or reading the protection register, the Product ID Exit command must be given prior to performing any other operation RDY/BUSY An open-drain READY/BUSY output pin provides another method of detecting the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. The open-drain connection allows for ORtying of several devices to the same RDY/BUSY line. Please see Status Bit Table on page 12 for more details Common Flash Interface (CFI) CFI is a published, standardized data structure that may be read from a flash device. CFI allows system software to query the installed device to determine the configurations, various electrical and timing parameters, and functions supported by the device. CFI is used to allow the system to learn how to interface to the flash device most optimally. The two primary benefits of using CFI are ease of upgrading and second source availability. The command to enter the CFI Query mode is a one-bus cycle command which requires writing data 98h to address 55h. The CFI Query command can be written when the device is ready to read data or can also be written when the part is in the product ID mode. Once in the CFI Query mode, the system can read CFI data at the addresses given in Common Flash Interface Definition Table on page 27. To exit the CFI Query mode, the product ID exit command must be given Hardware Data Protection The Hardware Data Protection feature protects against inadvertent programs to the in the following ways: (a) V CC sense: if V CC is below 1.8V (typical), the program function is inhibited. (b) V CC power-on delay: once V CC has reached the V CC sense level, the device will automatically time out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Program inhibit: V PP is less than V ILPP Input Levels While operating with a 2.65V to 3.6V power supply, the address inputs and control inputs (OE, CE andwe) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to V CC + 0.6V. 9

10 Figure 4-1. Data Polling Algorithm (Configuration Register = 00) Figure 4-2. Data Polling Algorithm (Configuration Register = 01) START START Read I/O7 - I/O0 Addr = VA Read I/O7 - I/O0 Addr = VA I/O7 = Data? YES I/O7 = Data? YES NO NO NO I/O3, I/O5 = 1? NO I/O3, I/O5 = 1? YES YES Read I/O7 - I/O0 Addr = VA Read I/O7 - I/O0 Addr = VA I/O7 = Data? YES I/O7 = Data? YES NO NO Program/Erase Operation Not Successful, Write Product ID Exit Command Program/Erase Operation Successful, Device in Read Mode Program/Erase Operation Not Successful, Write Product ID Exit Command Program/Erase Operation Successful, Write Product ID Exit Command Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. I/O7 should be rechecked even if I/O5 = 1 because I/O7 may change simultaneously with I/O5. Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. I/O7 should be rechecked even if I/O5 = 1 because I/O7 may change simultaneously with I/O5. 10

11 Figure 4-3. Toggle Bit Algorithm (Configuration Register = 00) Figure 4-4. Toggle Bit Algorithm (Configuration Register = 01) START START Read I/O7 - I/O0 Read I/O7 - I/O0 Read I/O7 - I/O0 Read I/O7 - I/O0 Toggle Bit = Toggle? NO Toggle Bit = Toggle? NO YES YES NO I/O3, I/O5 = 1? NO I/O3, I/O5 = 1? YES YES Read I/O7 - I/O0 Twice Read I/O7 - I/O0 Twice Toggle Bit = Toggle? NO Toggle Bit = Toggle? NO YES Program/Erase Operation Not Successful, Write Product ID Exit Command Program/Erase Operation Successful, Device in Read Mode YES Program/Erase Operation Not Successful, Write Product ID Exit Command Program/Erase Operation Successful, Write Product ID Exit Command Note: 1. The system should recheck the toggle bit even if I/O5 = 1 because the toggle bit may stop toggling as I/O5 changes to 1. Note: 1. The system should recheck the toggle bit even if I/O5 = 1 because the toggle bit may stop toggling as I/O5 changes to 1. 11

12 5. Status Bit Table Status Bit I/O7 I/O7 I/O6 I/O5 (1) I/O3 (2) I/O2 RDY/BUSY Configuration Register /01 00/01 00/01 00/01 00/01 Programming I/O7 0 TOGGLE Erasing 0 0 TOGGLE 0 0 TOGGLE 0 Erase Suspended & Read Erasing Sector Erase Suspended & Read Non-erasing Sector Erase Suspended & Program Non-erasing Sector Erase Suspended & Program Suspended and Reading from Nonsuspended Sectors Program Suspended & Read Programming Sector TOGGLE 1 DATA DATA DATA DATA DATA DATA 1 I/O7 0 TOGGLE 0 0 TOGGLE 0 DATA DATA DATA DATA DATA DATA 1 I/O TOGGLE 1 Program Suspended & Read Non-programming Sector DATA DATA DATA DATA DATA DATA 1 Notes: 1. I/O5 switches to a 1 when a program or an erase operation has exceeded the maximum time limits or when a program or sector erase operation is performed on a protected sector. 2. I/O3 switches to a 1 when the V PP level is not high enough to successfully perform program and erase operations. 12

13 6. Command Definition Table Command Sequence Bus Cycles 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read 1 Addr D OUT Chip Erase AA AAA (2) AA AAA Sector Erase AA AAA AA AAA 55 SA (3) 30 Byte/Word Program AA AAA A0 Addr D IN Dual Byte/Word Program (4) AA AAA E0 Addr0 D IN0 Addr1 D IN1 Enter Single Pulse Program Mode Single Pulse Byte/Word Program AA AAA AA AAA A0 1 Addr D IN Sector Lockdown AA AAA (2) AA AAA 55 SA (3)(5) 60 Erase/Program Suspend Erase/Program Resume 1 XXX B0 1 XXX 30 Product ID Entry AA AAA Product ID Exit (6) AA AAA F0 (7) Product ID Exit (6) 1 XXX F0 (7) Program Protection Register Lock Protection Register - Block B Status of Block B Protection Set Configuration Register AA AAA C0 Addr (8) D IN AA AAA C0 080 X AA AAA (9) D OUT AA AAA D0 XXX 00/01 (10) CFI Query (11) 1 X55 98 Notes: 1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). In word operation I/O15 - I/O8 are don t care. The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A20 through A11 are don t care in the word mode. Address A20 through A11 and A-1 are don t care in the byte mode. 2. Since A11 is a Don t Care, AAA can be replaced with 2AA. 3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see pages for details). 4. This fast programming option enables the user to program two words in parallel only when V PP = 9.5V. The Addresses, Addr0 and Addr1, of the two words, D IN0 and D IN1, must only differ in address A0. This command should be used during manufacturing purposes only. 5. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power cycled. 6. Either one of the Product ID Exit commands can be used. 7. Bytes of data other than F0 may be used to exit the Product ID mode. However, it is recommended that F0 be used. 8. Any addresses within the user programmable protection register region. Address locations are shown on Protection Register Addressing Table (1)(2)(3) on page If data bit D1 is 0, block B is locked. If data bit D1 is 1, block B can be reprogrammed. 10. The default state (after power-up) of the configuration register is When accessing the data in the CFI table, the address format is A15 - A0 (Hex) in the word mode and A14 - A1 (Hex) in the byte mode. 13

14 7. Absolute Maximum Ratings* Temperature under Bias C to +125 C Storage Temperature C to +150 C All Input Voltages (including NC Pins) with Respect to Ground V to +6.25V All Output Voltages with Respect to Ground V to V CC + 0.6V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on V PP with Respect to Ground V to + 9.5V 8. Protection Register Addressing Table (1)(2)(3) Address Use Block A7 A6 A5 A4 A3 A2 A1 A0 81 Factory A Factory A Factory A Factory A User B User B User B User B Notes: 1. All address lines not specified in the above table must be 0 when accessing the protection register, i.e., A20 - A8 = The addressing shown above should be used when the device is operating in the word (x16) mode. 3. In the byte (x8) mode, A-1 should be used when addressing the protection register: with A-1 = 0, the LSB of the address location can be accessed; and with A-1 = 1, the MSB of the address location can be accessed 14

15 9. AT49BV322D Sector Address Table Sector Size (Bytes/Words) x8 Address Range (A20 - A-1) x16 Address Range (A20 - A0) SA0 8K/4K FFF FFF SA1 8K/4K FFF FFF SA2 8K/4K FFF FFF SA3 8K/4K FFF FFF SA4 8K/4K FFF FFF SA5 8K/4K 00A000-00BFFF FFF SA6 8K/4K 00C000-00DFFF FFF SA7 8K/4K 00E000-00FFFF FFF SA8 64K/32K FFFF FFFF SA9 64K/32K FFFF FFF SA10 64K/32K FFFF FFFF SA11 64K/32K FFFF FFF SA12 64K/32K FFFF FFFF SA13 64K/32K FFFF FFF SA14 64K/32K FFFF FFFF SA15 64K/32K FFFF FFF SA16 64K/32K FFFF FFFF SA17 64K/32K 0A0000-0AFFFF FFF SA18 64K/32K 0B0000-0BFFFF FFFF SA19 64K/32K 0C0000-0CFFFF FFF SA20 64K/32K 0D0000-0DFFFF FFFF SA21 64K/32K 0E0000-0EFFFF FFF SA22 64K/32K 0F0000-0FFFFF FFFF SA23 64K/32K FFFF FFF SA24 64K/32K FFFF FFFF SA25 64K/32K FFFF FFF SA26 64K/32K FFFF FFFF SA27 64K/32K FFFF A A7FFF SA28 64K/32K FFFF A AFFFF SA29 64K/32K FFFF B B7FFF SA30 64K/32K FFFF B BFFFF SA31 64K/32K FFFF C C7FFF SA32 64K/32K FFFF C CFFFF SA33 64K/32K 1A0000-1AFFFF D D7FFF SA34 64K/32K 1B0000-1BFFFF D DFFFF SA35 64K/32K 1C0000-1CFFFF E E7FFF SA36 64K/32K 1D0000-1DFFFF E EFFFF 15

16 9. AT49BV322D Sector Address Table (Continued) Sector Size (Bytes/Words) x8 Address Range (A20 - A-1) x16 Address Range (A20 - A0) SA37 64K/32K 1E0000-1EFFFF F F7FFF SA38 64K/32K 1F0000-1FFFFF F FFFFF SA39 64K/32K FFFF FFF SA40 64K/32K FFFF FFFF SA41 64K/32K FFFF FFF SA42 64K/32K FFFF FFFF SA43 64K/32K FFFF FFF SA44 64K/32K FFFF FFFF SA45 64K/32K FFFF FFF SA46 64K/32K FFFF FFFF SA47 64K/32K FFFF FFF SA48 64K/32K FFFF FFFF SA49 64K/32K 2A0000-2AFFFF FFF SA50 64K/32K 2B0000-2BFFFF FFFF SA51 64K/32K 2C0000-2CFFFF FFF SA52 64K/32K 2D0000-2DFFFF FFFF SA53 64K/32K 2E0000-2EFFFF FFF SA54 64K/32K 2F0000-2FFFFF FFFF SA55 64K/32K FFFF FFF SA56 64K/32K FFFF FFFF SA57 64K/32K FFFF FFF SA58 64K/32K FFFF FFFF SA59 64K/32K FFFF 1A0000-1A7FFF SA60 64K/32K FFFF 1A8000-1AFFFF SA61 64K/32K FFFF 1B0000-1B7FFF SA62 64K/32K FFFF 1B8000-1BFFFF SA63 64K/32K FFFF 1C0000-1C7FFF SA64 64K/32K FFFF 1C8000-1CFFFF SA65 64K/32K 3A0000-3AFFFF 1D0000-1D7FFF SA66 64K/32K 3B0000-3BFFFF 1D8000-1DFFFF SA67 64K/32K 3C0000-3CFFFF 1E0000-1E7FFF SA68 64K/32K 3D0000-3DFFFF 1E8000-1EFFFF SA69 64K/32K 3E0000-3EFFFF 1F0000-1F7FFF SA70 64K/32K 3F0000-3FFFFF 1F8000-1FFFFF 16

17 10. AT49BV322DT Sector Address Table Sector Size (Bytes/Words) x8 Address Range (A20 - A-1) x16 Address Range (A20 - A0) SA0 64K/32K FFFF FFF SA1 64K/32K FFFF FFFF SA2 64K/32K FFFF FFF SA3 64K/32K FFFF FFFF SA4 64K/32K FFFF FFF SA5 64K/32K FFFF FFFF SA6 64K/32K FFFF FFF SA7 64K/32K FFFF FFFF SA8 64K/32K FFFF FFF SA9 64K/32K FFFF FFFF SA10 64K/32K 0A0000-0AFFFF FFF SA11 64K/32K 0B0000-0BFFFF FFFF SA12 64K/32K 0C0000-0CFFFF FFF SA13 64K/32K 0D0000-0DFFFF FFFF SA14 64K/32K 0E0000-0EFFFF FFF SA15 64K/32K 0F0000-0FFFFF FFFF SA16 64K/32K FFFF FFF SA17 64K/32K FFFF FFFF SA18 64K/32K FFFF FFF SA19 64K/32K FFFF FFFF SA20 64K/32K FFFF A A7FFF SA21 64K/32K FFFF A AFFFF SA22 64K/32K FFFF B B7FFF SA23 64K/32K FFFF B BFFFF SA24 64K/32K FFFF C C7FFF SA25 64K/32K FFFF C CFFFF SA26 64K/32K 1A0000-1AFFFF D D7FFF SA27 64K/32K 1B0000-1BFFFF D DFFFF SA28 64K/32K 1C0000-1CFFFF E E7FFF SA29 64K/32K 1D0000-1DFFFF E EFFFF SA30 64K/32K IE IEFFFF F F7FFF SA31 64K/32K 1F0000-1FFFFF F FFFFF SA32 64K/32K FFFF FFF SA33 64K/32K FFFF FFFF SA34 64K/32K FFFF FFF SA35 64K/32K FFFF FFFF SA36 64K/32K FFFF FFF 17

18 10. AT49BV322DT Sector Address Table (Continued) Sector Size (Bytes/Words) x8 Address Range (A20 - A-1) x16 Address Range (A20 - A0) SA37 64K/32K FFFF FFFF SA38 64K/32K FFFF FFF SA39 64K/32K FFFF FFFF SA40 64K/32K FFFF FFF SA41 64K/32K FFFF FFFF SA42 64K/32K 2A0000-2AFFFF FFF SA43 64K/32K 2B0000-2BFFFF FFFF SA44 64K/32K 2C0000-2CFFFF FFF SA45 64K/32K 2D0000-2DFFFF FFFF SA46 64K/32K 2E0000-2EFFFF FFF SA47 64K/32K 2F0000-2FFFFF FFFF SA48 64K/32K FFFF FFF SA49 64K/32K FFFF FFFF SA50 64K/32K FFFF FFF SA51 64K/32K FFFF FFFF SA52 64K/32K FFFF 1A0000-1A7FFF SA53 64K/32K FFFF 1A8000-1AFFFF SA54 64K/32K FFFF 1B0000-1B7FFF SA55 64K/32K FFFF 1B8000-1BFFFF SA56 64K/32K FFFF 1C0000-1C7FFF SA57 64K/32K FFFF 1C8000-1CFFFF SA58 64K/32K 3A0000-3AFFFF 1D0000-1D7FFF SA59 64K/32K 3B0000-3BFFFF 1D8000-1DFFFF SA60 64K/32K 3C0000-3CFFFF 1E0000-1E7FFF SA61 64K/32K 3D0000-3DFFFF 1E8000-1EFFFF SA62 64K/32K 3E0000-3EFFFF 1F0000-1F7FFF SA63 8K/4K 3F0000-3F1FFF 1F8000-1F8FFF SA64 8K/4K 3F2000-3F3FFF 1F9000-1F9FFF SA65 8K/4K 3F4000-3F5FFF 1FA000-1FAFFF SA66 8K/4K 3F6000-3F7FFF 1FB000-1FBFFF SA67 8K/4K 3F8000-3F9FFF 1FC000-1FCFFF SA68 8K/4K 3FA000-3FBFFF 1FD000-1FDFFF SA69 8K/4K 3FC000-3FDFFF 1FE000-1FEFFF SA70 8K/4K 3FE000-3FFFFF 1FF000-1FFFFF 18

19 11. DC and AC Operating Range -70 Operating Temperature (Case) Ind. -40 C - 85 C V CC Power Supply 2.65V to 3.6V 12. Operating Modes Mode CE OE WE RESET V PP (1) Ai I/O Read V IL V IL V IH V IH X (2) Ai D OUT Program/Erase (3) V IL V IH V IL V IH V IHPP (4) Standby/Program Inhibit V IH X (2) X V IH X X High-Z Program Inhibit X X V IH V IH X X V IL X V IH X X X X V IH V ILPP (5) Output Disable X V IH X V IH X High-Z Reset X X X V IL X X High-Z Product Identification Software (6) V IH A0 = V IL,A1-A20=V IL Manufacturer Code (7) A0 = V IH,A1-A20=V IL Device Code (7) Notes: 1. The VPP pin can be tied to V CC. For faster program operations, V PP can be set to 9.5V ± 0.5V. 2. X can be V IL or V IH. 3. Refer to Program Cycle Waveforms on page V IHPP (min) = 1.65V 5. V ILPP (max) = 0.4V. 6. See details under Software Product Identification Entry/Exit on page Manufacturer Code: 1FH (x8); 001FH (x16), Device Code: C8H (x8) - AT49BV322D; 01C8H (x16) - AT49BV322D; C9H (x8) - AT49BV322DT; 01C9H (x16) - AT49BV322DT. Ai D IN 19

20 13. DC Characteristics Symbol Parameter Condition Min Typ Max Units I LI Input Load Current V IN =0VtoV CC 2 µa I LO Output Leakage Current V I/O =0VtoV CC 2 µa I SB V CC Standby Current CMOS CE = V CC - 0.3V to V CC µa I CC (1) V CC Active Read Current f = 5 MHz; I OUT =0mA ma I CC1 V CC Programming Current 25 ma I PP1 V PP Input Load Current 10 µa V IL Input Low Voltage 0.6 V V IH Input High Voltage 2.0 V V OL1 Output Low Voltage I OL = 2.1 ma 0.45 V V OL2 Output Low Voltage I OL = 1.0 ma 0.20 V V OH1 Output High Voltage I OH = -400 µa 2.4 V V OH2 Output High Voltage I OH = -100 µa 2.5 V Note: 1. In the erase mode, I CC is 25 ma. 20

21 14. Input Test Waveforms and Measurement Level t R,t F <5ns 15. Output Test Load 16. Pin Capacitance f = 1 MHz, T = 25 C (1) Symbol Typ Max Units Conditions C IN 4 6 pf V IN =0V C OUT 8 12 pf V OUT =0V Note: 1. This parameter is characterized and is not 100% tested. 21

22 17. AC Read Characteristics Symbol Parameter 18. AC Read Waveforms (1)(2)(3)(4) -70 t RC Read Cycle Time 70 ns t ACC Address to Output Delay 70 ns t CE (1) t OE (2) t DF (3)(4) t OH CE to Output Delay 70 ns OE to Output Delay 0 20 ns CE or OE to Output Float 0 25 ns Output Hold from OE, CE or Address, whichever occurred first Min Max Units 0 ns t RO RESET to Output Delay 100 ns t RC ADDRESS ADDRESS VALID CE t CE OE t OE t DF t OH t ACC RESET t RO OUTPUT HIGH Z OUTPUT VALID Notes: 1. CE may be delayed up to t ACC -t CE after the address transition without impact on t ACC. 2. OE may be delayed up to t CE -t OE after the falling edge of CE without impact on t CE or by t ACC -t OE after an address change without impact on t ACC. 3. t DF is specified from OE or CE, whichever occurs first (CL = 5 pf). 4. This parameter is characterized and is not 100% tested. 22

23 19. AC Byte/Word Load Characteristics Symbol Parameter Min Max Units t AS,t OES Address, OE Setup Time 0 ns t AH Address Hold Time 25 ns t CS Chip Select Setup Time 0 ns t CH Chip Select Hold Time 0 ns t WP Write Pulse Width (WE or CE) 25 ns t WPH Write Pulse Width High 15 ns t DS Data Setup Time 25 ns t DH,t OEH Data, OE Hold Time 0 ns 20. AC Byte/Word Load Waveforms 20.1 WE Controlled 20.2 CE Controlled 23

24 21. Program Cycle Characteristics Symbol Parameter Min Typ Max Units t BP Byte/Word Programming Time µs t BPD Byte/Word Programming Time in Dual Programming Mode 5 60 µs t AS Address Setup Time 0 ns t AH Address Hold Time 25 ns t DS Data Setup Time 25 ns t DH Data Hold Time 0 ns t WP Write Pulse Width 25 ns t WPH Write Pulse Width High 15 ns t WC Write Cycle Time 70 ns t RP Reset Pulse Width 500 ns t EC Chip Erase Cycle Time 33 seconds t SEC1 Sector Erase Cycle Time (4K Word Sectors) seconds t SEC2 Sector Erase Cycle Time (32K Word Sectors) seconds t ES Erase Suspend Time 15 µs t PS Program Suspend Time 10 µs 22. Program Cycle Waveforms OE PROGRAM CYCLE CE t WP t WPH t BP WE t AS t AH t DH A0 - A AAA 555 ADDRESS 555 t WC t DS DATA AA 55 A0 INPUT DATA AA 23. Sector or Chip Erase Cycle Waveforms OE (1) CE t WP t WPH WE t AS t AH t DH A0-A AAA AAA Note 2 t WC t DS t EC DATA AA AA 55 Note 3 WORD 0 WORD 1 WORD 2 WORD 3 WORD 4 WORD 5 Notes: 1. OE must be high only when WE and CE are both low. 2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased. (See note 3 under Command Definition Table on page 13.) 3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H. 24

25 24. Data Polling Characteristics (1) Symbol Parameter Min Typ Max Units t DH Data Hold Time 10 ns t OEH OE Hold Time 10 ns t OE OE to Output Delay (2) ns t WR Write Recovery Time 0 ns Notes: 1. These parameters are characterized and not 100% tested. 2. See t OE spec in AC Read Characteristics on page Data Polling Waveforms WE CE OE t OEH I/O7 t DH t OE HIGH Z t WR A0-A20 An An An An An 26. Toggle Bit Characteristics (1) Symbol Parameter Min Typ Max Units t DH Data Hold Time 10 ns t OEH OE Hold Time 10 ns t OE OE to Output Delay (2) ns t OEHP OE High Pulse 50 ns t WR Write Recovery Time 0 ns Notes: 1. These parameters are characterized and not 100% tested. 2. See t OE spec in AC Read Characteristics on page Toggle Bit Waveforms (1)(2)(3) Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The t OEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 25

26 28. Software Product Identification Entry (1) LOAD DATA AA TO ADDRESS Sector Lockdown Enable Algorithm (1) LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA 55 TO ADDRESS AAA 29. Software Product Identification Exit (1)(6) LOAD DATA AA TO ADDRESS 555 LOAD DATA 90 TO ADDRESS 555 ENTER PRODUCT IDENTIFICATION MODE (2)(3)(5) OR LOAD DATA F0 TO ANY ADDRESS LOAD DATA 80 TO ADDRESS 555 LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA 55 TO ADDRESS AAA LOAD DATA F0 TO ADDRESS 555 EXIT PRODUCT IDENTIFICATION MODE (4) LOAD DATA 60 TO SECTOR ADDRESS PAUSE 200 μs (2) EXIT PRODUCT IDENTIFICATION MODE (4) Notes: 1. Data Format: I/O15 - I/O8 (Don t Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex), A-1, and A11 - A20 (Don t Care). 2. A1 - A20 = V IL. Manufacturer Code is read for A0 = V IL ; Device Code is read for A0 = V IH. Additional Device Code is read from address 0003H. 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 1FH(x8); 001FH(x16) Device Code:C8 (x8) AT49BV322D; 01C8 (x16) AT49BV322D; C9H (x8) AT49BV322DT; 01C9H (x16) AT49BV322DT. Additional Device Code: 01 (x8) ; 0001 (x16) 6. Either one of the Product ID Exit commands can be used. Notes: 1. Data Format: I/O15 - I/O8 (Don t Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex), A-1, and A11 - A20 (Don t Care). 2. Sector Lockdown feature enabled. 26

27 31. Common Flash Interface Definition Table Address Data (x16 Mode) (x8 Mode) Comments 10h 20h 0051h Q 11h 22h 0052h R 12h 24h 0059h Y 13h 26h 0002h 14h 28h 0000h 15h 2Ah 0041h 16h 2Ch 0000h 17h 2Eh 0000h 18h 30h 0000h 19h 32h 0000h 1Ah 34h 0000h 1Bh 36h 0027h VCC min write/erase 1Ch 38h 0036h VCC max write/erase 1Dh 3Ah 0090h VPP min voltage 1Eh 3Ch 00A0h VPP max voltage 1Fh 3Eh 0004h Typ word write 10 µs 20h 40h 0002h Typ dual word program time 5 µs 21h 42h 0009h Typ sector erase, 500 ms 22h 44h 000Fh Typ chip erase, 33,000 ms 23h 46h 0004h Max word write/typ time 24h 48h 0004h Max dual word program time/typ time 25h 4Ah 0004h Max sector erase/typ sector erase 26h 4Ch 0004h Max chip erase/ typ chip erase 27h 4Eh 0016h Device size 28h 50h 0002h x8/x16 device 29h 52h 0000h x8/x16 device 2Ah 54h 0002h Maximum number of bytes in multiple byte write = 4 2Bh 56h 0000h Maximum number of bytes in multiple byte write = 4 2Ch 58h 0002h 2 regions, x = 2 2Dh 5Ah 0007h 8K bytes, Y = 7 2Eh 5Ch 0000h 8K bytes, Y = 7 2Fh 5Eh 0020h 8K bytes, Z = 32 30h 60h 0000h 8K bytes, Z = 32 31h 62h 003Eh 64K bytes, Y = 62 32h 64h 0000h 64K bytes, Y = 62 33h 66h 0000h 64K bytes, Z = h 68h 0001h 64K bytes, Z =

28 31. Common Flash Interface Definition Table (Continued) Address Data (x16 Mode) (x8 Mode) Comments VENDOR SPECIFIC EXTENDED QUERY 41h 82h 0050h P 42h 84h 0052h R 43h 86h 0049h I 44h 88h 0031h Major version number, ASCII 45h 8Ah 0030h Minor version number, ASCII 46h 8Ch 0087h Bit 0 chip erase supported, 0 no,1 yes Bit1 erasesuspend supported, 0 no,1 yes Bit 2 program suspend supported, 0 no, 1 yes Bit 3 simultaneous operations supported, 0 no,1 yes Bit4 burst mode read supported, 0 no,1 yes Bit 5 page mode read supported, 0 no,1 yes Bit 6 queued erase supported, 0 no,1 yes Bit 7 protection bits supported, 0 no, 1 yes 47h 8Eh 0000h (top) or 0001h (bottom) Bit 8 top ( 0 ) or bottom ( 1 ) boot block device undefined bits are 0 48h 90h 0000h 49h 92h 0000h Bit0 4wordlinear burst with wrap around, 0 no,1 yes Bit1 8wordlinear burst with wrap around, 0 no,1 yes Bit 2 continuos burst, 0-no,1-yes Undefined bits are 0 Bit0 4wordpage, 0 no,1 yes Bit1 8wordpage, 0 no,1 yes Undefined bits are 0 4Ah 94h 0080h Location of protection register lock byte, the section s first byte 4Bh 96h 0003h # of bytes in the factory prog section of prot register 2*n 4Ch 98h 0003h # of bytes in the user prog section of prot register 2*n 28

29 32. Ordering Information 32.1 Green Package (Pb/Halide-free) t ACC (ns) Active I CC (ma) Standby Ordering Code Package Operation Range AT49BV322D-70CU AT49BV322D-70TU AT49BV322DT-70CU AT49BV322DT-70TU 48C17 48T 48C17 48T Industrial (-40 to 85 C) Industrial (-40 to 85 C) Package Type 48C17 48T 48-ball, Plastic Chip-Size Ball Grid Array Package (CBGA) 48-lead, Plastic Thin Small Outline Package (TSOP) 29

30 33. Packaging Information C17 CBGA A1 Ball ID E D Top View A1 A 1.50 REF E1 e A1 Ball Corner Side View 2.20 REF A B C D E D1 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE E F E1 4.0 TYP G H b Bottom View e D D1 5.6 TYP A 1.0 A e 0.80 BSC b 0.35 TYP 10/26/05 R 2325 Orchard Parkway San Jose, CA TITLE 48C17, 48-ball (6 x8array), 0.80 mm Pitch, 7.0 x 10.0 x 1.0 mm Chip-scale Ball Grid Array Package (CBGA) DRAWING NO. 48C17 REV. B 30

31 T TSOP PIN 1 0º ~ 8º c Pin 1 Identifier D1 D L e b L1 E A2 A SEATING PLANE GAGE PLANE A1 COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MO-142, Variation DD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX NOTE A 1.20 A A D D Note 2 E Note 2 L L BASIC b c e 0.50 BASIC 10/18/01 R 2325 Orchard Parkway San Jose, CA TITLE 48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. 48T REV. B 31

32 34. Revision History Revision No. Revision A Sept History Initial Release Revision B Nov.2005 Changed the CFI values of addresses 20h & 24h in the x16 mode to 0002h and 0004h, respectively. 32

33 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) Fax: 1(408) Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) Fax: (41) Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) Fax: (852) Japan 9F, Tonetsu Shinkawa Bldg Shinkawa Chuo-ku, Tokyo Japan Tel: (81) Fax: (81) Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) Fax: 1(408) Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) Fax: 1(408) La Chantrerie BP Nantes Cedex 3, France Tel: (33) Fax: (33) ASIC/ASSP/Smart Cards Zone Industrielle Rousset Cedex, France Tel: (33) Fax: (33) East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) Fax: 1(719) Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) Fax: (44) RF/Automotive Theresienstrasse 2 Postfach Heilbronn, Germany Tel: (49) Fax: (49) East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) Fax: 1(719) Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP Saint-Egreve Cedex, France Tel: (33) Fax: (33) Literature Requests Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN- TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. Atmel Corporation All rights reserved. Atmel, logo and combinations thereof, Everywhere You Are and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Printed on recycled paper. /xm