CS303 LOGIC DESIGN FINAL EXAM


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1 JANUARY CS303 LOGIC DESIGN FINAL EXAM STUDENT NAME & ID: DATE: Instructions: Examination time: 100 min. Write your name and student number in the space provided above. This examination is closed book. There are 4 questions. The points for each question are given in the square brackets, next to the question title. The overall maximum score is 100. This final exam weighs 40% of your final grade. Answer each question in the space provided. If you need to continue an answer onto the back of the sheet, clearly indicate that and label the continuation with the question number. QUESTION POINTS /18 /28 /20 /34 TOTAL /100
2 1. Mark the correct statement(s) (18 %) 1.1 The minimum number of NOR gates (only!) with which it is possible to implement an AND gate is (hint: DeMorgan s theorem): [3] a) 2, b) 3, c) 4, d) It is not possible to do. 1.2 Which type of memory is volatile? [3] a) EEPROM, b) SRAM, c) DRAM, d) HDD. 1.3 Which of the following is an axiom of Boolean algebra: [3] a) x. 0 = 0, b) = 1, c) x. x = 0, d) x + x = 1, e) = 1 f) None of these 1.4 A priority encoder with 4 inputs has: [3] a) 2 outputs, b) 3 outputs, c) 4 outputs, d) 16 outputs 1.5 The binary number is the two's complement representation of: [3] a) 11, b) 12, c) 20, d) The output Y = 1. Which input combination below gives this output? [3] a) , b) , c) , d) e) None of the above. 2. RAM, Logic gates and components (28%) 2.1 Write down the excitation tables of D type, T type and JK type flip flops! [9] 2.2 Implement the Boolean function F with 4x1 multiplexer and external gates. [7] D = ( ) 2.3 Design (draw the chips and main components and connections) a 32M x 16 memory using RAM chips that are 8M x 8! How many address bits are required? How many data bits constitute the data bus? If the address decoder has in total 4 inputs, what is the maximum capacity to which you can expand the memory? [12]
3 3. VHDL exercise (20 %) Complete VHDL code to create a 16bit synchronous counter that increments its value on each positive edge of the clock if the Enable signal is high. The counter is reset to 0 on the next positive clock edge if the synchronous Reset input is low. Use two toggle switches for enable and reset inputs, and pushbutton switch for counter input value. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY Counter IS PORT ( SW : IN STD_LOGIC_VECTOR( ); KEY : STD_LOGIC_VECTOR( ); HEX3, HEX2, HEX1, HEX0 : ( )); END Counter; ARCHITECTURE Structural OF Counter IS COMPONENT hex7seg PORT ( ); END COMPONENT; Clock, Reset, Enable : STD_LOGIC; Count : ; PROCESS ( ) END PROCESS;  drive the displays digit3: digit2: digit1: digit0: END Structural;
4 LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY hex7seg IS PORT ( hex : IN STD_LOGIC_VECTOR( ); display : OUT STD_LOGIC_VECTOR( ); END hex7seg; ARCHITECTURE Function OF hex7seg IS PROCESS (hex) CASE IS WHEN " " => display <= " "; WHEN " " => display <= " "; WHEN " " => display <= " "; WHEN " " => display <= " "; WHEN " " => display <= " "; WHEN " " => display <= " "; WHEN " " => display <= " "; WHEN " " => display <= " "; WHEN " " => display <= " "; WHEN " " => display <= " "; WHEN " " => display <= " "; WHEN " " => display <= " "; WHEN " " => display <= " "; WHEN " " => display <= " "; WHEN " " => display <= " "; WHEN => display <= " "; END CASE; END PROCESS; END Function;
5 4. Finite State Machine Design (34 %) You are a tourist and you want to visit some cities. You can travel from one to another city, depending on how much money you have in your pocket. The four cities are: Sarajevo, Tuzla, Mostar and Bihac. In your pocket, you can either see that there is money (M=1), or there is no money (M=0). You start the trip in Sarajevo. Sarajevo: If you don t have money stay in Sarajevo. If you have money then go to Tuzla. Tuzla: if you don t have any money left return back to Sarajevo. If you have money then go to Bihac. Bihac: if you don t have any money left return back to Sarajevo. If you have more money then go to Mostar. Mostar: if you don t have any money left return back to Sarajevo. If you have money stay in Mostar. 4.1 Assign states to cities and make the state diagram! [8] 4.2 Fill the state table! [8] 4.3 Design the FSM with Tflip flops! (Just state the input equations.) [9] 4.4 Design the FSM with D or JKflip flops! (Just state the input equations.) [9] Present State INPUT Next T flip flops flip flops M State T1 T0
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