Number Representations Cptr280 Dr Curtis Nelson Number Systems and Their Representations In this presentation you will learn about: Representation of numbers in computers; Signed vs. unsigned numbers; Conditions which cause overflow; Some MIPS instructions. 1
7-Bit ASCII Code Arithmetic for Computers Operations on integers Addition and subtraction; Multiplication and division; Dealing with overflow. Floating-point numbers Representation and operations; Dealing with overflow and underflow. 2
Numbers in Different Systems Positional Number Representation Decimal D = d n-1 d n-2...d 1 d 0 V(D) = d n-1 10 n-1 + d n-2 10 n-2 +... + d 1 10 1 + d 0 10 0 Example: 432 10 = (4x10 2 + 3x10 1 + 2x10 0 ) 10 Binary B = b n-1 b n-2...b 1 b 0 V(B) = b n-1 2 n-1 + b n-2 2 n-2 +... + b 1 2 1 + b 0 2 0 Example: 1101 2 = (1x2 3 + 1x2 2 + 0x2 1 + 1x2 0 ) 10 Hexadecimal H = h n-1 h n-2 h 1 h 0 V(H) = h n-1 16 n-1 + h n-2 16 n-2 +... + h 1 16 1 + h 0 16 0 Example: 6e2f 16 = (6x16 3 + ex16 2 + 2x16 1 + fx16 0 ) 10 3
Conversion: Binary to/from Decimal Conversion of binary to decimal V = b n-1 2 n-1 + b n-2 2 n-2 +... + b 1 2 1 + b 0 (1101) 2 = Conversion of decimal to binary Use power s of two table or repeated division method. (857) 10 =??? Decimal to Binary Conversion Example 4
Conversion: Binary to/from Hexadecimal Conversion of binary to hexadecimal Groups of four digits, starting with the LSB. (101001101011101) 2 =( ) 16 Conversion of hexadecimal to binary Reverse of above. (3f2a) 16 = ( ) 2 Conversion: Decimal to/from Hexadecimal Conversion of decimal to hexadecimal Decimal to binary to hexadecimal. (61) 10 =( ) 2 = ( ) 16 Conversion of hexadecimal to decimal Reverse of above. (3f2a) 16 = ( ) 2 = ( ) 10 5
Unsigned Binary Representation Unsigned binary numbers are typically used to represent computer addresses or other values that are guaranteed not to be negative. Unsigned binary means no negative numbers are represented. Often when people say "binary number" this is what they mean: With N bits and base two representation, the integers 0, 1, 2,... 2 N - 1 can be represented. So, for instance, with 8 bits, the integers 0, 1,..., 2 8-1 can be represented. This is 0... 255. With N bits, zero is represented by 0...0...0 (all 0's). (2 N - 1) is represented by 1...1...1 (all 1's). These facts are NOT always true for other binary number representation schemes. Know what scheme is used before you decide what a pattern represents. Details Usually math operands and the result have a fixed number of bits (8, 16, 32, or 64). These are the sizes that processors use to represent integers. To keep the result the same size as the operands, you may have to include zero bits in some of the leftmost columns (sign extension). Compute the carry-out of the leftmost column, but don't write it as part of the answer (because there is no room if you have a fixed number of bits.) When the operands are represented using the unsigned binary scheme, a carry-out of 1 from the leftmost column means the sum does not fit into the fixed number of bits. This is called Overflow. When the operands are represented using the two's complement scheme (which will be described later), then a carry-out of 1 from the leftmost column is not necessarily overflow. Integers may be represented using a scheme called unsigned binary or a scheme called two's complement binary. The same binary addition hardware is used, but to interpret the result you need to know what scheme is being used. 6
Unsigned Binary Addition Add 122 10 and 125 10 in unsigned binary. result is 247 10, carry = 0 Now add 122 10 and 145 10. Result is 267 10, binary = 00001011? Result is 11 10, carry = 1, i.e. overflow Overflow in unsigned binary addition (assembly instructions addu, addiu) means the result is incorrect an error condition that may or may not be flagged by the processor. Unsigned Binary Subtraction Subtract 122 10 from 125 10 in unsigned binary. result is 3 10, carry = 0 Now subtract 125 10 from 122 10 Result is 3 10, binary = 11111101 (+253 10?) Result is 253 10, carry = 1, i.e. underflow Underflow in unsigned binary subtraction (subu) means the result is incorrect an error condition that will not be flagged by the processor (or SPIM). 7
Unsigned - Detecting Overflow For unsigned numbers, overflow occurs if there is a carry out of the most significant bit. For example, 1001 = 9 +1000 = 8 0001 = 1 With the MIPS architecture Overflow exceptions occur for two s complement arithmetic add, sub, addi Overflow exceptions do not occur for unsigned arithmetic addu, subu, addiu Unsigned Vs. Signed Numbers b n 1 b 1 b 0 MSB Magnitude (a) Unsigned number bn 1bn 2 b 1 b 0 Sign 0 denotes 1 denotes + MSB Magnitude (b) Signed number 8
Interpretation of Four-Bit Signed Integers abcd Sign and magnitude 1 s complement 2 s complement 0111 +7 +7 +7 0110 +6 +6 +6 0101 +5 +5 +5 0100 +4 +4 +4 0011 +3 +3 +3 0010 +2 +2 +2 0001 +1 +1 +1 0000 +0 +0 0 1000-0 -7-8 1001-1 -6-7 1010-2 -5-6 1011-3 -4-5 1100-4 -3-4 1101-5 -2-3 1110-6 -1-2 1111-7 -0-1 Sign and Magnitude Magnitude of positive and negative numbers represented in the same way; Sign used to distinguish them; Simple to understand; Complicates hardware design. If both operands have the same sign, then addition is simple Add magnitudes and copy the sign. If they have opposite signs, then must subtract smaller from the larger. This is complicated, so sign magnitude is seldom used in computers. 9
1 s Complement n-bit negative number found by subtracting its positive form from 2 n -1 K 1 = (2 n 1) P Found by just complementing each bit. Used in earlier computers (pre-1970). 2 s Complement Representation By far the most common form for signed numbers today. To negate a two's complement integer, invert all the bits and add a one to the least significant bit. What are the two s complements of: 6 = 0110-4 = 1100 10
Examples What is the value of the two's complement integer 1111111111111101 in decimal? What is the value of the unsigned integer 1111111111111101 in decimal? What is the negation of the two's complement integer 1010000000000000 in binary? Graphical Representation of Four-bit 2 s Complement Numbers 1101 1110 1111 2 3 1 0000 0 + 1 0001 + 2 + 3 0010 0011 1100 4 + 4 0100 5 + 5 1011 0101 6 + 6 7 + 7 1010 8 0110 1001 0111 1000 11
Two s Complement Addition To add two's complement numbers, add the corresponding bits of both numbers with carry between bits. For example, 3 = 0011-3 = 1101-3 = 1101 3 = 0011 + 2 = 0010 +-2 = 1110 + 2 = 0010 + -2 = 1110 -------- --------- --------- --------- Unsigned and two s complement addition are performed exactly the same way, but how they detect overflow differs. More 2 s Complement Addition Examples ( + 5) + ( + 2) + 0 1 0 1 0 0 1 0 ( 5) + ( + 2) + 1 0 1 1 0 0 1 0 ( + 7) 0 1 1 1 ( 3) 1 1 0 1 ( + 5) + ( 2) + 0 1 0 1 1 1 1 0 ( 5) + ( 2) + 1 0 1 1 1 1 1 0 ( + 3) 1 0 0 1 1 ( 7) 1 1 0 0 1 ignore ignore 12
Two s Complement Subtraction To subtract two's complement numbers, first negate the second number and then add the corresponding bits of both numbers. For example: 3 = 0011-3 = 1101-3 = 1101 3 = 0011-2 = 0010 - -2 = 1110-2 = 0010 - -2 = 1110 ---------- --------- --------- --------- More 2 s Complement Subtraction Examples ( +5) ( +2) ( +3) 0 1 0 1 0 0 1 0 + 0 1 0 1 1 1 1 0 1 0 0 1 1 ( 5) ( +2) ( 7) 1 0 1 1 0 0 1 0 ignore + 1 0 1 1 1 1 1 0 1 1 0 0 1 ignore ( +5) 0 1 0 1 0 1 0 1 ( 2) 1 1 1 0 + 0 0 1 0 ( +7) 0 1 1 1 ( 5) 1 0 1 1 1 0 1 1 ( 2) 1 1 1 0 + 0 0 1 0 ( 3) 1 1 0 1 13
Overflow When adding or subtracting numbers, the sum or difference can go beyond the range of representable numbers. This is known as overflow. For example, for two's complement numbers, 5 = 0101-5 = 1011 5 = 0101-5 = 1011 + 6 = 0110 + -6 = 1010 + -6 = 1010 +6 = 0110 -------- --------- --------- --------- -5 = 1011 5 = 0101-1 = 1111 1 = 0001 Overflow creates an incorrect result that must be detected and dealt with. Summary of Overflow Conditions Overflow occurs when the result of an operation cannot be represented in 32-bits, i.e., when the sign bit contains a value bit of the result and not the proper sign bit. When adding operands with different signs or when subtracting operands with the same sign, overflow can never occur. Operation Operand A Operand B Result indicating overflow A + B 0 0 < 0 A + B < 0 < 0 0 A - B 0 < 0 < 0 A - B < 0 0 0 MIPS signals overflow with an exception (interrupt) an unscheduled procedure call where the Exception Program Counter (EPC) contains the address of the instruction that caused the exception. 14
Detecting Overflow Logically When adding two's complement numbers, overflow will only occur if: The numbers being added have the same sign; The sign of the result is different then the sign of the two operands. If we perform the addition a n-1 a n-2... a 1 a 0 + b n-1 b n-2 b 1 b 0 ---------------------------------- = s n-1 s n-2 s 1 s 0 Overflow can be detected as V = an - 1 bn - 1 sn-1 + an-1 bn-1 sn - 1 Overflow can also be detected as V = c n Ä cn - 1 where c n-1 and c n are the carry in and carry out of the most significant bit. MIPS 32-bit Number Representations 32-bit signed numbers (2 s complement): 0000 0000 0000 0000 0000 0000 0000 0000 two = 0 ten 0000 0000 0000 0000 0000 0000 0000 0001 two = + 1 ten... maxint 0111 1111 1111 1111 1111 1111 1111 1110 two = + 2,147,483,646 ten 0111 1111 1111 1111 1111 1111 1111 1111 two = + 2,147,483,647 ten 1000 0000 0000 0000 0000 0000 0000 0000 two = 2,147,483,648 ten 1000 0000 0000 0000 0000 0000 0000 0001 two = 2,147,483,647 ten... MSB 1111 1111 1111 1111 1111 1111 1111 1110 two = 2 ten 1111 1111 1111 1111 1111 1111 1111 1111 two = 1 ten LSB minint 15
MIPS Arithmetic Instructions MIPS arithmetic instructions Instruction Example Meaning Comments add add $1,$2,$3 $1 = $2 + $3 3 operands; exception possible subtract sub $1,$2,$3 $1 = $2 $3 3 operands; exception possible add immediate addi $1,$2,100 $1 = $2 + 100 + constant; exception possible add unsigned addu $1,$2,$3 $1 = $2 + $3 3 operands; no exceptions subtract unsigned subu $1,$2,$3 $1 = $2 $3 3 operands; no exceptions add imm. unsign. addiu $1,$2,100 $1 = $2 + 100 + constant; no exceptions multiply mult $2,$3 Hi, Lo = $2 x $3 64-bit signed product multiply unsigned multu $2,$3 Hi, Lo = $2 x $3 64-bit unsigned product divide div $2,$3 Lo = $2 $3, Lo = quotient, Hi = remainder Hi = $2 mod $3 divide unsigned divu $2,$3 Lo = $2 $3, Unsigned quotient & remainder Hi = $2 mod $3 Move from Hi mfhi $1 $1 = Hi Used to get copy of Hi Move from Lo mflo $1 $1 = Lo Used to get copy of Lo Note: Move from Hi and Move from Lo are really data transfers Converting < 32-bit Values into 32-bit Values Copy the most significant bit (the sign bit) into the empty bits: 0010 -> 0000 0010 1010 -> 1111 1010 Sign-extend versus Zero-extend 16
Integer Addition Example: 7 + 6 n n Overflow if result out of range Adding a + and - operand, no overflow possible. n Adding two + operands n Overflow if sign of result is 1. n Adding two operands n Overflow if sign of result is 0. Integer Subtraction Add negation of second operand. Example: 7 6 = 7 + ( 6) +7: 0000 0000 0000 0111 6: 1111 1111 1111 1010 +1: 0000 0000 0000 0001 Overflow if result out of range Subtracting two + or two operands, no overflow. Subtracting + from operand Overflow if result sign is 0. Subtracting from + operand Overflow if result sign is 1. 17
MIPS Arithmetic Logic Unit (ALU) zero ovf Must support the Arithmetic/Logic operations of the ISA A add, addi, addiu, addu sub, subu mult, multu, div, divu B sqrt and, andi, nor, or, ori, xor, xori beq, bne, slt, slti, sltiu, sltu 32 32 1 1 ALU result 32 4 m (operation) With special handling for - Sign extend addi, addiu, slti, sltiu - Zero extend andi, ori, xori - Overflow detection add, addi, sub Conclusions In this presentation you learned about: Representation of numbers in computers; Signed vs. unsigned numbers; Conditions which cause overflow; Some MIPS instructions. 18