Computer Graphics Hardware A Overview
Graphics System Moitor Iput devices CPU/Memory GPU
Raster Graphics System Raster: A array of picture elemets Based o raster-sca TV techology The scree (ad a picture) cosists of discrete pixels, ad each pixel has a small display area video cotroller A Frame buffer Moitor
Frame Buffer Frame buffer: the memory to hold the pixel properties (color, alpha, depth, stecil mask, etc) Properties of a frame buffer that affect the graphics performace: Size: scree resolutio Depth: color level 1 bit/pixel: black ad white 8 bits/pixel: 256 levels of gray or color pallet idex 24 bits/pixel: 16 millio colors Speed: refresh speed
Graphics Accelerator Graphics Memory/ Frame buffer A dedicated processor for graphics processig Graphics Processor Video Cotroller CPU Mai Memory System bus
Graphics Bus Iterface PCI based techology Graphics Memory/ Frame buffer Graphics Processor Video Cotroller Other Peripherals PCIe (8 GB/s) System Bus CPU Mai Memory
Graphics Accelerators
What do GPUs do? Graphics processig uits (GPUs) are massively parallel processors Process geometry/pixels ad produce images to be displayed o the scree Ca also be used to perform geeral purpose computatio (via CUDA/OpeGL) Evolved from simple video sca cotrollers, to special purpose processors that implemet a simple pipelie with fixed graphics fuctioality, to complex may-core architectures that cotai several deep parallel pipelies Example: vidia s Kepler GK110 cotais 15x192 cores ad 7.1 billios trasistors A graphics card ca easily have more tha 2GB of video memory
Computer Graphics Hardware A Overview
CPU/GPU Performace Gap
Vidia Kepler GK110 (2012)
Vidia TITAN X (2018) 12 B Trasistors 28 SMXs 11 TFlops 3 MB L2 Cache 384-bit GDDR5 PCI Express Ge3
Vidia Latest GPUs
SMX or SM (Streammig Processor)
Why are GPU s so fast? Etertaimet Idustry has drive the ecoomy of these chips? Males age 15-35 buy $10B i video games / year Moore s Law ++ Simplified desig (stream processig) Sigle-chip desigs.
Moder GPU has more ALU s
A Specialized Processor Very Efficiet For Fast Parallel Floatig Poit Processig Sigle Istructio Multiple Data Operatios High Computatio per Memory Access Not As Efficiet For Double Precisio Logical Operatios o Iteger Data Brachig-Itesive Operatios Radom Access, Memory-Itesive Operatios
The Rederig Pipelie The process to geerate two-dimesioal images from give virtual cameras ad 3D objects The pipelie stages implemet various core graphics rederig algorithms Why should you kow the pipelie? Necessary for programmig GPUs Uderstad various graphics algorithms Aalyze performace bottleeck host iterface vertex processig triagle setup pixel processig memory iterface
The Rederig Pipelie The basic costructio three coceptual stages Each stage is a pipelie ad rus i parallel Graphics performace is determied by the slowest stage Moder graphics systems: Software hardware Applicatio Geometry Rasteriazer Image
Host Iterface The host iterface is the commuicatio bridge betwee the CPU ad the GPU It receives commads from the CPU ad also pulls geometry iformatio from system memory It outputs a stream of vertices i object space with all their associated iformatio (ormals, texture coordiates, per vertex color etc) host iterface vertex processig triagle setup pixel processig memory iterface
Vertex Processig The vertex processig stage receives vertices from the host iterface i object space ad outputs them i scree space This may be a simple liear trasformatio, or a complex operatio ivolvig morphig effects Normals, texcoords etc are also trasformed No ew vertices are created i this stage, ad o vertices are discarded (iput/output has 1:1 mappig) host iterface vertex processig triagle setup pixel processig memory iterface
Triagle setup I this stage geometry iformatio becomes raster iformatio (scree space geometry is the iput, pixels are the output) Prior to rasterizatio, triagles that are backfacig or are located outside the viewig frustrum are rejected Some GPUs also do some hidde surface removal at this stage host iterface vertex processig triagle setup pixel processig memory iterface
Triagle Setup (cot) A fragmet is geerated if ad oly if its ceter is iside the triagle Every fragmet geerated has its attributes computed to be the perspective correct iterpolatio of the three vertices that make up the triagle host iterface vertex processig triagle setup pixel processig memory iterface
Fragmet Processig Each fragmet provided by triagle setup is fed ito fragmet processig as a set of attributes (positio, ormal, texcoord etc), which are used to compute the fial color for this pixel The computatios takig place here iclude texture mappig ad math operatios Typically the bottleeck i moder applicatios host iterface vertex processig triagle setup pixel processig memory iterface
Memory Iterface Fragmet colors provided by the previous stage are writte to the framebuffer Before the fial write occurs, some fragmets are rejected by the zbuffer, stecil ad alpha tests O moder GPUs, z ad color are compressed to reduce framebuffer badwidth (but ot size) host iterface vertex processig triagle setup pixel processig memory iterface
Programmability i the GPU Vertex ad fragmet processig, ad ow triagle set-up, are programmable The programmer ca write programs that are executed for every vertex as well as for every fragmet This allows fully customizable geometry ad shadig effects that go well beyod the geeric look ad feel of older 3D applicatios host iterface vertex processig triagle setup pixel processig memory iterface
The Graphics Pipelie
Diagram of a moder GPU Iput from CPU Host iterface Vertex processig Triagle setup Pixel processig Memory Iterface 64bits to memory 64bits to memory 64bits to memory 64bits to memory
The Quest for Realism (courtesy: vidia)