Capital Capital Logic Generative v2016.1 Student Workbook 2017 Mentor Graphics Corporation All rights reserved. This document contains information that is trade secret and proprietary to Mentor Graphics Corporation or its licensors and is subject to license terms. No part of this document may be photocopied, reproduced, translated, distributed, disclosed or provided to third parties without the prior written consent of Mentor Graphics.
This document is for information and instruction purposes. Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice, and the reader should, in all cases, consult Mentor Graphics to determine whether any changes have been made. The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers. No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever. MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS) ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT, EVEN IF MENTOR GRAPHICS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. U.S. GOVERNMENT LICENSE RIGHTS: The software and documentation were developed entirely at private expense and are commercial computer software and commercial computer software documentation within the meaning of the applicable acquisition regulations. Accordingly, pursuant to FAR 48 CFR 12.212 and DFARS 48 CFR 227.7202, use, duplication and disclosure by or for the U.S. Government or a U.S. Government subcontractor is subject solely to the terms and conditions set forth in the license agreement provided with the software, except for provisions which are contrary to applicable mandatory federal laws. TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the owner of the Mark, as applicable. The use herein of a third- party Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to indicate a product from, or associated with, a particular third party. A current list of Mentor Graphics trademarks may be viewed at: www.mentor.com/trademarks. End-User License Agreement: You can print a copy of the End-User License Agreement from: www.mentor.com/eula. Mentor Graphics Corporation 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777 Telephone: 503.685.7000 Toll-Free Telephone: 800.592.2210 Website: www.mentor.com SupportNet: supportnet.mentor.com/ Send Feedback on Documentation: supportnet.mentor.com/doc_feedback_form Part Number: 073618
Module 1: Introduction and Course Overview... 11 Abbreviations Used in This Course... 12 Overview of Capital Products... 13 Overview of Capital Logic Course... 15 Introduction to Capital Logic... 15 General Terminology... 16 Logical (or Functional) Design... 17 Wiring Design... 18 Example Design Types... 19 Getting Started... 20 Capital Logic`s User Interface... 22 Module 1 Lab: Introduction to Capital Logic... 25 Module 2: Creating Functional Diagrams... 27 Design Abstractions... 28 Flows Starting with Logical Designs... 29 Example of Logical Diagram... 30 Creating & Opening Projects... 30 Creating Designs... 31 Managing Diagrams... 34 Grid Preferences... 35 Borders... 36 Style Sets... 37 Adding Devices... 39 Associating Graphical Objects with Devices... 41 I
Replacing Device Symbols... 42 Adding Nets... 43 Module 2 Lab: Exercises #1 & #2... 45 Managing Pins on Parameterized Objects... 46 Adding Part Numbers... 48 Pin Properties and Graphics... 49 Object Names in Capital Logic... 49 Ring Terminals... 50 Moving Objects... 51 Conductor Routing... 53 Grip Points... 54 Moving Conductors... 55 Design Rule Checks (DRCs)... 56 Report Generation... 57 Filtering the Project and Design Views... 58 Saving Your Work... 58 Printing Designs... 59 Module 2 Lab: Exercise #3... 59 Module 3: Introduction to Capital Project... 61 Capital Project Concepts... 62 Capital Project Process... 63 Getting Started with Capital Project... 64 Project Templates... 66 System vs. Project Parameters... 68 Release Levels... 69 II
Release Level Behaviors... 71 Release Level Transitions... 72 Design Abstractions... 73 Audit Trails... 75 Exporting a Project... 75 Export / Import Project... 76 Close Project... 77 Module 3 Lab: Exercise #1... 77 Naming Conventions... 78 Object Type Information... 79 Default Names... 81 Duplicate Object Names... 84 Module 3 Lab: Exercise #2... 85 Advanced Naming Overview... 85 Advanced Naming Counters... 87 Creating an Advanced Naming Composition... 88 Advanced Naming Condition... 90 Applying the Advanced Naming Compositions... 91 Batch Generation of Object Names... 92 Language Translation... 93 Project Preferences... 95 Project Export Facility for Data Corruption... 97 Module 3 Lab: Exercise #3... 97 Module 4: Devices... 99 Devices... 100 III
Associating a Library Part with a Device... 102 Device Pin Mating... 104 Convert Device Symbol to Parameterized... 104 Module 4 Lab: Exercise #1... 105 Properties, Attributes and Graphics... 106 Top-Down vs. Bottom-Up Design... 109 Placing Library Parts onto a Diagram... 110 Batch Update Library Parts... 112 Module 4 Lab: Exercises #2 - #3... 113 Footprints... 114 Device-Side Connector Footprints... 116 Find and Replace... 117 Module 4 Lab: Exercise #4... 118 Module 5: Advanced Wiring... 119 Highways... 120 Conductor Manipulation... 122 Conductor Module Codes... 123 Splices... 123 Center Strip Splices... 124 Module 5 Lab: Exercise #1... 124 Adding Generic Multicores... 125 Associate a Library Part with a Generic Multicore... 126 Adding Multicores Directly from Library... 127 Shield Terminations... 128 Multi-Level Multicores... 130 IV
Customizing Multicore Indicators... 131 Overbraids... 132 Daisy Chained Multicores... 133 Module 5 Lab: Exercise #2... 134 Assemblies... 135 Stacked Pins... 137 Adding Images to Diagrams... 138 Block Diagrams vs. Block Views... 138 Module 5 Lab: Exercise #3... 140 Module 6: Shared Objects... 141 Design Wide Objects... 142 Join Command... 145 Cross-Reference Text... 146 Changing the Home Instance... 148 Module 6 Lab: Exercise #1... 148 Concurrency... 149 Shared Nets/Wires... 151 Shared Objects... 152 Shared Objects in Capital Logic... 155 Locating Shared Objects in a Project... 156 Finding, Navigating & Unsharing Shared Objects... 157 Module 6 Lab: Exercise #2... 158 Shared Objects Pin Management... 158 Shared Pin Lists in Capital Project... 159 Creating an SPL with a Plug Map... 160 V
Shared Object Names... 163 Placing a Shared Device on a Design... 163 Shared Conductors... 165 Shared Object Usages Report... 169 Revisions of Shared Objects... 170 Swapping Out Shared Object Revisions... 171 Module 6 Lab: Exercise #3... 173 Freezing/Unfreezing Shared Objects... 174 Composite Symbols as Shared Objects... 175 Build Lists... 177 Module 6 Lab: Exercise #4... 182 Module 7: Symbols and Borders... 183 Symbol Overview... 184 Creating a Symbol Library... 184 Elements of a Symbol... 185 Symbol Creation Process... 186 Changing a Pin`s Name, Attributes & Properties... 190 Adding a Property to a Pin... 192 Symbol Properties... 193 Additional Symbol Tasks... 194 Symbol Library Management... 195 Module 7 Lab: Exercise #1... 196 Composite Symbols... 197 Composite Symbols in Capital Logic... 198 Connectivity in Symbols... 200 VI
Module 7 Lab: Exercise #2... 202 Borders... 203 Border Preferences... 204 Creating a Border... 205 Adding Zones to a Border Symbol... 206 Inserting Images... 208 Properties... 209 Intelligent Text... 210 Module 7 Lab: Exercise #3... 215 Module 8: Options... 217 Options Overview... 218 Defining Options... 219 Assigning Options to Designs... 221 Mandating Applicable Options... 221 Deleting Options... 222 Assigning Options to Objects... 222 Configurations... 223 Filtered Configuration Views... 225 Option Combinations... 226 Module Code Definition... 226 Module 8 Lab: Exercise #1... 227 Module 9: Design Validation... 229 Design Rule Checks... 230 Design Rule Checks: Manually Run... 232 Design Rule Checks: Background Run... 233 VII
Design Rule Checks: Release Design... 234 Types of DRCs... 235 Defining and Applying Design Rules... 239 Module 9 Lab: Exercise #1... 240 Design Revisions... 240 Engineering Change Orders... 242 Setting & Tracking ECO Progress... 243 Compare Designs... 244 To Do Lists... 246 Module 9 Lab: Exercise #2... 246 Signal Tracing... 247 Design & Project Exports/Imports... 248 Module 9 Lab: Exercise #3... 250 Module 10: Design Management... 251 Design Folder Editing... 252 Design Abstractions... 254 Module 10 Lab: Exercises #1 & #2... 255 Storing Circuit Information as a Composite Symbol... 256 Copying Designs Within a Project... 257 Copying Designs to Another Project... 258 Moving Diagram Content... 261 Style Sets... 261 Releasing Designs... 264 Module 10 Lab: Exercises #3 & #4... 265 Capital Logic and Rules... 266 VIII
Printing Logic Diagrams... 267 Domains... 269 Design Scope... 272 Simulation of Electrical Schematics... 273 Capital Logic Bridges... 275 Module 10 Lab: Exercises #5 through #8... 276 Appendix 1: Capital Logic's User Interface... A-1 Appendix 2: Object Naming... A-12 Appendix 3: Preferences... A-25 Appendix 4: Shared Objects... A-29 Appendix 5: Capital Bridges... A-38 Appendix 6: Capital Enterprise Reporter... A-40 Appendix 7: Block Diagrams... A-46 Appendix 8: Report Builder... A-48 List of Capital Shortcuts/Hot Keys... 327 IX