Combinational Equivalence Checking

Similar documents
Advanced VLSI Design Prof. Virendra K. Singh Department of Electrical Engineering Indian Institute of Technology Bombay

The Einstein Puzzle. Hints to Einstein Puzzle. Hints to Einstein Puzzle (cont) Specify Einstein Puzzle in SAT. Specify Einstein Puzzle in SAT

EECS 219C: Formal Methods Boolean Satisfiability Solving. Sanjit A. Seshia EECS, UC Berkeley

Normal Forms for Boolean Expressions

EECS 219C: Computer-Aided Verification Boolean Satisfiability Solving. Sanjit A. Seshia EECS, UC Berkeley

Boolean Satisfiability Solving Part II: DLL-based Solvers. Announcements

Boolean Representations and Combinatorial Equivalence

Boolean Functions (Formulas) and Propositional Logic

Satisfiability. Michail G. Lagoudakis. Department of Computer Science Duke University Durham, NC SATISFIABILITY

QuteSat. A Robust Circuit-Based SAT Solver for Complex Circuit Structure. Chung-Yang (Ric) Huang National Taiwan University

CS-E3200 Discrete Models and Search

An Experimental Evaluation of Conflict Diagnosis and Recursive Learning in Boolean Satisfiability

Combinational Equivalence Checking Using Satisfiability and Recursive Learning

Symbolic Methods. The finite-state case. Martin Fränzle. Carl von Ossietzky Universität FK II, Dpt. Informatik Abt.

Practical SAT Solving

Zchaff: A fast SAT solver. Zchaff: A fast SAT solver

On Resolution Proofs for Combinational Equivalence Checking

SAT Solvers. Ranjit Jhala, UC San Diego. April 9, 2013

On the Relation between SAT and BDDs for Equivalence Checking

ESE535: Electronic Design Automation CNF. Today CNF. 3-SAT Universal. Problem (A+B+/C)*(/B+D)*(C+/A+/E)

Satisfiability (SAT) Applications. Extensions/Related Problems. An Aside: Example Proof by Machine. Annual Competitions 12/3/2008

PROPOSITIONAL LOGIC (2)

SAT Solvers: A Condensed History. Sharad Malik Princeton University COS 598d 3/1/2010

Solving 3-SAT. Radboud University Nijmegen. Bachelor Thesis. Supervisors: Henk Barendregt Alexandra Silva. Author: Peter Maandag s

On Resolution Proofs for Combinational Equivalence

Satisfiability Solvers

Constraint Satisfaction Problems

4.1 Review - the DPLL procedure

Chapter 2 PRELIMINARIES

Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other Applications

Reliable Verification Using Symbolic Simulation with Scalar Values

An Introduction to SAT Solvers

Learning Techniques for Pseudo-Boolean Solving and Optimization

ABC basics (compilation from different articles)

Heuristic Backtracking Algorithms for SAT

Circuit versus CNF Reasoning for Equivalence Checking

12. Use of Test Generation Algorithms and Emulation

Deductive Methods, Bounded Model Checking

Integrating a SAT Solver with Isabelle/HOL

Automated Software Solutions to Logic Restructuring and Silicon Debug. Yu-Shen Yang

A Satisfiability Procedure for Quantified Boolean Formulae

1 Model checking and equivalence checking

BerkMin: a Fast and Robust Sat-Solver

BITCOIN MINING IN A SAT FRAMEWORK

HECTOR: Formal System-Level to RTL Equivalence Checking

Finite Model Generation for Isabelle/HOL Using a SAT Solver

Example: Map coloring

SEARCHING FOR TRUTH: TECHNIQUES FOR SATISFIABILITY OF BOOLEAN FORMULAS

Design Diagnosis Using Boolean Satisfiability

Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation

SAT/SMT Solvers and Applications

CS-E3220 Declarative Programming

Massively Parallel Seesaw Search for MAX-SAT

1.4 Normal Forms. We define conjunctions of formulas as follows: and analogously disjunctions: Literals and Clauses

Boolean Satisfiability: From Theoretical Hardness to Practical Success. Sharad Malik Princeton University

DM841 DISCRETE OPTIMIZATION. Part 2 Heuristics. Satisfiability. Marco Chiarandini

Robust Boolean Reasoning for Equivalence Checking and Functional Property Verification

ECE 587 Hardware/Software Co-Design Lecture 11 Verification I

CDCL SAT Solvers. Joao Marques-Silva. Theory and Practice of SAT Solving Dagstuhl Workshop. April INESC-ID, IST, ULisbon, Portugal

On Computing Minimum Size Prime Implicants

Efficient SAT-based Boolean Matching for FPGA Technology Mapping

Chapter 27. Other Approaches to Reasoning and Representation

VLSI Testing. Fault Simulation. Virendra Singh. Indian Institute of Science Bangalore

Large-scale Boolean Matching

DIGITAL DESIGN TECHNOLOGY & TECHNIQUES

Chaff: Engineering an Efficient SAT Solver

Foundations of AI. 8. Satisfiability and Model Construction. Davis-Putnam, Phase Transitions, GSAT and GWSAT. Wolfram Burgard & Bernhard Nebel

SAT Solver Heuristics

Using Problem Symmetry in Search Based Satisfiability Algorithms. Mukul R. Prasad Fujitsu Labs. of America Sunnyvale, CA

Unrestricted Backtracking Algorithms for Satisfiability

A Scalable Algorithm for Minimal Unsatisfiable Core Extraction

Course Summary! What have we learned and what are we expected to know?

Module 4. Constraint satisfaction problems. Version 2 CSE IIT, Kharagpur

Notes on Non-Chronologic Backtracking, Implication Graphs, and Learning

DPLL(Γ+T): a new style of reasoning for program checking

MajorSat: A SAT Solver to Majority Logic

A Novel SAT All-Solutions Solver for Efficient Preimage Computation

Random backtracking in backtrack search algorithms for satisfiability

On Proof Systems Behind Efficient SAT Solvers. DoRon B. Motter and Igor L. Markov University of Michigan, Ann Arbor

Dipartimento di Elettronica Informazione e Bioingegneria. Cognitive Robotics. SATplan. Act1. Pre1. Fact. G. Gini Act2

Parallelizing SAT Solver With specific application on solving Sudoku Puzzles

Acceleration of SAT-based Iterative Property Checking

Administrative. Local Search!

N-Queens problem. Administrative. Local Search

VLSI Testing. Virendra Singh. Bangalore E0 286: Test & Verification of SoC Design Lecture - 7. Jan 27,

Study of efficient techniques for implementing a Pseudo-Boolean solver based on cutting planes

CSc Parallel Scientific Computing, 2017

Encoding The Lexicographic Ordering Constraint in Satisfiability Modulo Theories

Using SAT for Combinational Equivalence Checking

DPLL(T ):Fast Decision Procedures

Research Collection. Formal background and algorithms. Other Conference Item. ETH Library. Author(s): Biere, Armin. Publication Date: 2001

Computer-Aided Program Design

SAT Based Efficient Directed Test Generation Techniques

Guiding CNF-SAT Search via Efficient Constraint Partitioning

Checking Satisfiability of a Conjunction of BDDs

Addressing Verification Bottlenecks of Fully Synthesized Processor Cores using Equivalence Checkers

Set 5: Constraint Satisfaction Problems Chapter 6 R&N

3. Formal Equivalence Checking

Solving Satisfiability with a Novel CPU/GPU Hybrid Solution

A Practical Reconfigurable Hardware Accelerator for Boolean Satisfiability Solvers

Transcription:

Combinational Equivalence Checking Virendra Singh Associate Professor Computer Architecture and Dependable Systems Lab. Dept. of Electrical Engineering Indian Institute of Technology Bombay viren@ee.iitb.ac.in EE 709: Testing & Verification of VLSI Circuits Lecture 10 (Jan 24, 2012)

DPLL algorithm for SAT Given : CNF formula f(v 1,v 2,..,v k ), and an ordering function Next_Variable Example : [Davis, Putnam, Logemann, Loveland 1960,62] ( a b)( a c)( a b) b c 0 1 0 1 C 1 C 2 C 3 CONFLICT! C 1 0 a 1 C 3 C 2 SAT! Jan 24, 2012 EE-709@IITB 2

Basic Backtracking Search 1 (a + b + c) a 2 3 (a + b + c) ( a + b + c) b b 4 5 (a + c + d) ( a + c + d) c c c 6 7 ( a + c + d) ( b + c + d) d d d d d 8 ( b + c + d) Jan 24, 2012 EE-709@IITB 3

Basic Search with Implications 1 (a + b + c) a 2 3 4 (a + b + c) ( a + b + c) (a + c + d) c b c b 5 ( a + c + d) 6 7 8 ( a + c + d) ( b + c + d) 86 5 b a 75 34 ( b + c + d) d c 86 5 b c 75 34 86 d 6 6 6 Jan 24, 2012 EE-709@IITB 4

DPLL algorithm: Unit clause rule Rule: Assign to true any single literal clauses. ( a b c) = = 0 0 c = 1 Apply Iteratively: Boolean Constraint Propagation (BCP) a( a c)( b c)( a b c)( c e)( d e)( c d e) c( b c)( c e)( d e)( c d e) e( d e) Jan 24, 2012 EE-709@IITB 5

Pure Literal Rule A variable is pure if its literals are either all positive or all negative Satisfiability of a formula is unaffected by assigning pure variables the values that satisfy all the clauses containing them j = (a +c )(b+ c )(b + d)( a + b + d) Set c to 1; if j becomes unsatisfiable, then it is also unsatisfiable when c is set to 0. Jan 24, 2012 EE-709@IITB 6

Resolution (original DP) Iteratively apply resolution (consensus) to eliminate one variable each time i.e., consensus between all pairs of clauses containing x and x formula satisfiability is preserved Stop applying resolution when, Either empty clause is derived instance is unsatisfiable Or only clauses satisfied or with pure literals are obtained instance is satisfiable j = (a + c)(b + c)(d + c)( a + b + c) j 1 = (a + a + b)(b + a + b )(d + a + b ) = (d + a + b ) Eliminate variable c Instance is SAT! Jan 24, 2012 EE-709@IITB 7

Stallmarck s Method (SM) in CNF Recursive application of the branch-merge rule to each variable with the goal of identifying common conclusions j = (a + b)( a + c) ( b + d)( c + d) Try a = 0: (a = 0) (b = 1) (d = 1) C(a = 0) = {a = 0, b = 1, d = 1} Try a = 1: (a = 1) (c = 1) (d = 1) C(a = 1) = {a = 1, c = 1, d = 1} C(a = 0) C(a = 1) = {d = 1} Any assignment to variable a implies d = 1. Hence, d = 1 is a necessary assignment! Recursion can be of arbitrary depth Jan 24, 2012 EE-709@IITB 8

Recursive Learning (RL) in CNF Recursive evaluation of clause satisfiability requirements for identifying common assignments j = (a + b)( a + d) ( b + d) Try a = 1: (a = 1) (d = 1) C(a = 1) = {a = 1, d = 1} Try b = 1: (b = 1) (d = 1) C(b = 1) = {b = 1, d = 1} C(a = 1) C(b = 1) = {d = 1} Every way of satisfying (a + b) implies d = 1. Hence, d = 1 is a necessary assignment! Recursion can be of arbitrary depth Jan 24, 2012 EE-709@IITB 9

SM vs. RL Both complete procedures for SAT Stallmarck s method: hypothetic reasoning based on variables Recursive learning: hypothetic reasoning based on clauses Both can be integrated into backtrack search algorithms Jan 24, 2012 EE-709@IITB 10

Local Search Repeat M times: Randomly pick complete assignment Repeat K times (and while exist unsatisfied clauses): Flip variable that will satisfy largest number of unsat clauses j = (a + b)( a + c) ( b + d)( c + d) Pick random assignment j = (a + b)( a + c) ( b + d)( c + d) Flip assignment on d j = (a + b)( a + c) ( b + d)( c + d) Instance is satisfied! Jan 24, 2012 EE-709@IITB 11

Comparison Local search is incomplete If instances are known to be SAT, local search can be competitive Resolution is in general impractical Stallmarck s Method (SM) and Recursive Learning (RL) are in general slow, though robust SM and RL can derive too much unnecessary information For most EDA applications backtrack search (DP) is currently the most promising approach! Augmented with techniques for inferring new clauses/implicates (i.e. learning)! Jan 24, 2012 EE-709@IITB 12

Techniques for Backtrack Search Conflict analysis Clause/implicate recording Non-chronological backtracking Incorporate and extend ideas from: Resolution Recursive learning Stallmarck s method Formula simplification & Clause inference [Li,AAAI00] Randomization & Restarts [Gomes&Selman,AAAI98] Jan 24, 2012 EE-709@IITB 13

Clause Recording During backtrack search, for each conflict create clause that explains and prevents recurrence of same conflict j = (a + b)( b + c + d) ( b + e)( d + e + f) Assume (decisions) c = 0 and f = 0 Assign a = 0 and imply assignments A conflict is reached: ( d + e + f) is unsat (a = 0) (c = 0) (f = 0) (j = 0) (j = 1) (a = 1) (c = 1) (f = 1) create new clause: (a + c + f) Jan 24, 2012 EE-709@IITB 14

Clause Recording Clauses derived from conflicts can also be viewed as the result of applying selective consensus j = (a + b)( b + c + d) ( b + e)( d + e + f) consensus (a + c + d) (a + e) (a + c + e + f) (a + c + f) Jan 24, 2012 EE-709@IITB 15

Non-Chronological Backtracking During backtrack search, in the presence of conflicts, backtrack to one of the causes of the conflict j = (a + b)( b + c + d) ( b + e)( d + e + f) (a + c + f)( a + g)( g + b)( h + j)( i + k) Assume (decisions) c = 0, f = 0, h = 0 and i = 0 Assignment a = 0 caused conflict clause (a + c + f) created (a + c + f) implies a = 1 A conflict is again reached: ( d + e + f) is unsat (a = 1) (c = 0) (f = 0) (j = 0) (j = 1) (a = 0) (c = 1) (f = 1) create new clause: ( a + c + f) Jan 24, 2012 EE-709@IITB 16

Non-Chronological Backtracking Created clauses: (a + c + f) and ( a + c + f) Apply consensus: new unsat clause (c + f) backtrack to most recent decision: f = 0 created clauses/implicates: (a + c + f), ( a + c + f), and (c + f) 0 i a 0 1 0 0 h c 0 f (c + f) Jan 24, 2012 EE-709@IITB 17

Ideas from other Approaches Resolution, Stallmarck s method and recursive learning can be incorporated into backtrack search (DP) create additional clauses/implicates anticipate and prevent conflicting conditions identify necessary assignments allow for non-chronological backtracking Resolution within DP: (a + b + c) ( a + b + d) consensus (b + c + d) (b + c + d) Unit clause! Clause provides explanation for necessary assignment b = 1 Jan 24, 2012 EE-709@IITB 18

Stallmarck s Method within DP j = (a + b + e)( a + c + f)( b + d) ( c + d + g) Implications: (a = 0) (e = 0) (b = 1) (d = 1) (a = 1) (f = 0) (c = 1) (c = 1) (g = 0) (d = 1) (e = 0) (f = 0) (g = 0) (d = 1) Clausal form: consensus (b + e + c + f) (d + e + c + f) (e + f + g + d) (e + f + g + d) Unit clause! Clause provides explanation for necessary assignment d = 1 Jan 24, 2012 EE-709@IITB 19

Recursive Learning within DP j = (a + b + c)( a + d + e) ( b + d + c) Implications: (a = 1) (e = 0) (d = 1) (b = 1) (c = 0) (d = 1) consensus (b + c + e + d) consensus (c = 0) ((e = 0) (c = 0)) (d = 1) (c + e + d) Clausal form: (c + e + d) Unit clause! Clause provides explanation for necessary assignment d = 1 Jan 24, 2012 EE-709@IITB 20

The Power of Consensus Most search pruning techniques can be explained as particular ways of applying selective consensus Conflict-based clause recording Non-chronological backtracking Extending Stallmarck s method to backtrack search Extending recursive learning to backtrack search Clause inference conditions General consensus is computationally too expensive! Most techniques indirectly identify which consensus operations to apply! To create new clauses/implicates To identify necessary assignments Jan 24, 2012 EE-709@IITB 21

SAT Solvers Today Capacity: Formulas upto a million variables and 3-4 million clauses can be solved in few hours Only for structured instances e.g. derived from realworld circuits & systems Tool offerings: Public domain GRASP : Univ. of Michigan SATO: Univ. of Iowa zchaff: Princeton University BerkMin: Cadence Berkeley Labs. Commercial PROVER: Prover Technologies Jan 24, 2012 EE-709@IITB 22

Solving circuit problems as SAT a b c f h d e g i Input Vector Assignment? Primary Output i to 1? Jan 24, 2012 EE-709@IITB 23

SAT formulas for simple gates a b c a b c ( c a)( c b)( c a b) a b a b c ( a b)( a b) ( c a)( c b)( c a b) Jan 24, 2012 EE-709@IITB 24

Solving circuit problems as SAT Set of clauses representing function of each gate Unit literal clause asserting output to 1 a b c d e f g h i ( b f )( c f )( b c f ) ( d g)( e g)( d e g ) ( a h )( f h )( a f h) ( h i )( g i )( h g i) (i) Jan 24, 2012 EE-709@IITB 25

Combinational Equivalence Checking (CEC) Currently most practical and pervasive equivalence checking technology Nearly full automation possible Designs of up to several million gates verified in a few hours or minutes Hierarchical verification deployed Full chip verification possible Key methodology: Convert sequential equivalence checking to a CEC problem! Match Latches & extract comb. portions for EC Jan 24, 2012 EE-709@IITB 26

CEC in Today s ASIC Design Flow RTL Design Synthesis & optimization DFT insertion CEC CEC Routing ECO CEC IO Insertion Placement Clock tree synthesis CEC CEC CEC Jan 24, 2012 EE-709@IITB 27

Major Industrial Offerings of CEC Formality (Synopsys) Conformal Suite (Verplex, now Cadence) FormalPro (Mentor Graphics) Typical capabilities of these tools: Can handle circuits of up to several million gates flat in up to a few hours of runtime Comprehensive debug tool to pinpoint error-sources Counter-example display & cross-link of RTL and gatelevel netlists for easier debugging Ability to checkpoint verification process and restart from same point later What if capability (unique to FormalPro) Jan 24, 2012 EE-709@IITB 28

Combinational Equivalence Checking Functional Approach transform output functions of combinational circuits into a unique (canonical) representation two circuits are equivalent if their representations are identical efficient canonical representation: BDD Structural identify structurally similar internal points prove internal points (cut-points) equivalent find implications Jan 24, 2012 EE-709@IITB 29

Functional Equivalence If BDD can be constructed for each circuit represent each circuit as shared (multi-output) BDD use the same variable ordering! BDDs of both circuits must be identical If BDDs are too large cannot construct BDD, memory problem use partitioned BDD method decompose circuit into smaller pieces, each as BDD check equivalence of internal points Jan 24, 2012 EE-709@IITB 30

Functional Decomposition Decompose each function into functional blocks represent each block as a BDD (partitioned BDD method) define cut-points (z) verify equivalence of blocks at cut-points starting at primary inputs F G f 2 g 2 z z f 1 g 1 x y x y Jan 24, 2012 EE-709@IITB 31

Cut-Points Resolution Problem If all pairs of cut-points (z 1,z 2 ) are equivalent so are the two functions, F,G If intermediate functions (f 2,g 2 ) are not equivalent the functions (F,G) may still be equivalent this is called false negative Why do we have false negative? functions are represented in terms of intermediate variables to prove/disprove equivalence must represent the functions in terms of primary inputs (BDD composition) z 1 x f 1 f 2 y F z 2 x g 1 g 2 y G Jan 24, 2012 EE-709@IITB 32

Cut-Point Resolution Theory Let f 1 (x)=g 1 (x) x if f 2 (z,y) g 2 (z,y), z,y then f 2 (f 1 (x),y) g 2 (f 1 (x),y) F G if f 2 (z,y) g 2 (z,y), z,y f 2 (f 1 (x),y) g 2 (f 1 (x),y) F G F G We cannot say if F G or not z x f 1 f 2 y z x g 1 g 2 y False negative two functions are equivalent, but the verification algorithm declares them as different. Jan 24, 2012 EE-709@IITB 33

Cut-Point Resolution How to verify if negative is false or true? Procedure 1: create a miter (XOR) between two potentially equivalent nodes/functions perform ATPG test for stuck-at 0 find test pattern to prove F G efiicient for true negative (gives test vector, a proof) inefficient when there is no test 0, F G (false negative) 1, F G (true negative) F G Jan 24, 2012 EE-709@IITB 34

Cut-Point Resolution Procedure 2: create a BDD for F G perform satisfiability analysis (SAT) of the BDD if BDD for F G =, problem is not satisfiable, false negative BDD for F G, problem is satisfiable, true negative F G = F G =, F G (false negative) Non-empty, F G Note: must compose BDDs until they are equivalent, or expressed in terms of primary inputs the SAT solution, if exists, provides a test vector (proof of non-equivalence) as in ATPG unlike the ATPG technique, it is effective for false negative (the BDD is empty!) Jan 24, 2012 EE-709@IITB 35

Thank you Jan 24, 2012 EE-709@IITB 36