Preliminary TK23H256 High Temperature ROM June 06, 2018 Product Proposal Features o 262,144 bit ROM o Up to 300 o C Operation o -100 ns Access Time (5V) o Fully Non-Volatile o 2.7V to 5.5V operation o High Temperature SOI Process o High Reliability Features o Internal ECC o Tungsten Metallization o Double Bonds o Interrupts on ECC failure. o Aluminum bonding standard o Gold pad / gold bonds available o Available in Die Form for Hybrid Use o Optional support for Multiplexed Address / Data o Available in Multiple Widths o 32Kx8, 16Kx16, 8Kx32 o Interrupt on ECC Failure o JTAG Boundary Scan o Multiple Package Options General Description The TK23H256 is a high temperature, masked ROM. Manufactured on an SOI process, it is designed to operate at temperatures of up to 300 o C. The data is permanently stored within the ROM. The Tekmos TK23H256 does not have any of the data retention issues associated with flash memories. The TK23H256 ROM may be programmed to be either 8, 16, or 32 bits wide. It may also be programmed to support a multiplexed address / data bus. The ROM contains built-in ECC circuitry. This circuitry will correct single bit errors, and detect two bit errors. If a bit failure occurs, the TK23H256 will generate an interrupt, allowing the address and defective data to be identified by the processor. The parts are manufactured in Ceramic packages. These are available in either through-hole or surface mount options. The part is also available in die form. The TK23H256 ROM has a Minimum Order Quantity (MOQ) of 500 Units. Up to 4 different ROM codes can be combined in a single order. ROM DIP PGA SOIC QFP QFN 32K x 8 32 44 42 48 32 16K x 16 40 44 42 48 44 8K x 32 N/A 68 N/A 68 68 32K x 8 Muxed A/D 28 44 42 48 32 www.tekmos.com
Mask Programming Options Option 1 ROM Configuration Programming option 1 selects the ROM configuration. The following options are available. Option ROM Configuration 1 Parallel 32K x 8 2 Parallel 16K x 16 3 Parallel 8K x 32 4 Parallel 32K x 8, Mux ed address / data Option 2 Disable ECC The ECC function can be disabled, resulting in an approximately 10 ns improvement in ROM access time. Option 3 Interrupt Options The interrupt can be programmed to be either active high or active low. And the output buffer can be programmed to be push-pull or open drain. Option 4 Base Address for ECC Control Functions The base address that is used for the unlock command for the ECC Control functions may be user programmed. The address must be chosen so that it will not be inadvertently accessed during normal program operation. It should also be configured so that the least significant 3 address bits are zero. ECC Control Functions The ROM control functions are accessed through 4 repeated reads. Each read must occur within 16 reads of the previous read. This allows for normal program accesses out of the ROM. The base address of the reads is programmable, so that it can be located out of commonly accessed program areas. The first 3 reads are always from the same base address. The address of the 4 th read determines the control function. The address base may be programmed by the user. ECC Control Functions Address Base Output the last ECC failure bit on D0-D5, and flag that says 1 or 2 errors exist on D6. Address Base+1 Output the ECC failure address bits A4-A11 on pins D0-D7. Address Base+2 Output the ECC failure address bits A12-A15 on pins D0-D3. Address Base+3 Reset the ECC interrupt flag. The following commands are for ROM test purposes. Address Base+4 Turn off the ECC. The next 32K reads (16K reads in x16 mode, 8K reads in x32 mode) will be made without ECC correction. Address Base+5 Output ECC data. The next 32K reads (16K reads in x16 mode, 8K reads in x32 mode) will show the 7 ECC bits on D0 through D6. Internally the ECC is calculated on a 64 bit word. ROM Architecture ROM Organization The TK23H256 uses a NOR architecture. Transistors are programmed by using a contact to connect them to the bit line. Internally, the ROM is organized as 512 rows by 568 bit lines. The bit lines are multiplexed together in groups of 8, before going into the sense amps. This produces a 71 bit internal word (64 bits plus 7 ECC bits). Output multiplexors are used after the ECC correction circuitry to create the x8, x16, or x32 configurations. ROM Cycle The ROM is kept in a precharge state when idle. When a read cycle is triggered, the precharge is turned off, and a single word line is enabled. The state of each bit line depends on the status of one transistor. If it is programmed, the bit line will be pulled to zero. If it is unprogrammed, then the bit line will remain a one. After the bit lines have had time to reach their programmed values, the sense amps are triggered, 2 www.tekmos.com 5/6/18
storing the read data. Then the word lines are turned off, and the chip returns to the precharge state. Address Clock Generation Address lines A0, A1, and A2 These address lines run the output multiplexor, and so do not trigger a new ROM cycle. Address lines A3 to A15 An internal clock generator is used to detect changes in these address lines, and generate a new ROM cycle. Should an address line change in the middle of a ROM cycle, that cycle will be aborted, and a new cycle will begin. The address clock generator is only active when chip enable is active. 3 www.tekmos.com 5/6/18
Electrical Specifications Maximum Ratings Characteristics Symbol Min Max Unit Supply Voltage Vdd -0.5 5.5 V Input Voltage Vin Vss 0.3 Vdd + 0.3 V Current Drain per Pin IOL 15 ma Operating Temperature Range Ta -55 +300 o C Storage Temperature range Tstg -55 +150 o C DC Electrical Specifications (Vdd = 5.0 V +/- 10%, Vss = 0 V, Ta = -55 o C to +300 o C) Characteristics Condition Symbol Min Max Unit Input high level VIH 0.7 * Vdd Vdd V Input low level VIL 0.3 * Vdd Vdd V Output high level Ioh = 8 ma VOH 0.0 0.8 V Output low level Iol = 8 ma VOL 2.4 Vdd V Leakage Current Ta = 25 o C IZ25 TBD ua Ta = 175 o C IZ175 TBD ua Ta = 250 o C IZ250 TBD ua Ta = 300 o C IZ300 TBD ua Supply current, Active mode, f = 1 MHz Ta = 25 o C IDD TBD ua Ta = 175 o C TBD ma Ta = 250 o C TBD ma Ta = 300 o C TBD ma Supply current, Active mode, f = 10 MHz Ta = 25 o C IDD TBD ma Ta = 175 o C TBD ma Ta = 250 o C TBD ma Ta = 300 o C TBD ma Supply current, Standby mode, Ta = 25 o C IDDSB TBD ua Ta = 175 o C TBD ua Ta = 250 o C TBD ua Ta = 300 o C TBD ua Pin Capacitance Ta = 25 o C CIO 10 pf AC Electrical Specifications (Vdd = 5.0 V +/- 10%, Vss = 0 V, Ta = -55 o C to +300 o C) Ta = 125 o C Ta = 175 o C Ta = 250 o C Ta = 300 o C Characteristics Symbol Min Max Min Max Min Max Min Max Unit Read Cycle Time trc 100 100 100 100 ns Address Access Time taa 100 100 100 100 ns Chip Enable Access Time tce 100 100 100 100 ns Page Access Time tpa 25 25 25 25 ns Output Enable Time toe 25 25 25 25 ns Output Hold After Address toh 0 0 0 0 ns Output High-Z Delay thz 20 20 20 20 ns Notes: 4 www.tekmos.com 5/6/18
Ordering Information Tekmos assigns each customer code a programming number, of the form Pxxxx. The complete part number becomes TK23H256-Pxxxx. Contact Information The TK23H256 be ordered directly from Tekmos Tekmos, Inc. 7901 E. Riverside Drive Building 2, Suite 150 Austin, TX 78744 512 342-9871 phone Sales@Tekmos.Com www.tekmos.com Revision History Date Revision Description 7/21/17 0.1 Engineering Draft 5/6/18 0.9 Pre-release 2018 Tekmos, Inc. Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Tekmos Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Tekmos products as critical components in life support systems is not authorized except with express written approval by Tekmos. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Tekmos logo and name are registered trademarks of Tekmos, Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. All rights reserved. Terms and product names in this document may be trademarks of others. 5 www.tekmos.com 5/6/18