TDTS01. Computer Aided Design of Electronics. Lab Compendium

TDTS01 Computer Aided Design of Electronics Lab Compendium 2012.02.03-00

Authors history Nima Aghaee, 2012 Adrian Lifa, 2011 Zhiyuan He, 2010 Acknowledgments The authors would like to thank Dimitar Nikolov for his contributions to chapters 5. Have a look at chapter 6, Lab Assignments, first! Table of Contents TDTS01 1 Chapter 1 Introduction 3 Chapter 2 Preparation for the Lab 5 2.1 Setting Up the CAD Tool Environment 5 2.2 Setting Up Environment Variables 5 2.3 Copying Files for Tutorial 6 Chapter 3 Tutorial of System-Level Design and Simulation 8 3.1 Design Specification for Array Accumulator 8 3.2 Behavioral Design in VHDL 9 3.3 Compiling Your Design for Simulation 11 3.4 Simulation of Behavioral Design 14 Chapter 4 Tutorial of Logic Synthesis 17 Chapter 5 Tutorial of Test Pattern Generation 23 Chapter 6 Lab Assignments 26 2

Chapter 1 Introduction The aim of this lab is to get familiar with a typical design flow: 1. Learn how to work with typical tools for functional simulation, gate level synthesis, and test pattern generation, 2. Use these tools in order to produce a functionally correct design, and then to improve some aspect of the design (only testability is required for this lab) by iterative modifications of the design (repeating the design flow each time). In order to understand the design flow (see Figure 1), students will be given an example of a hardware design in the tutorial with the following steps: preliminary hardware specification behavioral design on the system level simulation of the behavioral design high-level synthesis (HLS) of the design to the register-transfer level (RTL) simulation of the structural design logic synthesis of the design to the gate level test pattern generation A hardware description language, VHDL, is used for the behavioral and structural design. Several computer-aided design tools from Mentor Graphics are used for the simulation; synthesis, and test pattern generation (see Figure 1). Students are required to follow the above steps to make their own designs and write the final reports. During the design phase, a designer usually iterates a couple of times and modifies the design in order to improve some aspects of the design. These aspects are evaluated using the CAD tools. For example after logic synthesis with LeonardoSpectrum, designer will have a gate-level estimate of the area and delay. Another example is the testability statistics which will be available after test pattern generation using FastScan. There are other important aspects for a design, e.g. power consumption and reliability, as well. However in this lab we focus on area, delay, and testability. Please first read the whole section once, and then start working on the computers. It gives you an insight about what you are going to do and what you should expect to happen. Parts of this tutorial are copyright Mentor Graphics Corporation 1990-2010. All rights reserved.

Figure 1. Design flow for this lab 4

Chapter 2 Preparation for the Lab Before starting the lab for hardware design and test, you have to set up the lab environment. Please use TERMINAL other than CONSOLE for the lab! 2.1 Setting Up the CAD Tool Environment 1. Open a terminal (not a console window). Load a module called prog/mentor/c.2 which is used by Mentor Graphics tools ModelSim, DFTAdvisor, and FlexTest. First of all, check if this module has already been loaded with the following command (note that % is used in this tutorial to denote the command prompt): % module list If you cannot find the module prog/mentor/c.2 in the module list, you can issue the following command to initially add the module to the login setup file.login : % module initadd prog/mentor Then load this module for your present terminal: % module load prog/mentor 2. Initially load a module called prog/mentor/fpgadv which is used by Mentor Graphics synthesis tool LeonardoSpectrum, if it has not been loaded yet, with the following command: % module initadd prog/mentor/fpgadv Then load this module for your present shell: % module load prog/mentor/fpgadv Make sure that the module prog/mentor/c.2 is always loaded BEFORE the module prog/mentor/fpgadv! 2.2 Setting Up Environment Variables In this step you will set environment variables for your shell. 1. Set the environment variable MGC_HOME which should point to the location of the most recent release of Mentor Graphics tools. First, use the following command % setenv grep MGC_HOME

to check if MGC_HOME = /sw/mentor/c.2/mentor If not, set MGC_HOME with the desired value: % setenv MGC_HOME /sw/mentor/c.2/mentor 2. Set the environment variable MODEL_TECH which should point to the bin directory of the most recent release of the ModelTech tools, including ModelSim. First, check if MODEL_TECH = /sw/mentor/c.2/fpgadv/4.0/modeltech/bin If not, set MODEL_TECH with the desired value. 3. Check and/or set the environment variable PATH : The path $MGC_HOME/bin which contains the executable files for Mentor Graphics applications, and the path $MODEL_TECH which contains executable files for ModelSim should be present at the beginning of the PATH. If this is not the case, use the following command to set the PATH variable accordingly: % setenv PATH /sw/mentor/c.2/mentor/bin:/sw/mentor/c.2/fpgadv/4.0/modeltech/bin:$path Repeated below with large fonts, but there is no line-return/enter in between (it is broken to fit in page margins): % setenv PATH /sw/mentor/c.2/mentor/bin:/sw/mentor/c.2/fpgadv/4.0/modeltech/bi n:$path Make sure that version 4.0 of Modeltech is specified first in PATH and not version 6.2! 2.3 Copying Files for Tutorial 1. Move to the directory where you want to create a copy of the tutorial data (it can be your root directory) and execute the commands below % mkdir hls % mkdir hls/src % cp /home/tdts01/hls_tutorial/std_arit.vhd hls/src/. % cp /home/tdts01/hls_tutorial/array_acc_behavioral.vhd hls/src/. % cp /home/tdts01/hls_tutorial/tb_array_acc_behavioral.vhd hls/src/. % cp /home/tdts01/hls_tutorial/array_acc_structural.vhd hls/src/. % cp /home/tdts01/hls_tutorial/tb_array_acc_structural.vhd hls/src/. % cp /home/tdts01/hls_tutorial/c35_corelib.atpg hls/src/. 6

2. Navigate to the created hls/src directory and check if all files are correctly copied. Please note that the following files should be observed: std_arit.vhd -- source file of the standard binary-component library array_acc_behavioral.vhd and array_acc_structural.vhd -- source files of the behavioral and structural design, respectively tb_array_acc_behavioral.vhd and tb_array_acc_structural.vhd -- source files of the test bench for behavioral and structural design, respectively c35_corelib.atpg -- AMS c35 ATPG library with scan flip-flops 7

Chapter 3 Tutorial of System-Level Design and Simulation In this chapter, you will learn to: write a specification for the design generate a VHDL description for the behavioral design compile the VHDL source file into a library used for simulation use a simulator called ModelSim to verify the functionality of the behavioral design 3.1 Design Specification for Array Accumulator An Array Accumulator (ARRAY_ACC) can accumulatively add up the value of each element in an input array X and output the sum value to an output port SUM. In order to show a hardware design which is of the capability to run concurrent operations, the value of each element in array X is added with that of another input array Y, and each sum value is assigned to the corresponding element of an array variable Z (not a output port). Figure 2 shows the logic symbol for the ARRAY_ACC design, where CLK is the clock port, and RST is the reset port. X and Y are two input arrays with L elements. SUM is the output port for the sum value, and DV is the data valid port. Note that only when DV outputs 1, the sum value at the port SUM becomes valid. CLK SUM RST X(0 to L-1) L ARRAY_ACC DV Y(0 to L-1) L Figure 2. Logic symbol for the ARRAY_ACC design

3.2 Behavioral Design in VHDL The VHDL description of the behavioral design of ARRAY_ACC is shown below: 1 -- Array Accumulator Behavioral Description 2 -- VHDL Pre-synthesis Behavioral Model 3 4 package ARRAY_ACC_PKG is 5 type UI16 is range 0 to 2 ** 16-1; 6 type ARRAY_UI16 is array ( UI16 range <> ) of UI16; 7 end; 8 use work.array_acc_pkg.all; 9 10 entity ARRAY_ACC is 11 generic ( ARRAY_LEN : UI16 := 10 ); 12 port ( X : in ARRAY_UI16 ( 0 to ARRAY_LEN - 1 ); 13 Y : in ARRAY_UI16 ( 0 to ARRAY_LEN - 1 ); 14 CLK : in bit; 15 RST : in bit; 16 SUM : out UI16; 17 DV : out bit ); 18 end ARRAY_ACC; 19 20 architecture BEHAVIORAL of ARRAY_ACC is 21 Begin 22 P_MAIN : process 23 variable SUM_VAR : UI16; 24 variable IDX_VAR : UI16; 25 variable Z_VAR : ARRAY_UI16 ( 0 to ARRAY_LEN 1 ); 26 begin 27 LOOP_MAIN : loop 28 wait until ( CLK'event and CLK = '0' ) or ( RST = '1' ); 29 exit LOOP_MAIN when RST = '1'; 30 SUM_VAR := 0; 31 IDX_VAR := 0; 32 while ( IDX_VAR < ARRAY_LEN ) loop 33 SUM_VAR := SUM_VAR + X( IDX_VAR ); 34 Z_VAR( IDX_VAR ) := X( IDX_VAR ) + Y( IDX_VAR ); 35 IDX_VAR := IDX_VAR + 1; 36 end loop; 37 SUM <= SUM_VAR; 38 DV <= '1'; 39 end loop LOOP_MAIN; 40 SUM <= 0; 41 DV <= '0'; 42 end process P_MAIN; 43 end BEHAVIORAL; Figure 3. VHDL description of the behavioral design of ARRAY_ACC Below are the explanations for the behavioral description: Lines 4-8: Type definition of the unsigned integer and the array of unsigned integer. For simplicity we only use unsigned integers in this design. Lines 10-18: Declaration of the entity ARRAY_ACC which has four input ports and two output ports. Input ports consists of X, Y, CLK, and RST. X and Y are two input arrays, CLK is the clock port, and RST is the reset port. Output ports include SUM and DV. SUM is the sum of element values of array X, and DV outputs the data valid signal. 9

Lines 20-26: The architecture of ARRAY_ACC contains one process. Three variables SUM_VAR, IDX_VAR, and Z_VAR are created to store temporary values. SUM_VAR is used to store the present sum value of the calculated elements in array X. IDX_VAR stores the present index value for array X, used for addressing the element which should be currently calculated. Z_VAR is an array which stores the sum of each pair of elements with the same index value in arrays X and Y. Lines 22-42: Definition of main body of the algorithm. SUM_VAR and IDX_VAR are initialized with the value 0 (lines 30 and 31). Lines 32-36: In the WHILE loop, all the elements in the arrays X and Y are explored. The value of each element in array X is accumulatively added to the variable SUM_VAR. The values of each pair of elements in X and Y are added and the sum value is stored in the corresponding element in array Z. The index IDX_VAR is incremented at every iteration step and is used for quitting the loop when it gets equal to the right bound value of the arrays. Lines 37-38: Output the value of SUM_VAR and set the data valid port DV to 1 when the WHILE loop is terminated. Lines 40-41: When the reset is active (RST = '1', line 29), we exit the main loop (LOOP_MAIN), and after that we reset the value of the SUM and DV output ports. In the following sections (3.3 and 3.4) we will compile and simulate our designs. In this compendium an old version of the ModelSim(R) which is available on the university s server, is used. When you are developing a new VHDL project, you may alternatively download and install the up-to-date student version of the ModelSim on your personal computers to have an easier life. In case you want to do the work remotely (SSH), use a command similar to: ssh -Y your_user_name@astmatix.ida.liu.se 10

3.3 Compiling Your Design for Simulation In this section, we will use the GUI of ModelSim in order to compile the VHDL source codes of the ARRAY_ACC design for simulation. 1. Invoke the ModelSim simulator: % $MODEL_TECH/vsim & 2. Click Create a Project. 3. Set the Project s Home to the desired directory (your choice) by Browse... button. 4. Set the Projects Name to a desired name (your choice). For this compendium we use hls as project name. 5. Press OK. 6. You are asked if you want to create a new HDL source file. Here we are going to use the HDL source files that you have copied to src directory. Therefore, press No. 11

7. Now in the welcome window shown under point 1, in front of Open Project button, select the path-name of your project. Open it by pressing Open Project. 8. Now you see the ModelSim window as shown above. In order to copy the VHDL source files to the project directory, do: File >> New >> Import Source. 9. In Import Project Source File window press Browse and navigate to the src directory that you have the source files there. Choose array_acc_behavioral.vhd. 10. You will be asked if you would like to edit the newly imported file. Press No. 11. Repeat points 8 to 10 for tb_array_acc_behavioral.vhd. 12. In order to compile the source files and add them to the project, do: Options >> Edit Project. 13. The Edit Project window will open as shown above. Make sure you are on Source List tab. Press the downward arrow or Browse button and select array_acc_behavioral.vhd. The Complie button will become active. 14. Press Compile and wait until the compile is done. The Add to Library button will become active. 15. Press Add to Library button. Some informative windows may show. 16. Repeat points 14 and 15 for tb_array_acc_behavioral.vhd. 12

17. Navigate to Project Build tab on the Edit Project window shown below. 18. Press Edit Script and check if the following lines are present in the file that has been opened. vcom -reportprogress 300 -work work {$MODELSIM_PROJECT/array_acc_behavioral.vhd} vcom -reportprogress 300 -work work {$MODELSIM_PROJECT/tb_array_acc_behavioral.vhd} The order of the lines represents the order that the vhdl files will be compiled by vcom command when the project is being compiled. The vhdl files are shown at the end of the lines. 19. Press Done. It goes back to ModelSim main window. 20. On the ModelSim main window showed under point 7, do the following in order to compile the project. Design >> Compile Project. Some progress bars may show. <Please browse to the next page> 13

21. In order to make sure that the project has been compiled correctly, one can check the Transcript window. It should be similar to the below picture. 3.4 Simulation of Behavioral Design 1. We can continue from section 3.3 without closing the ModelSim. Otherwise, ModelSim should be invoked similar to point 1 in section 3.3 and then the project should be opened similar to point 7 in section 3.3 2. In order to open the design for simulation, do: Design >> Load Design 14

3. Select [test_bench_behavioral Architecture] as shown in the Load Design window picture under point 2 and press Load. 4. Now the design is loaded and we are back to the ModelSim main window. In order to see what signals are present in your design, do: View >> Signals. 5. Move the cursor to the Signals window and execute the following pull-down menus: View >> Wave >> Signals in Design. The signals listed in the Signals window are added to the Wave window. 6. Move the cursor to the Signals window, then execute the following pull-down menus: View >> List >> Signals in Design. The signals listed in the Signals window are added to the List window 7. Expand the Wave window to the full width of the screen for the convenience of observing the waveforms. 8. Move the cursor to the ModelSim Main Window and execute the following pulldown menu: Run >> Run 100 ns. 9. We can use two shortcuts shown in the following picture by black/yellow arrows in order to Run the simulation (for a duration which is set on the ModelSim main window) and in order to zoom on the existing waveforms. 10. From the wave window, execute the pull-down menu Zoom >> Full. Place the mouse pointer on the blue cursor, hold down the Select mouse button (the left button) and slide the cursor across the window to examine the results. The expected results in the Wave window are shown below: 15

Observe the simulation results and the behavior of your VHDL model. Check if the sum was correctly calculated for each element in the input array. Pay attention to the time that the DV port was set to 1 for the first time. Compare the time that DV port is set to 1 in the simulation of the behavioral design and the structural design. Explain the reason of the observed difference in your final report. Before going further in the compendium, please read Tutorial of High-Level Synthesis. 16

Chapter 4 Tutorial of Logic Synthesis Before going further in the compendium, please read Tutorial of High-Level Synthesis. LeonardoSpectrum is a suite of high-level design tools for a Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), or Application Specific Integrated Circuit (ASIC). LeonardoSpectrum offers design capture, VHDL and Verilog entry, register-transfer level debugging for logic synthesis, constraint-based optimization, timing analysis, encapsulated place-and-route, and schematic viewing. In this tutorial, you will use LeonardoSpectrum to synthesize the structural design to a gate-level net list. 1. In order to invoke LeonardoSpectrum correctly, you have to load the module prog/mentor/fpgadv Use the following command to see loaded modules: % module list If the required module has not been loaded yet, load it with the following command: & module load prog/mentor/fpgadv 2. Invoke LeonardoSpectrum: % leonardo & It may take a while before you see the following window. Please be patient. Select LeonardoSpectrum Level 3 and click OK on the dialogue box:

Be patient, the main window of LeonardoSpectrum will be displayed after a while: 3. In the main window, click the menu Tools >> FlowTabs to enter the advanced setup mode: 18

4. Click the Technology tab and select the technology ASIC >> AMS >> c35_corelib. Then click Load Library button to load the specified technology library. Observe the transcripts in the upper-right text window. 5. Click the Input tab and set your desired Working Directory. Press the Open button to load the structural design source file array_acc_structural.vhd. Then press the Read button. See the transcripts to make sure that no errors occurred and the preoptimization succeeded. 19

6. Click the Elaborate tab at the bottom-left corner of the main window. Select the Top level designs as ARRAY_ACC_STRUCTURAL and the Architecture as STRUCTURAL. Then press the Elaborate button. 7. Click Optimize tab. Select the Target Technology as AMS c35_corelib, and select Run Type as Optimize. Click the Optimize button. 20

8. Click Report tab. Click Report Area tab at the bottom-left corner of the main window. Specify the Report Filename as synthesis_report.area and press the Report Area button to save the area report. 9. On the Report tab. Click Report Delay tab at the bottom-left corner of the main window. Specify the Report Filename as synthesis_report.delay and press the Report Delay button to save the delay report. 10. Click Output tab. Choose Format as Verilog (*.v). Specify the file name as array_acc_structural.v and press the Write button to save the netlist file. 11. Close LeonardoSpectrum and get back to the Unix terminal. 12. Inspect the area report. cat synthesis_report.area We can see how many instances of each primitive from the library c35_corelib is used, what are the approximated areas for them, what is the total count of the utilized primitives and the most important metric is Number of um2 which shows the overall area for the design. The area depends on the technology (given in the library) as well as the design. Knowing the breakdown of the area may help the designer in improving it. However, it should be mentioned that by the advancement of the technology and shrinkage of the feature sizes, the area metric is becoming less and less important while the power issues are becoming more and more important. Please put a copy of the area report in your final report. You may use a screen shot as well. On a Solaris workstation, an application called SnapShot can be used to capture screen shots. 21

13. Inspect the delay report. cat synthesis_report.delay Here, we focus on Clock Frequency Report. It might be reported for clock signal or its negate, e.g. CLK or NOT_CLK, depending on the design. LeonardoSpectrum finds and reports the critical paths Critical path #n. They are indexed by natural numbers (#n) and might be a number of them or only one. Identifying the critical path is critical to improve the design performance. Finding the critical path is not always feasible for a human designer especially that it may depend on the technology (given in the library) as well. Then the designer may look for ways to shorten this path. Please put a copy of the delay report in your final report. You may use a screen shot as well. On a Solaris workstation, an application called SnapShot can be used to capture screen shots. It is worth mentioning that the important metrics for a design include delay, area, power, reliability, and testability. Unfortunately, there are tradeoffs between them. For example there are well-known techniques to tradeoff area vs. other metrics. 22

Chapter 5 Tutorial of Test Pattern Generation In the previous chapters, you have learned how to synthesize a design down to the gate level. Sometimes designs have very low testability. In order to improve the testability, modifications to the original design are required, while the functionality of the design should remain the same. There are a few techniques to revise the design and improve the testability (some of them are automated). But it is not easy for a human designer to immediately and exactly see how testable a design is. Here the CAD tools will help the designer in order to evaluate the testability of a design. In order to test a manufactured chip, test patterns are applied to it. But what is a minimum set of test patterns to cover as much faults as possible? Here again CAD tools help to find a very good set of test patterns with a minimal size (in fact test application time is important) and a maximal coverage. In this chapter, you will learn to use FastScan to automatically generate test patterns and get the testability statistics. FastScan is part of TESSENT and therefore we need to load the TESSENT module. % module add prog/mentor/tessent More information about module commands: % module avail shows the available modules % module initadd modulefile Adds modulefile to the shell's initialization file % module add modulefile % module load modulefile Loads modulefile into the shell environment % module rm modulefile % module unload modulefile Removes modulefile from the shell environment % module display modulefile % module show modulefile Display information about modulefile % module list List loaded modules Please pay attention that by adding the module its path is usually added to the beginning of the environmental variable PATH. In order to make sure do echo $PATH At its beginning you should see /sw/mentor/tessent/bin otherwise add it as follows. Note that even if the module is loaded, you need to check for its path in PATH. % setenv PATH /sw/mentor/tessent/bin:$path In order to automatically generate test patterns, The ATPG library which contains scan flip-flops for the specified technology is required. In the lab we use a library for AMS c35 technology. You can obtain one copy of this ATPG library file from the /home/tdts01/hls_tutorial. Copy the file c35_corelib.atpg from there to the desirable directory which also contains your synthesized design (It is a file in verilog format that you generated and saved in synthesis chapter). In the following we assume that the desired directory is /home/u_name/tdts01/example. Change your working directory to: /home/u_name/tdts01/example/ 23

Therefore, % pwd should give: /home/u_name/tdts01/example And, % ls should show: array_acc_structural.v, and c35_corelib.atpg. Now we are ready to start the FastScan. 1. Invoke FastScan: % fastscan array_acc_structural.scan.v -lib c35_corelib.atpg 2. Read the messages; except Warning: 8 cases: Unused net in DFT library model, should not be other warnings or errors. 3. Type report primary inputs and pay attention to the CLK and RST in the list. These inputs are special inputs for clock and reset signals. 4. These special inputs are non-data signals that propagate to (almost) all memory elements in your design and therefore should be explicitly declared to the FastScan. These inputs are identified by the general name of clocks in the FastScan. Declare them as follows: add clocks 1 CLK add clocks 0 RST 5. In order to check if they are correctly added do the following: report clocks The response should be: /CLK off-state = 1 /RST off-state = 0 In case you have entered a wrong entry, use the following to remove it. delete clocks name_of_wrong_entry Usually there are two primary pins that you may want to define as circuit clocks, CLK (clock) and RST (reset). Here a primary clock pin means that you use the raising or falling edge of the clock signal coming from this primary input port to trigger an event. The off-state of a primary input clock should be defined as 0 if you use its raising edge, or 1 when using the falling edge. 6. Initial settings are done, change the mode to Automatic Test Pattern Generation (ATPG): set system mode atpg 7. Create the test patterns: create patterns FastScan ATPG statistics will be displayed after some delay. You may get the statistics later by typing: report STAT 24

Please make a screen shot for the above statistics result and put it in your final report. Do it for both of the original design and the design that you have modified for testability. Describe the differences shortly. On a Solaris workstation, an application called SnapShot can be used to capture screen shots. 8. Save the test patterns. save patterns array_acc_structural.patterns -ascii 9. Exit. exit 25

Chapter 6 Lab Assignments Students are supposed to do their own projects by following the same design and test flow as they did in the tutorial. Projects can be assignments provided on the course webpage or can be defined by students themselves. Two students should work together in a team on their project. In the lab, students are supposed to follow the steps bellow: preliminary hardware specification behavioral design simulation of behavioral design high-level synthesis of the design to the register-transfer level (RTL) simulation of structural design logic synthesis of the design to the gate level test pattern generation and testability statistics analyze the design from a testability point of view (testability improvement is required only for the final project) change the design in order to improve testability Repeat the design flow until you are satisfied with the results Project specifications should be discussed with the lab assistants. When agreed, email the specs to the lab assistant and do not alter the specs afterwards. Start it only when the specs are approved. The projects should be demonstrated in person by the last lab. The project specs, project demonstration, and final report are mandatory. Improving the testability is required. The important thing here is a convincing argument about the modification and describing how it helps to improve the testability. The amount of improvement per se is not crucial. Please report the area, delay, and testability of your original design and then report the area, delay, and testability for the finalized design which is modified in order to improve the testability. Interested students are encouraged to try to improve the delay. It is not advised to try to improve the area.

Quick Guide to the Minimal Requirements: 1. Experiment with the tools for the given example. 2. Finalize your project specifications with lab assistants. 3. Demonstrate the behavioral model. [Deadline] 4. Develop your structural design and pay attention to the design metrics. 5. Improve the testability of your design by making some modifications. 6. Observe the effects of the modification on design metrics. 7. Demonstrate your final design. [Deadline] 8. Hand in your final report. [Deadline] Project Specification 1. Decide the functionality of you design (what it will do). 2. Decide the interface. How inputs are read/given and how outputs are written/taken. The strong suggestion is a hand-shaking with Start and Busy signals for input and Valid signal for output. 3. Decide for how many samples you will demonstrate. 4. Decide how many inputs you accept for one run. 5. Decide the bit-width of your inputs and outputs. 6. Decide to design for performance or for area. Suggested Hand-Shaking and Functionality Check Protocol 1. Connect the clock. 2. Reset the circuit. (Start Up reset) 3. Give the inputs. 4. Pulse the Start signal to the circuit. 5. Circuit should activate its Busy signal. 6. When the processing is done, the outputs are given and the Valid signal is activated. Only activate Valid signal when the output is actually valid. 7. The Busy signal is now deactivated and the circuit is ready for the next run. Design for Performance or Area There are always tradeoffs between design metrics and in order to come up with a good design, the designer should have a clear mind about them from the very beginning. In this lab you are not required to iterate over the design in order to improve the performance (delay, speed) or the area. However you do, at least, one iteration to improve the testability. It should be shown and argued (especially in your final report) what design choices you have made in sake of performance or area. One very important choice which is not in your VHDL code is in the optimization section of the Leonardo. 27