Is t It Time You Got Faster, Quicker? AltiVec Techology At-a-Glace OVERVIEW Motorola s advaced AltiVec techology is desiged to eable host processors compatible with the PowerPC istructio-set architecture (ISA) to perform with sigificatly more geeral-purpose processig power. At the same time, this leadigedge techology is egieered to support high badwidth data processig ad algorithmic-itesive computatios, all i a sigle chip solutio. With its ease-of-use software eviromet, AltiVec techology is egieered to brig exceptioal power to applicatios such as telecom switches, IP telephoy gateways, speech processig systems, image ad video processig systems, virtual private etwork servers, highresolutio 3-D graphics ad more. AltiVec techology has prove itself to be a leader i eablig high performace: Motorola s MPC7455 was amed 2001 Embedded Processor of the Year by I-Stat MDR, ad accordig to the EEMBC, a cosortium of semicoductor, compiler ad RTOS vedors, the MPC7455 has the highest certified performace ratig of ay microprocessor i productio the cosortium has ever published. AltiVec techology offers a programmable solutio desiged to easily migrate via software upgrades to follow chagig stadards ad customer requiremets. The bottom lie? With AltiVec techology ad host processors compatible with the PowerPC ISA, your techology ivestmet is protected well ito the future. This at-a-glace guide to AltiVec techology is desiged to give you the iformatio you eed to make the right choices about processors ad performace. This guide icludes a roadmap, features ad beefits, bechmarks ad URLs to help you fid more iformatio.
THE SOLUTION FOR EMBEDDED COMPUTING CHALLENGES With its high performace ad ease-of-use software eviromet, AltiVec techology offers a sigle-chip solutio to may commo embedded computig challeges. AltiVec techology eables: High-badwidth data commuicatios Packet data processig Image ad video processig Access cocetrators/dslams - ADSL ad digital data cocetrators Speech recogitio Voice/soud processig Array umeric processig Basestatio processig Real-time cotiuous speech I/O - HMM, Viterbi acceleratio, eural algorithms 3-D graphics - Games, etertaimet - High-precisio CAD Virtual reality Motio video - MPEG2, MPEG4 - H.234 High-fidelity audio - 3-D audio, AC-3, MP3 Machie itelligece Istructio Stream AltiVec techology has prove itself to be a leader i eablig high performace. Dispatch IU FPU Vector Uit GPRs FPRs Vector Register File 32 bits 64 bits 128 bits Cache/Memory ALTIVEC EXECUTION OF MULTIPLY-ACCUMULATE ALTIVEC TECHNOLOGY S VECTOR EXECUTION UNIT va vb vc Prod Vector executio uit is cocurret with iteger ad floatig poit uits (FPUs) 32 separate, dedicated 128-bit vector registers - Large amespace for low register pressure/spillage - Separate files are accessible by executio uits i parallel - Deep register files allow for sophisticated software optimizatios No pealty for miglig iteger, FPU ad AltiVec techology operatios vd - Log vector legth eables more data-level parallelism
ALTIVEC TECHNOLOGY FEATURES AND BENEFITS ALTIVEC TECHNOLOGY BENEFITS Desiged to provide a sigle, high-performace RISC microprocessor with DSP-like computig power for cotroller ad sigal processig fuctios - Supplemets performace-leadig host processors compatible with the PowerPC ISA with a advaced, best-i-class executio uit - Vector processig egie desiged to provide for highly parallel operatios, which ca allow for the simultaeous executio of up to 16 operatios i a sigle clock cycle - Desiged to accelerate may traditioal computig ad embedded processig operatios with its wide data paths ad field operatios Desiged to provide product desigers ad customers with a iovative oe part/oe code itegrated approach egieered to coverge system cotrol fuctioality with specialized fuctioality typically residet o off-chip devices Offers a programmable solutio desiged to easily migrate via software upgrades to follow chagig stadards ad customer requiremets - Simplifies desig ad support programmable i flexible extesios to C laguage - Desiged to allow customers to leverage PowerPC compatibility ad legacy code, ad add AltiVec performace as they eed it ALTIVEC TECHNOLOGY FEATURES SIMD fuctioality for embedded applicatios with massive data processig eeds Key features: - 128-bit vector executio uit with 32-etry, 128-bit register file - Parallel processig with vector permute uit ad vector arithmetic logical uit - 162 additioal istructios - Advaced data types such as packed byte, halfword ad word itegers, ad packed IEEE sigle-precisio floats - Saturatio arithmetic Simplified architecture - Virtually o iterrupts other tha data storage iterrupt o loads ad stores - Allows hardware ualiged access support - Virtually o pealty for ruig AltiVec ad stadard PowerPC istructios simultaeously - Streamlied architecture to facilitate efficiet implemetatio Maitais PowerPC ISA s RISC register-toregister programmig model Supports parallel operatio o byte, halfword, word ad 128-bit operads - Itra ad iter-elemet arithmetic istructios - Itra ad iter-elemet coditioal istructios - Powerful permute, shift ad rotate istructios Vector iteger ad floatig-poit arithmetic - Data types 8-, 16- ad 32-bit siged ad usiged iteger data types 32-bit IEEE sigle-precisio floatig-poit data type 8-, 16- ad 32-bit Boolea data types (e.g., OxFFFF= 16-bit TRUE) - Modulo ad saturatio iteger arithmetic - 32-bit IEEE-default sigle-precisio floatig poit arithmetic IEEE-default exceptio hadlig IEEE-default roud-to-earest Fast o-ieee mode (e.g., deorms flushed to zero) Cotrol flow with highly flexible bit maipulatio egie - Compare creates field mask used by select fuctio - Compare RC bit eables settig Coditio Register Trivial accept/reject i 3-D graphics Exceptio detectio via software pollig Available library
ABOUT 128-BIT SIMD VECTOR ARCHITECTURE 128-BIT VECTOR ARCHITECTURE FEATURES 128-bit wide data paths betwee L1 cache, L2 cache, load/store uits ad registers - Wider data paths speed save ad restore operatios Offers SIMD processig support for the followig: - 16-way parallelism for 8-bit siged ad usiged bytes ad characters - 8-way parallelism for 16-bit siged ad usiged halfword - 4-way parallelism for 32-bit siged ad usiged itegers ad IEEE floatig poit umbers Four fully pipelied idepedet executio uits - Vector permute uit is a highly flexible byte maipulatio egie Vector simple fixed-poit, vector complex fixed-poit, ad vector floatig-poit executio egies - Dual AltiVec istructio issue Without the power of AltiVec techology, the code may have to call a routie six times to perform the same operatio o multiple pieces of data. With AltiVec techology, the routie may be ru oly oce, o all six sectios of data simultaeously. SAMPLE-BASED PROCESSING SISD (Sigle Istructio, Sigle Data) AC3 - Audio Decode SIMD (Sigle Istructio, Multiple Data) AC3 - Audio Decode do { decode (chael 1) decode (chael 2) decode (chael 3) decode (chael 4) decode (chael 5) decode (chael 6) } while (Amplifier is o; step time) do { decode (chael 1, chael 2, chael 3, chael 4, chael 5, chael 6) } while (Amplifier is o; step time) Approximately 6x performace improvemet ALTIVEC INSTRUCTION SET 162 istructios added to the PowerPC ISA 4 operad, o-destructive istructios - Up to three source operads ad a sigle destiatio operad - Supports advaced multiply-add/sum ad permute primitives Istructios fully pipelied with sigle-cycle throughput - Simple ops: 1 cycle latecy - Compoud ops: 3 4 cycle latecy - No restrictio o issue with scalar istructios Ehaced cache/memory iterface - Software hits for data re-use probability - Prefetch support (stride-n access) Simplified load/store architecture - Simple byte, halfword, word ad quadword loads ad stores - Virtually o ualiged accesses softwaremaaged via permute istructio
ALL ABOUT ALTIVEC TECHNOLOGY WHAT IS A VECTOR ARCHITECTURE, ANYWAY? Desiged to allow the simultaeous processig of may data items i parallel Has roots i supercomputig, which attempted to extract large amouts of parallelism from software Performs operatios o multiple data elemets by a sigle istructio, called Sigle Istructio, Multiple Data (SIMD) parallel processig AltiVec techology is a short SIMD vector architecture - Uses 128-bit wide registers to provide 4-, 8- or 16-way parallelism - Supports a wide variety of data types SIMD extesio to host processors compatible with the PowerPC ISA - Processes multiple data streams/blocks i a sigle cycle - Commo approach to accelerate processig of ext-geeratio data types (audio, video, packet data) MOTOROLA S HIGH-PERFORMANCE EMBEDDED MICROPROCESSOR PRODUCTS Features G4+ G4 Platform with AltiVec Rapid IO Higher Level of Itegratio G4+ MPC7451/55/57 Platform 7-Stage Pipelie, Pi-for-Pi Compatible, SMP ad AltiVec, 484/360 Pi, L3 Cache Iterface, 2+ GHz MPC7457/47 L Spec > 1 GHz MPX: 166 200 MHz, 512K L2 MPC745x/44x 0.18µ 0.18µ SOI 0.13µ SOI 0.13µ SOI MPC7455/45 L Spec 600 1000 MHz, MPX: 133 MHz, 256K L2 MPC7455/45 First Sample Date (left edge) MPC7451/41 L Spec 600 667 MHz, MPX: 133 MHz, 256K L2 MPC7451/41 Product Qualificatio (right edge) MPC7410 L Spec 400 500 MHz, MPX: 133 MHz Time MPC7410 Except for historical iformatio, all of the expectatios ad assumptios cotaied i the foregoig are forward-lookig statemets ivolvig risk ad ucertaities. Importat factors that could cause actual results to differ materially from such forward-lookig statemets iclude, but are ot limited to, the competitive eviromet for our products, chages of rates of all related services ad legislatio that may affect the idustry. For additioal iformatio regardig these ad other risks associated with Compay s busiess, refer to the Compay s reports with the SEC.
BENCHMARKING DATA EEMBC RESULTS: TELECOMMUNICATIONS AND NETWORKING WITH ALTIVEC TECHNOLOGY MPC7455 @ 1 GHz Telecommuicatios MPC7455 @ 1 GHz Usig AltiVec Techology MPC7455 @ 1 GHz 4x Faster Networkig EEMBC Telemark MPC7455 with AltiVec: 121.6 MPC7455 without AltiVec: 28.3 EEMBC Netmark MPC7455 with AltiVec: 98.4 MPC7455 without AltiVec: 29.4 MPC7455 @ 1 GHz Usig AltiVec Techology MPC7455 @ 1 GHz 3x Faster 0 20 40 60 80 100 120 The EEMBC Certificatio Laboratories, LLC (ECL) has certified these scores accordig to the rules established by the EEMBC Board of Directors ad ECL. These scores are repeatable ad the disclosure iformatio o the EEMBC Web site has all bee verified. www.eembc.org www.ebechmarks.com FOR MORE INFORMATION Fid more iformatio about AltiVec techology embedded i Motorola s G4 processors at www.motorola.com/altivec Libraries - May be liked via stadard third-party compilers - Cotai elemets that have bee show to be effective by EEMBC s etworkig ad telecom bechmark suites Applicatio otes - Software code may be icorporated ito customer s specific code, i.e., Fft, dct, Ivert, etc. Customer code - Motorola s software egieers are available to help customers take advatage of the power of AltiVec techology i their code. For more iformatio about Motorola s products: www.motorola.com/semicoductors For additioal tech questios: www.motorola.com/semicoductors/support MOTOROLA ad the Stylized M Logo are registered i the U.S. Patet ad Trademark Office. All other product or service ames are the property of their respective owers. Motorola, Ic. 2002 ALTIVECGLANCE/D REV 1