Design Rules and Min Timing

7 Design Rules and Min Timing Learning Objectives After completing this lab, you should be able to: Apply design rules and hold time constraints Fix design rule violations Fix hold time violations Lab Duration: 20 minutes Design Rules and Min Timing Lab 7-1 Synopsys 31833-000-S38

Design Specifications The table below is a summary of constraints from Lab 5 and Lab 6. The design rule and hold time constraints shown in the second table are additional constraints that will be applied during this lab. Clock Frequency Clock Skew Input Ports (worst case input delay) Output Ports (worst case output delay) Area Goal 250 Mhz (4 ns) 50% duty cycle 0.25 ns T clk-q = 1ns All output ports are registered Follow lab instruction Voltage and Temperature Variation 1.8V +/- 0.18V, 0 C to 125 C Default Register Driving input ports (except for Clk port) Wire Load Model Wire Load Mode Max Capacitance Allowed on an input ports: (except for Clk port) Number of blocks each output port must be able to drive: Assumed load on output ports cell "fdef1a1", pin Q Note: fdef1a1 contains two of the letter one character, and no L characters 5KGATES top 5 and2a1 cells, pin A 3 5 x 3 and2a1 cells, pin A Max Transition driving input ports: (except for Clk port) Input Ports (best case input delay) Output Ports (best case output delay) 0.25 ns T clk-q = 0.2 ns FF hold requirement = 0.5 ns External logic delay T n = 0.2 ns Lab 7-2 Design Rules and Min Timing

To Get You Started Use the drawing below to determine the input and output delays for hold time calculations. Input Delay Output Delay A T clk-q B C T N T hold Clk PRGRM_CNT_TOP Question 1. From the specifications above, complete the commands below by filling in the blanks: set ALL_INS_EX_CLK [remove_from_collection \ [all_inputs] [get_ports Clk]] set_max_transition set_input_delay min -clock my_clk $ALL_INS_EX_CLK set_output_delay min -clock my_clk [all_outputs] Question 2. If you do not constrain the ports accurately, what is likely to happen?... Answers are at the back of this lab. Design Rules and Min Timing Lab 7-3

Flow Diagram of Lab Complete scripts/lab7.tcl for: Max Transition Minimum input delay Minimum output delay Read mapped/ PC.db Apply the constraints scripts/lab7.tcl Save PRGRM_CNT_TOP.db Generate reports Fix design rule violations Generate constraints report Fix timing violations Quit Lab 7-4 Design Rules and Min Timing

Task 1. Complete lab7.tcl Script file 1. Complete the existing scripts/lab7.tcl file with a text editor. Task 2. Read Mapped PC.db 1. Start dc_shell-t and read the previously mapped design PC.db. 2. Apply scripts/lab7.tcl to the PRGRM_CNT_TOP design. Remember that PC.db was previously mapped and saved with applied constraints. Sourcing lab7.tcl will just add more constraints to the PRGRM_CNT_TOP design. 3. Save PRGRM_CNT_TOP.db for use in the next lab. write hier output mapped/prgrm_cnt_top.db Task 3. Generate Reports 1. Generate a constraints report for all violations using the: report_constraint command. PRGRM_CNT_TOP now violates both the hold time and the design rule max_transition, because of the design rule and hold time constraints you just added. 2. Generate a detailed hold time report using the report_timing command. report_timing delay min Notice how clock skew (0.25 ns) and output constraint (0.30 ns) contribute to data required time of 0.55 ns. In order to meet this hold time requirement, the shortest delay on output ports cannot be faster than 0.55 ns. A detailed discussion on timing reports will be covered during lecture. Design Rules and Min Timing Lab 7-5

Task 4. Fix Design Rule Violations DC can fix all kinds of violations in one run. Fixing design rules can sometimes fix hold time violations. Begin by fixing design rules first. 1. Execute the following command to fix just the design rules. compile scan inc only_design_rule All design rule violations should be fixed by the end of this compile. Fixing design rules, however, may cause other constraints to fail. This is expected since other constraints have lower priority by default. Task 5. Generate Reports 1. Generate a constraints report for all violations. The report should not have any design rule violations. Question 3. PRGRM_CNT_TOP now violates setup timing. Can you explain why?... Question 4. What is the next logical step?... Task 6. Fix Timing Violations 1. Execute compile in incremental mode to fix setup violations. compile scan inc map high Verify that PRGRM_CNT_TOP now has only hold time violations. 2. Enable DC to fix hold time; use the following commands: set_fix_hold [all_clocks] compile scan inc only_design_rule Verify that PRGRM_CNT_TOP has no violated constraints. 3. Quit Design Compiler. (Do not overwrite mapped/pc.db file.) Lab 7-6 Design Rules and Min Timing

Answers / Solutions Question 1. From the specifications above, complete the commands below by filling in the blanks: set ALL_INS_EX_CLK [remove_from_collection \ [all_inputs] [get_ports Clk]] set_max_transition 0.25 $ALL_INS_EX_CLK set_input_delay min 0.2 -clock my_clk $ALL_INS_EX_CLK set_output_delay min 0.3 -clock my_clk [all_outputs] Question 2. If you do not constrain the ports accurately, what is likely to happen? If the port environment is not modeled accurately, timing or electrical rule violations may occur when the block you are compiling is inserted, or stitched into the higher-level design. Question 3. PRGRM_CNT_TOP now violates setup timing. Can you explain why? When using the only_design_rule option, Design Compiler fixes design rule violations at the expense of setup timing violations. Question 4. What is the next logical step? Perform a regular incremental compile that will fix setup as well as preserve the design rule fixes performed earlier. Design Rules and Min Timing Lab 7-7