Today: Machine Programming I: Basics Machine Level Programming I: Basics 15 213/1 213: Introduction to Computer Systems 5 th Lecture, Jan 29, 2013 History of Intel processors and architectures C, assembly, machine code Assembly Basics: Registers, operands, move Intro to x6 6 Instructors: Seth Copen Goldstein, Anthony Rowe, Greg Kesden 1 2 Intel x6 Processors Totally dominate laptop/desktop/server market Evolutionary design Backwards compatible up until 06, introduced in 197 Added more features as time goes on Complex instruction set computer (CISC) Many different instructions with many different formats But, only small subset encountered with Linux programs Hard to match performance of Reduced Instruction Set Computers (RISC) But, Intel has done just that! In terms of speed. Less so for low power. Intel x6 Evolution: Milestones Name Date Transistors MHz 06 197 29K 5 10 First 16 bit Intel processor. Basis for IBM PC & DOS 1MB address space 36 195 275K 16 33 First 32 bit Intel processor, referred to as IA32 Added flat addressing, capable of running Unix Pentium F 200 5M 200 300 First 6 bit Intel processor, referred to as x6 6 Core 2 2006 291M 1060 3500 First multi core Intel processor Core i7 200 731M 1700 3900 Four cores (our shark machines) 3
Moore s Law Moore s Law Goodness Goodness Time Time 5 6 Moore s Law Moore s Law? Goodness Goodness H ahappy p B Day py B day B D a y Time Time 7
More on Moore s Law You can buy this for $20 today. More than 23,900,000x improvement in $-cc 3 In 193 dollars, the equivalent cost >$250,000.00 Fit in >2,500 boxes Intel x6 Processors, cont. Machine Evolution 36 195 0.3M Pentium 1993 3.1M Pentium/MMX 1997.5M PentiumPro 1995 6.5M Pentium III 1999.2M Pentium 2001 2M Core 2 Duo 2006 291M Core i7 200 731M Added Features Instructions to support multimedia operations Instructions to enable more efficient conditional operations Transition from 32 bits to 6 bits More cores 9 9 10 x6 Clones: Advanced Micro Devices (AMD) Historically AMD has followed just behind Intel A little bit slower, a lot cheaper Then Recruited top circuit designers from Digital Equipment Corp. and other downward trending companies Built Opteron: tough competitor to Pentium Developed x6 6, their own extension to 6 bits Intel s 6 Bit Intel Attempted Radical Shift from IA32 to IA6 Totally different architecture (Itanium) Executes IA32 code only as legacy Performance disappointing AMD Stepped in with Evolutionary Solution x6 6 (now called AMD6 ) Intel Felt Obligated to Focus on IA6 Hard to admit mistake or that AMD is better 200: Intel Announces EM6T extension to IA32 Extended Memory 6 bit Technology Almost identical to x6 6! All but low end x6 processors support x6 6 But, lots of code still runs in 32 bit mode 11
Our Coverage IA32 The traditional x6 shark> gcc m32 hello.c x6 6 The emerging standard shark> gcc hello.c shark> gcc m6 hello.c Today: Machine Programming I: Basics History of Intel processors and architectures C, assembly, machine code Assembly Basics: Registers, operands, move Intro to x6 6 Presentation Book presents IA32 in Sections 3.1 3. Covers x6 6 in 3.13 We will cover both simultaneously Some labs will be based on x6 6, others on IA32 13 1 Definitions Architecture: (also ISA: instruction set architecture) The parts of a processor design that one needs to understand to write assembly code. Examples: instruction set specification, registers. Microarchitecture: Implementation of the architecture. Examples: cache sizes and core frequency. Example ISAs (Intel): x6, IA 15 Assembly Programmer s View CPU PC Registers Condition Codes Programmer Visible State PC: Program counter of next instruction Called EIP (IA32) or RIP (x6 6) Register file Heavily used program data Condition codes Store status information about most recent arithmetic operation Used for conditional branching es Data Instructions Memory Code Data Stack Memory Byte addressable array Code and user data Stack to support procedures 16
Turning C into Object Code Compiling Into Assembly Code in files p1.c p2.c Compile with command: gcc O1 p1.c p2.c -o p Use basic optimizations (-O1) Put resulting binary in file p text C program (p1.c p2.c) Compiler (gcc -S) C Code int sum(int x, int y) int t = x+y; return t; } Generated IA32 Assembly sum: pushl, (), addl (), popl ret text Asm program (p1.s p2.s) Assembler (gcc or as) binary binary Object program (p1.o p2.o) Linker (gcc or ld) Executable program (p) Static libraries (.a) Obtain with command /usr/local/bin/gcc O1 -S code.c Produces file code.s 17 1 Assembly Characteristics: Data Tes Integer data of 1, 2, or bytes Data values es (unted pointers) Floating point data of,, or 10 bytes Assembly Characteristics: Operations Perform arithmetic function on register or memory data Transfer data between memory and register Load data from memory into register Store register data into memory No aggregate tes such as arrays or structures Just contiguously allocated bytes in memory Transfer control Unconditional jumps to/from procedures Conditional branches 19 20
Object Code Code for sum 0x0100 <sum>: 0x55 0x9 0xe5 0xb 0x5 0x0c 0x03 0x5 0x0 0x5d 0xc3 Total of 11 bytes Each instruction 1, 2, or 3 bytes Starts at address 0x0100 Assembler Translates.s into.o Binary encoding of each instruction Nearly complete image of executable code Missing linkages between code in different files Linker Resolves references between files Combines with static run time libraries E.g., code for malloc, printf Some libraries are dynamically linked Linking occurs when program begins execution 21 Machine Instruction Example int t = x+y; addl (), Similar to eression: x += y More precisely: int eax; int *ebp; eax += ebp[2] 0x03ca: 03 5 0 C Code Add two signed integers Assembly Add 2 byte integers Long words in GCC parlance Same instruction whether signed or unsigned Operands: x: Register y: Memory M[+] t: Register Return function value in Object Code 3 byte instruction Stored at address 0x03ca 22 Disassembling Object Code Disassembled 003c <sum>: 03c: 55 push 03c5: 9 e5 mov, 03c7: b 5 0c mov 0xc(), 03ca: 03 5 0 add 0x(), 03cd: 5d pop 03ce: c3 ret Disassembler objdump -d p Useful tool for examining object code Analyzes bit pattern of series of instructions Produces approximate rendition of assembly code Can be run on either a.out (complete executable) or.o file 23 Alternate Disassembly Object 0x0100: 0x55 0x9 0xe5 0xb 0x5 0x0c 0x03 0x5 0x0 0x5d 0xc3 Disassembled Dump of assembler code for function sum: 0x003c <sum+0>: push 0x003c5 <sum+1>: mov, 0x003c7 <sum+3>: mov 0xc(), 0x003ca <sum+6>: add 0x(), 0x003cd <sum+9>: pop 0x003ce <sum+10>: ret Within gdb Debugger gdb p disassemble sum Disassemble procedure x/11xb sum Examine the 11 bytes starting at sum 2
What Can be Disassembled? % objdump -d WINWORD.EXE WINWORD.EXE: file format pei-i36 No symbols in "WINWORD.EXE". Disassembly of section.text: Today: Machine Programming I: Basics History of Intel processors and architectures C, assembly, machine code Assembly Basics: Registers, operands, move Intro to x6 6 30001000 <.text>: 30001000: 55 push 30001001: b ec mov, 30001003: 6a ff push $0xffffffff 30001005: 6 90 10 00 30 push $0x30001090 3000100a: 6 91 dc c 30 push $0x30cdc91 Anything that can be interpreted as executable code Disassembler examines bytes and reconstructs assembly source 25 26 Integer Registers (IA32) %ax %ah %al Origin (mostly obsolete) accumulate Moving Data: IA32 Moving Data Source, Dest: general purpose %cx %dx %bx %si %di %sp %bp %ch %dh %bh %cl %dl %bl counter data base source index destination index stack pointer base pointer Operand Tes Immediate: Constant integer data Example: $0x00, $-533 Like C constant, but prefixed with $ Encoded with 1, 2, or bytes Register: One of integer registers Example:, But and reserved for special use Others have special uses for particular instructions Memory: consecutive bytes of memory at address given by register Simplest example: () 16 bit virtual registers (backwards compatibility) 27 Various other address modes 2
Operand Combinations Source Dest Src,Dest C Analog Reg Imm Mem Reg Reg Mem Mem Reg $0x, temp = 0x; $-17,() *p = -17;, temp2 = temp1;,() *p = temp; (), temp = *p; Cannot do memory memory transfer with a single instruction Simple Memory ing Modes Normal (R) Mem[Reg[R]] Register R specifies memory address Aha! Pointer dereferencing in C (), Displacement D(R) Mem[Reg[R]+D] Register R specifies start of memory region Constant displacement D specifies offset (), 29 30 Using Simple ing Modes Using Simple ing Modes void swap(int *, int *) int t0 = *; int t1 = *; * = t1; * = t0; swap: pushl, pushl Set Up (), (), } (), (), Body, (), () void swap(int *, int *) int t0 = *; int t1 = *; * = t1; * = t0; } swap: pushl, pushl (), (), (), (),, (), () Set Up Body popl popl ret Finish popl popl ret Finish 31 32
Understanding Swap void swap(int *, int *) int t0 = *; int t1 = *; * = t1; * = t0; } Register Value t0 t1 Stack (in memory) 0 Old - Old (), # edx = (), # ecx = (), # ebx = * (t0) (), # eax = * (t1), () # * = t1, () # * = t0 33 Understanding Swap 0-0x11 0x11 0x10 (), # edx = (), # ecx = (), # ebx = * (t0) (), # eax = * (t1), () # * = t1, () # * = t0 3 Understanding Swap 0-0x11 0x11 0x10 (), # edx = (), # ecx = (), # ebx = * (t0) (), # eax = * (t1), () # * = t1, () # * = t0 Understanding Swap 0-0x11 0x11 0x10 (), # edx = (), # ecx = (), # ebx = * (t0) (), # eax = * (t1), () # * = t1, () # * = t0 35 36
Understanding Swap 0-0x11 0x11 0x10 (), # edx = (), # ecx = (), # ebx = * (t0) (), # eax = * (t1), () # * = t1, () # * = t0 Understanding Swap 0-0x11 0x11 0x10 (), # edx = (), # ecx = (), # ebx = * (t0) (), # eax = * (t1), () # * = t1, () # * = t0 37 3 Understanding Swap 0-0x11 0x11 0x10 (), # edx = (), # ecx = (), # ebx = * (t0) (), # eax = * (t1), () # * = t1, () # * = t0 Understanding Swap 0-0x11 0x11 0x10 (), # edx = (), # ecx = (), # ebx = * (t0) (), # eax = * (t1), () # * = t1, () # * = t0 39 0
Complete Memory ing Modes Most General Form D(Rb,Ri,S) Mem[Reg[Rb]+S*Reg[Ri]+ D] D: Constant displacement 1, 2, or bytes Rb: Base register: Any of integer registers Ri: Index register: Any, except for Unlikely you d use,either S: Scale: 1, 2,, or (why these numbers?) Today: Machine Programming I: Basics History of Intel processors and architectures C, assembly, machine code Assembly Basics: Registers, operands, move Intro to x6 6 Special Cases (Rb,Ri) D(Rb,Ri) (Rb,Ri,S) Mem[Reg[Rb]+Reg[Ri]] Mem[Reg[Rb]+Reg[Ri]+D] Mem[Reg[Rb]+S*Reg[Ri]] 1 2 Data Representations: IA32 + x6 6 Sizes of C Objects (in Bytes) C Data Te Generic 32 bit Intel IA32 x6 6 unsigned int long int char 1 1 1 short 2 2 2 float double long double 10/ 10/16 char * Or any other pointer x6 6 Integer Registers %rax %rbx %rcx %rdx %rsi %rdi %rsp %rbp %r %r9 %r10 %r11 %r %r13 %r1 %r15 %rd %r9d %r10d %r11d %rd %r13d %r1d %r15d 3 Extend existing registers. Add new ones. Make /%rbp general purpose
Instructions Long word l ( Bytes) Quad word q ( Bytes) New instructions: movq addl addq sall salq etc. 32 bit instructions that generate 32 bit results Set higher order bits of destination register to 0 Example: addl 32 bit code for swap void swap(int *, int *) int t0 = *; int t1 = *; * = t1; * = t0; } swap: pushl, pushl popl popl ret (), (), (), (),, (), () Set Up Body Finish 5 6 6 bit code for swap void swap(int *, int *) int t0 = *; int t1 = *; * = t1; * = t0; } swap: ret (%rdi), (%rsi),, (%rdi), (%rsi) Set Up Body Finish 6 bit code for long int swap void swap(long *, long *) long t0 = *; long t1 = *; * = t1; * = t0; } swap_l: movq movq movq movq ret (%rdi), %rdx (%rsi), %rax %rax, (%rdi) %rdx, (%rsi) Set Up Body Finish Operands passed in registers (why useful?) First () in %rdi, second () in %rsi 6 bit pointers No stack operations required 6 bit data Data held in registers %rax and %rdx movq operation q stands for quad word 32 bit data Data held in registers and operation 7
Machine Programming I: Summary History of Intel processors and architectures Evolutionary design leads to many quirks and artifacts C, assembly, machine code Compiler must transform statements, eressions, procedures into low level instruction sequences Assembly Basics: Registers, operands, move The x6 move instructions cover wide range of data movement forms Intro to x6 6 A major departure from the style of code seen in IA32 9