SYLLABUS UNIT - I 8086/8088 ARCHITECTURE AND INSTRUCTION SET

1 SYLLABUS UNIT - I 8086/8088 ARCHITECTURE AND INSTRUCTION SET Intel 8086/8088 Architecture Segmented Memory, Minimum and Maximum Modes of Operation, Timing Diagram, Addressing Modes, Instruction Set, Assembler Directives, Macros, Procedures, Assembly Language Programming Using Data Transfer, Arithmetic, Logical, Branching and String Manipulation Instructions. UNIT - II PERIPHERAL INTERFACES 8086 Interrupt structure, I/O and Memory Interfacing concepts using 8086, IC Chip Peripherals- 8255 PPI, 8254 Programmable Timer, 8257 DMA Controller, 8254 USART. UNIT - III 8051 ARCHITECTURE AND INSTRUCTION SET 8051 Microcontroller, Internal Architecture and Pin Configuration, 8051 Addressing Modes, Instruction Set, Bit Addressable Features, I/O Port Structure, Assembly Language Programming using Data Transfer, Arithmetic, Logical and Branch Instructions. UNIT - IV TIMER AND UART 8051 Timers/Counters, Serial Data Communication and its Programming, 8051 Interrupts, Interrupt Vector Table, Interrupt Programming. UNIT - V EXTERNAL INTERFACES Real World Interfacing of 8051 with External Memory, Expansion of I/O Ports, LCD, ADC, DAC, Stepper Motor Interfacing.

2 Contents MICROPROCESSORS AND MICROCONTROLLERS FOR b.e. (o.u) IIi year Ii semester (ELECTRONICS AND COMMUNICATION ENGINEERING) CONTENTS Syllabus as per R16-17 Curriculum UNIT - I [8086/8088 ARCHITECTURE AND INSTRUCTION SET]... 1.1-1.142 Part-A Short Questions with Answers... 1.1-1.6 1.1 INTRODUCTION TO MICROPROCESSORS... 1.7 1.2 INTEL 8086/8088 ARCHITECTURE... 1.7 1.2.1 Features of 8086 Microprocessor... 1.7 1.2.2 Functional Diagram of 8086... 1.8 1.2.2.1 Bus Interface Unit... 1.9 1.2.2.2 Execution Unit... 1.10 1.2.3 Memory Organization of 8086... 1.10 1.2.3.1 Memory Segmentation... 1.11 1.2.3.2 Generation of Physical Address... 1.12 1.2.3.3 Advantages of Segmented Memory... 1.14 1.2.4 Register Organization of 8086... 1.15 1.2.4.1 General Purpose Registers... 1.16 1.2.4.2 Pointer and Index Registers egisters... 1.17 1.2.4.3 Segment Registers... 1.18 1.2.4.4 Flag Registers... 1.19

3 1.3 SEGMENTED MEMORY... 1.22 1.4 MINIMUM AND MAXIMUM MODES OF OPERATION... 1.22 1.4.1 Pin/Signal Description of 8086 in Minimum and Maximum Mode... 1.23 1.4.1.1 Common Function Signals... 1.24 1.4.1.2 Minimum Mode Signals... 1.26 1.4.1.3 Maximum Mode Signals... 1.27 1.4.2 8086 Control Signal Interfacing Under Minimum Mode System... 1.28 1.4.3 8086 Control Signal Interfacing Under Maximum Mode... 1.30 1.5 TIMING DIAGRAMS... 1.32 1.5.1 Timing Diagram for Minimum Mode... 1.33 1.5.1.1 Timing Diagram for Read Operation... 1.33 1.5.1.2 Timing Diagram for Write Operation... 1.35 1.5.2 Timing Diagram for Maximum Mode... 1.36 1.5.2.1 Timing Diagram for Read Operation... 1.36 1.5.2.2 Timing Diagram for Write Operation... 1.38 1.5.3 Wait Cycles... 1.39 1.6 ADDRESSING MODES... 1.40 1.6.1 Register and Immediate Addressing Modes... 1.41 1.6.1.1 Immediate Addressing... 1.41 1.6.1.2 Register Addressing... 1.41 1.6.2 Memory Addressing Modes... 1.42 1.6.2.1 Direction Addressing... 1.43 1.6.2.2 Indirection Addressing... 1.44 1.6.2.3 Based Addressing... 1.46 1.6.2.4 Indexed Addressing with Displacement... 1.47 1.6.2.5 Based Index Addressing... 1.48

4 Contents 1.6.3 String Addressing... 1.49 1.6.4 I/O Port Addressing... 1.50 1.6.4.1 Fixed Port Addressing... 1.50 1.6.4.2 Variable Port Addressing... 1.50 1.6.5 Relative Addressing... 1.51 1.6.6 Implied Addressing... 1.51 1.7 INSTRUCTION SET... 1.51 1.7.1 Data Transfer Instructions... 1.52 1.7.1.1 General Purpose Data Transfer Instructions... 1.53 1.7.1.2 Special Address Transfer Instructions... 1.57 1.7.1.3 Flag Transfer Instructions... 1.59 1.7.1.4 Input-output Instructions... 1.60 1.7.2 Arithmetic Instructions... 1.61 1.7.2.1 Addition Instructions... 1.61 1.7.2.2 Subtraction Instructions... 1.65 1.7.2.3 Multiplication Instructions... 1.68 1.7.2.4 Division Instructions... 1.70 1.7.3 Logical Instructions... 1.73 1.7.4 Shift Instructions... 1.77 1.7.5 Rotate Instructions... 1.81 1.7.5.1 Rotate Instructions Without Carry... 1.81 1.7.5.2 Rotate Instructions with Carry (RCL/RCR)... 1.84 1.7.6 Branch Instructions... 1.87 1.7.6.1 Unconditional Branch Instructions... 1.87 1.7.6.2 Conditional Branch Instructions... 1.89 1.7.7 Iteration Control Instructions... 1.90 1.7.7.1 Processor Control Instructions... 1.91 1.7.7.2 Flag Control Instructions... 1.91 1.7.7.3 External Synchronization Instructions... 1.92

5 1.7.8 Interrupt Instructions... 1.94 1.7.9 String Manipulation Instructions... 1.94 1.8 ASSEMBLER DIRECTIVES... 1.98 1.9 MACROS... 1.105 1.9.1 Defining and Calling a Macro Without Parameters arameters... 1.106 1.9.2 Passing Parameters to Macros... 1.107 1.10 PROCEDURES... 1.108 1.10.1 Procedure Definition... 1.109 1.10.2 Procedure CALL and RETURN... 1.110 1.10.3 Parameter Passing... 1.111 1.10.3.1 Parameter Passing Using Registers... 1.111 1.10.3.2 Parameters Passing Using Memory Locations... 1.113 1.10.3.3 Parameter Passing with Pointers Passed in Registers... 1.115 1.10.3.4 Parameter Passing Using Stack... 1.116 1.10.4 Reentrant Procedure... 1.117 1.10.5 Comparison of Macros and Procedure (Subroutine)... 1.118 1.11 ASSEMBLY LANGUAGE GE PROGRAMMING USING DATA A TRANSFER, ARITHMETIC, LOGICAL, BRANCHING AND STRING MANIPULATION INSTRUCTIONS... 1.119 Part-B Important Essay Questions with References...1.141-1.142 UNIT - II [PERIPHERAL INTERFACES]... 2.1-2.116 Part-A Short Questions with Answers... 2.1-2.4 2.1 INTRODUCTION... 2.5 2.2 8086 INTERRUPT STRUCTURE... 2.5 2.2.1 Introduction to Interrupts... 2.5 2.2.1.1 Purpose of Interrupts... 2.6 2.2.1.2 Classification of Interrupts... 2.7

6 Contents 2.2.2 Interrupt Structure of 8086... 2.7 2.2.2.1 Predefined (or) Dedicated Interrupts... 2.8 2.2.2.2 Divide by Zero Interrupt (Type ype-0 Interrupt)... 2.9 2.2.2.3 Single-step Interrupt (Type ype-1 Interrupt)... 2.9 2.2.2.4 Non-maskable Interrupt (Type ype-2 Interrupt)... 2.9 2.2.2.5 Break-point Interrupt (Type ype-3 Interrupt)... 2.10 2.2.2.6 Overflow Interrupt (Type ype-4 Interrupt)... 2.10 2.2.3 Software Interrupts... 2.11 2.2.4 Hardware Interrupts... 2.11 2.2.5 Priorities of Interrupts... 2.12 2.2.6 Vector Interrupt Table... 2.12 2.2.7 Interrupt Service Routine... 2.14 2.3 MEMORY INTERFACING CONCEPTS USING 8086... 2.16 2.3.1 Memory Chip Organization... 2.16 2.3.2 Address Decoding Circuitry... 2.17 2.3.2.1 Address Decoding Using Basic Logic Gates... 2.18 2.3.2.2 Address Decoding Using 74LS138 Decoder... 2.18 2.3.3 Address Decoding Techniques... 2.20 2.3.3.1 Absolute (or) Full Address Decoding... 2.20 2.3.3.2 Partial (or) Linear Decoding... 2.21 2.3.4 Static RAM and EPROM Interfacing to 8086... 2.22 2.3.5 Memory Interfacing Using IC Chips... 2.28 2.3.5.1 Different Pins Present in Memory IC... 2.28 2.3.5.2 Components Used For Generating CS... 2.29

7 2.4 I/O INTERFACING CONCEPTS USING 8086... 2.30 2.4.1 Input/Output Ports... 2.30 2.4.2 I/O Interfacing Techniques in 8086... 2.31 2.4.2.1 I/O Mapped (or) Isolated I/O Interfacing... 2.31 2.4.2.2 Memory Mapped I/O Interfacing... 2.32 2.4.2.3 Comparison of I/O Mapped and Memory Mapped I/O... 2.33 2.4.3 7 Segment Display Unit Interface... 2.34 2.5 IC CHIP PERIPHERALS - 8255 PPI... 2.36 2.5.1 Features of 8255A... 2.36 2.5.2 Internal Block Diagram of 8255A... 2.37 2.5.3 Pin Configuration of 8255A... 2.39 2.5.4 Modes of Operation of 8255A... 2.41 2.5.4.1 Bit Set/Reset (BSR) Mode... 2.41 2.5.4.2 Parallel Input/Output Mode... 2.42 2.5.5 Interfacing of 8255 With 8086 Microprocessor... 2.51 2.5.6 Simple Program on Interfacing of Intel 8255 PPI Chip... 2.52 2.6 8254 PROGRAMMABLE TIMER/8253... 2.60 2.6.1 Signal Description of 8253... 2.60 2.6.2 Architecture of 8253... 2.62 2.6.3 Reading While Counting... 2.64 2.6.4 Modes of Operation of 8253... 2.65 2.6.4.1 Mode 0 Interrupt on Terminal Count... 2.65 2.6.4.2 Mode 1/Programmable One Shot... 2.68 2.6.4.3 Mode 2/Rate Generator... 2.70 2.6.4.4 Mode 3/Square Wave Generator... 2.72 2.6.4.5 Mode 4/Software Triggered Strobe... 2.73 2.6.4.6 Mode 5/Hardware Triggered Strobe... 2.75 2.6.5 Interfacing of 8253 With 8086 Microprocessor... 2.77

8 Contents 2.7 8257 DMA CONTROLLER... 2.81 2.7.1 Data Transfer Schemes... 2.81 2.7.1.1 Programmed Data Transfer Schemes... 2.82 2.7.1.2 DMA Data Transfer Method... 2.84 2.7.2 DMA Controller : INTEL 8257... 2.85 2.7.2.1 Features of 8257... 2.85 2.7.2.2 Internal Architecture of 8257... 2.86 2.7.2.3 Register Organization of 8257... 2.88 2.7.2.4 Pin Diagram of 8257... 2.91 2.7.2.5 DMA Transfer and Operations... 2.93 2.7.2.6 Priorities of the DMA Requests... 2.94 2.7.3 Interfacing 8086 with 8257... 2.95 2.8 8251 USART... 2.97 2.8.1 Introduction to Serial Communication... 2.97 2.8.1.1 Modes of Serial Communication... 2.97 2.8.2 Serial and Parallel Data Transmission Formats ormats... 2.98 2.8.2.1 Serial Data Transmission Format... 2.98 2.8.2.2 Parallel Data Transmission Format... 2.100 2.8.2.3 Comparison of Serial and Parallel Data Transfer.. 2.101 2.8.3 Features of 8251... 2.101 2.8.4 Pin Diagram of 8251... 2.102 2.8.5 Internal Architecture of 8251... 2.105 2.8.5.1 Read/Write Control Logic... 2.105 2.8.5.2 Data Bus Buffer... 2.106 2.8.5.3 Modem Control... 2.107 2.8.5.4 Transmitter Section... 2.107 2.8.5.5 Receiver Section... 2.108

9 2.8.6 Programming of 8251- USART... 2.109 2.8.6.1 Mode Word... 2.109 2.8.6.2 Command Word... 2.111 2.8.6.3 Status Word... 2.112 2.8.7 USART Interfacing... 2.113 Part-B Important Essay Questions with References... 2.115-2.116 UNIT - III [8051 ARCHITECTURE AND INSTRUCTION SET]... 3.1-3.76 Part-A Short Questions with Answers... 3.1-3.5 3.1 INTRODUCTION TO MICROCONTROLLER... 3.6 3.1.1 Microprocessors Vs Microcontrollers... 3.6 3.1.2 Advantages of Microcontrollers... 3.7 3.2 8051 MICROCONTROLLER... 3.7 3.2.1 Classification... 3.7 3.2.2 Features of 8051... 3.8 3.2.3 Internal Architecture of 8051... 3.9 3.2.4 Pin Configuration of 8051... 3.10 3.2.5 Programming Model of 8051... 3.12 3.2.6 The 8051 Oscillator and Clock... 3.13 3.2.6.1 CPU Timing... 3.14 3.2.7 Central Processing Unit (CPU)... 3.15 3.2.8 A and B Registers... 3.15 3.2.9 Program Status Word (PSW) Register... 3.15 3.2.10 Data Pointer (DPTR)... 3.17 3.2.11 Stack Pointer ointer... 3.17 3.2.12 Program Counter... 3.18 3.2.13 Scratch Pad ad Registers (R0 to R7)... 3.19 3.2.14 Special Function Registers (SFR)... 3.19 3.2.15 Internal Memory... 3.21

10 Contents 3.3 8051 ADDRESSING MODES... 3.21 3.3.1 Immediate Addressing... 3.22 3.3.2 Direct Addressing... 3.22 3.3.3 Register Addressing... 3.23 3.3.4 Register Indirect Addressing... 3.23 3.3.5 Base Register Plus Index Register Indirect Addressing... 3.24 3.3.6 Summary of Addressing Modes... 3.25 3.4 INSTRUCTION SET... 3.26 3.4.1 Data Transfer Instructions... 3.26 3.4.1.1 External Memory Data Transfer Instructions... 3.29 3.4.1.2 Code Memory Data Transfer Instructions... 3.30 3.4.1.3 PUSH and POP Instructions... 3.31 3.4.1.4 Data Exchange Instructions... 3.32 3.4.1.5 Simple Programs Based on Data Transfer Instructions... 3.34 3.4.2 Logical Instructions... 3.35 3.4.2.1 ANL Instruction... 3.35 3.4.2.2 ORL Instruction... 3.37 3.4.2.3 XRL Instruction... 3.38 3.4.2.4 CLEAR and COMPLEMENT Instructions... 3.40 3.4.2.5 Rotate Instructions... 3.41 3.4.2.6 SWAP Instruction... 3.43 3.4.2.7 Boolean Variable Manipulation Instructions... 3.44 3.4.3 Arithmetic Instructions... 3.46 3.4.3.1 Flags Affected by Instructions... 3.47 3.4.3.2 Increment Operation... 3.49 3.4.3.3 Decrement Operation... 3.50

11 3.4.3.4 Addition... 3.50 3.4.3.5 Subtraction... 3.52 3.4.3.6 Multiplication... 3.55 3.4.3.7 Division... 3.55 3.4.3.8 Decimal Arithmetic... 3.56 3.4.4 Branching Group... 3.57 3.4.4.1 Address Range... 3.57 3.4.4.2 JUMP Instructions... 3.59 3.4.4.3 Calls and Subroutines... 3.63 3.4.4.4 Call Instructions... 3.65 3.4.4.5 Return Instructions... 3.65 3.5 I/O PORT STRUCTURES... 3.66 3.5.1 Port ort-0 Configuration... 3.67 3.5.2 Port ort-1 Configuration... 3.68 3.5.3 Port ort-2 Configuration... 3.69 3.5.4 Port ort-3 Configuration... 3.70 3.6 ASSEMBLY LANGUAGE GE PROGRAMMING USING DATA A TRANSFER, ARITHMETIC, LOGICAL AND BRANCH INSTRUCTIONS... 3.71 3.6.1 Lines of Code... 3.71 3.6.2 8051 Instruction Syntax... 3.71 3.6.2.1 Label... 3.71 3.6.2.2 Instructions... 3.72 3.6.2.3 Comments... 3.72 3.6.3 Simple Programs... 3.73 Part-B Important Essay Questions with References... 3.76

12 Contents UNIT - IV [TIMER AND UART]... 4.1-4.28 Part-A Short Questions with Answers... 4.1-4.3 4.1 8051 TIMERS AND COUNTERS... 4.4 4.1.1 Timer/Counter Control Logic... 4.4 4.1.2 Timer Mode (TMOD) Register... 4.5 4.1.3 Timer Control (TCON) Register... 4.7 4.1.4 Timer Modes of Operation... 4.8 4.1.4.1 Timer / Counter Mode 0... 4.8 4.1.4.2 Timer Mode 1... 4.8 4.1.4.3 Timer Mode 2... 4.9 4.1.4.4 Timer Mode 3... 4.10 4.1.5 Counter Modes of Operation... 4.10 4.2 SERIAL DATA A COMMUNICATION AND ITS PROGRAMMING... 4.11 4.2.1 Serial Port of 8051... 4.11 4.2.2 Serial Buffer (SBUF) Register... 4.11 4.2.3 Serial Port Control (SCON) Register... 4.11 4.2.4 Power Mode Control (PCON) Register... 4.13 4.2.5 Operation of Serial Data Transfer... 4.13 4.2.6 Modes of Serial Port... 4.14 4.2.6.1 Mode 0 : Shift Register Mode... 4.14 4.2.6.2 Mode 1 : Standard 8 Bit UART Mode... 4.15 4.2.6.3 Mode 2 : Multiprocessor Mode... 4.16 4.2.6.4 Mode 3 : Multiprocessor Mode... 4.18 4.3 8051 INTERRUPTS... 4.18 4.3.1 Interrupt Types of 8051... 4.18 4.3.2 Interrupt Enable Register... 4.20 4.3.3 Interrupt Priority Register... 4.21 4.4 INTERRUPT VECTOR OR TABLE ABLE... 4.23 4.5 INTERRUPT PROGRAMMING... 4.23 Part-B Important Essay Questions with References... 4.28

13 UNIT - V [EXTERNAL INTERFACES]... 5.1-5.28 Part-A Short Questions with Answers... 5.1-5.3 5.1 REAL WORLD INTERFACING OF 8051 WITH EXTERNAL MEMORY... 5.4 5.1.1 Expanding the Program Memory... 5.4 5.1.2 Expanding the Data Memory... 5.5 5.2 EXPANSION OF I/O PORTS TS... 5.6 5.3 LCD (LIQUID CRYST YSTAL DISPLAY)... 5.7 5.3.1 Interfacing LCD Displays... 5.9 5.4 ACD (ANALOG TO DIGITAL CONVERTER)... 5.14 5.5 DAC (DIGITAL TO ANALOG CONVERTER)... 5.17 5.6 STEPPER MOTOR OR INTERFACING... 5.20 Part-B Important Essay Questions with References... 5.28