Section 14. Timer1 HIGHLIGHTS. Timer1. This section of the manual contains the following major topics:

Section 14. Timer1 HIGHLIGHTS This section of the manual contains the following major topics: 14.1 Introduction... 14-2 14.2 Control Register... 14-4 14.3 Timer1 Operation in Timer Mode... 14-5 14.4 Timer1 Operation in Synchronized Counter Mode... 14-5 14.5 Timer1 Operation in Asynchronous Counter Mode... 14-6 14.6 Reading and Writing of Timer1... 14-7 14.7 Timer1 Oscillator... 14-10 14.8 Typical Application... 14-11 14.9 Sleep Operation... 14-12 14.10 Resetting Timer1 Using a CCP Trigger Output... 14-12 14.11 Resetting Timer1 Register Pair (TMR1H:TMR1L)... 14-13 14.12 Timer1 Prescaler... 14-13 14.13 Initialization... 14-14 14.14 Design Tips... 14-16 14.15 Related Application Notes... 14-17 14.16 Revision History... 14-18 14 Timer1 2000 Microchip Technology Inc. DS39514A-page 14-1

PIC18C Reference Manual 14.1 Introduction The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) that are readable and writable. The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. If enabled, the Timer1 Interrupt is generated on overflow that is latched in the TMR1IF interrupt flag bit. This interrupt can be enabled/disabled by setting/clearing the TMR1IE interrupt enable bit. Timer1 can operate in one of three modes: As a synchronous timer As a synchronous counter As an asynchronous counter The operating mode is determined by clock select bit, TMR1CS (T1CON register), and the synchronization bit, T1SYNC (Figure 14-1). In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock input pin T1OSI. Timer1 can be turned on and off using thetmr1on control bit (T1CON register). Timer1 also has an internal reset input, which can be generated by a CCP module. Timer1 has the capability to operate off an external crystal. When the Timer1 oscillator is enabled (T1OSCEN is set), the T1OSI and T1OSO pins become inputs, so their corresponding TRIS values are ignored. Figure 14-1: Timer1 Block Diagram Set TMR1IF flag bit on Overflow TMR1 CLR TMR1H TMR1L T1OSO/T1CKI T1OSI T1OSC T1OSCEN Enable Oscillator (1) Fosc/4 Internal Clock CCP Special Event Trigger TMR1ON on/off 1 0 TMR1CS 0 1 T1SYNC Prescaler 1, 2, 4, 8 2 T1CKPS1:T1CKPS0 Synchronized Clock Input Synchronize det SLEEP input Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS39514A-page 14-2 2000 Microchip Technology Inc.

Section 14. Timer1 Figure 14-2:Timer1 Block Diagram 16-Bit Read/Write Mode Data Bus<7:0> 8 Write TMR1L Read TMR1L TMR1H 8 8 TMR1IF Overflow Interrupt flag bit T13CKI/ T1OSO T1OSI 8 TMR1 Timer 1 TMR1L High Byte T1OSCEN Enable Oscillator (1) Fosc/4 Internal Clock TMR1ON on/off T1SYNC 1 Prescaler 1, 2, 4, 8 0 2 TMR1CS T1CKPS1:T1CKPS0 0 1 Synchronized Clock Input Synchronize det SLEEP input Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. 14 Timer1 2000 Microchip Technology Inc. DS39514A-page 14-3

PIC18C Reference Manual 14.2 Control Register Register 14-1 shows the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 oscillator enable bit (T1OSCEN). Register 14-1: T1CON: Timer1 Control Register R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7 bit 6 bit 5:4 bit 3 bit 2 bit 1 bit 0 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register Read/Write of Timer1 in one 16-bit operation 0 = Enables register Read/Write of Timer1 in two 8-bit operations Unimplemented: Read as '0' T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 Oscillator is enabled 0 = Timer1 Oscillator is shut off. The oscillator inverter and feedback resistor are turned off to eliminate power drain. T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1Onbit 1 = Enables Timer1 0 =StopsTimer1 Legend R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 - n = Value at POR reset 1 = bit is set 0 = bit is cleared x = bit is unknown DS39514A-page 14-4 2000 Microchip Technology Inc.

Section 14. Timer1 14.3 Timer1 Operation in Timer Mode Timer mode is selected by clearing the TMR1CS (T1CON register) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit, T1SYNC (T1CON register), has no effect since the internal clock is always synchronized. 14.4 Timer1 Operation in Synchronized Counter Mode Counter mode is selected by setting the TMR1CS bit. In this mode, the timer increments on every rising edge of clock input on the T1OSI pin when the Timer1 oscillator enable bit (T1OSCEN) is set, or the T1OSO/T13CKI pin when the T1OSCEN bit is cleared. If the T1SYNC bit is cleared, then the external clock input is synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The prescaler operates asynchronously. The timer increments at the Q4:Q1 edge. In this configuration, during SLEEP mode, Timer1 will not increment even if the external clock is present, since the synchronization circuit is shut off. The prescaler however will continue to increment. 14.4.1 External Clock Input Timing for Synchronized Counter Mode When an external clock input is used for Timer1 in synchronized counter mode, it must meet certain requirements. The external clock requirement is due to internal phase clock (TSCLK) synchronization. Also, there is a delay in the actual incrementing of TMR1 after synchronization. When the prescaler is 1:1, the external clock input is the same as the prescaler output. The synchronization of T1CKI with the internal phase clocks is accomplished by sampling the prescaler output on alternating TscLK clocks of the internal phase clocks. Therefore, it is necessary for the T1CKI pin to be high for at least 2TscLK (and a small RC delay) and low for at least 2TscLK (and a small RC delay). Refer to parameters 45, 46, and 47 in the Electrical Specifications section. When a prescaler other than 1:1 is used, the external clock input is divided by the asynchronous prescaler so that the prescaler output is symmetrical. In order for the external clock to meet the sampling requirement, the prescaler counter must be taken into account. Therefore, it is necessary for the T1CKI pin to have a period of at least 4TscLK (and a small RC delay) divided by the prescaler value. Another requirement on the T1CKI pin high and low time is that they do not violate the minimum pulse width requirements). Refer to parameters 40, 42, 45, 46, and47 in the Electrical Specifications section. 14 Timer1 2000 Microchip Technology Inc. DS39514A-page 14-5

PIC18C Reference Manual 14.5 Timer1 Operation in Asynchronous Counter Mode If T1SYNC (T1CON register) is set, the external clock input is not synchronized. The timer continues to increment asynchronously to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt on overflow that will wake-up the processor. However, special precautions in software are needed to read/write the timer (Subsection 14.6.4 Reading and Writing Timer1 in Asynchronous Counter Mode with RD16 = 0 ). Since the counter can operate in sleep, Timer1 can be used to implement a true real-time clock. The timer increments at the Q4:Q1 and Q2:Q3 edges. In asynchronous counter mode, Timer1 cannot be used as a time-base for capture or compare operations. 14.5.1 External Clock Input Timing with Unsynchronized Clock If the T1SYNC control bit is set, the timer will increment completely asynchronously. The input clock must meet certain minimum high time and low time requirements. Refer to the Device Data Sheet Electrical Specifications section, timing parameters 45, 46, and 47. DS39514A-page 14-6 2000 Microchip Technology Inc.

Section 14. Timer1 14.6 Reading and Writing of Timer1 Timer1 has modes that allow the 16-bit timer register to be read/written as two 8-bit registers or one 16-bit register. The mode depends on the state of the RD16 bit. The following subsections discuss this operation. 14.6.1 Timer1 and 16-bit Read/Write Modes 14.6.2 16-bit Mode Timer Write 14.6.3 16-bit Read-Modify-Write Timer1 can be configured for 16-bit reads and writes. When the RD16 control bit (T1CON register) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 high byte buffer. This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte followed by a read of the low byte is valid due to a rollover between reads. AwritetothehighbyteofTimer1mustalsotakeplacethroughtheTMR1Hbufferregister.Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once (See Figure 14-3). The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 high byte buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L. Read-modify-write instructions like BSF or BCF will read the contents of a register, make the appropriate changes, and place the result back into the register. In the case of Timer1 when configured in 16-bit mode, the read portion of a read-modify-write instruction of TMR1L will not update the contents of the TMR1H buffer. The TMR1H buffer will remain unchanged. When the write of TMR1L portion of the instruction takes place, the contents of TMR1H will be placed into thehighbyteoftimer1. Figure 14-3:Timer1 Block Diagram When Configured in 16-bit Read/Write Mode Data Bus<7:0> Write TMR1L Read TMR1L TMR1IF Overflow Interrupt flag bit T13CKI/ T1OSO 8 8 TMR1H 8 TMR1 Timer 1 high byte TMR1L T1OSC 8 T1OSCEN Enable Oscillator (1) TTIP FOSC/4 Internal Clock TMR1ON on/off T1SYNC 1 Prescaler 1, 2, 4, 8 0 2 TMR1CS T1CKPS1:T1CKPS0 0 1 Synchronized Clock Input Synchronize det SLEEP input 14 Timer1 Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. 2000 Microchip Technology Inc. DS39514A-page 14-7

PIC18C Reference Manual 14.6.4 Reading and Writing Timer1 in Asynchronous Counter Mode with RD16 = 0 Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers while the register is incrementing. This may produce an unpredictable value in the timer register. Reading the 16-bit value requires some care, since two separate reads are required to read the entire 16-bits. Example 14-1 shows why this may not be a straight forward read of the 16-bit register. Example 14-1: Reading 16-bit Register Issues TMR1 Sequence 1 Sequence 2 Action TMPH:TMPL Action TMPH:TMPL 04FFh READ TMR1L xxxxh READ TMR1H xxxxh 0500h StoreinTMPL xxffh StoreinTMPH 04xxh 0501h READ TMR1H xxffh READ TMR1L 04xxh 0502h StoreinTMPH 05FFh StoreinTMPL 0401h DS39514A-page 14-8 2000 Microchip Technology Inc.

Section 14. Timer1 Example 14-2 shows a routine to read the 16-bit timer value without experiencing the issues shown in Example 14-1. This is useful if the timer cannot be stopped. Example 14-2: Reading a 16-bit Free-Running Timer All interrupts are disabled MOVF TMR1H, W Read high byte MOVWF TMPH MOVF TMR1L, W Read low byte MOVWF TMPL MOVF TMR1H, W Read high byte SUBWF TMPH, W Sub 1st read with 2nd read BTFSC STATUS,Z Is result = 0 GOTO CONTINUE Good 16-bit read TMR1L may have rolled over between the read of the high and low bytes. Reading the high and low bytes now will read a good value. MOVF TMR1H, W Read high byte MOVWF TMPH MOVF TMR1L, W Read low byte MOVWF TMPL Re-enable the Interrupt (if required) CONTINUE Continue with your code Writing a 16-bit value to the 16-bit TMR1 register is straightforward. First the TMR1L register is cleared to ensure that there are many Timer1 clock/oscillator cycles before there is a rollover into the TMR1H register. The TMR1H register is then loaded, and finally the TMR1L register is loaded. Example 14-3 shows a routine that does a 16-bit write to a Free Running Timer. Example 14-3: Writing a 16-bit Free Running Timer All interrupts are disabled CLRF TMR1L Clear Low byte, Ensures no rollover into TMR1H MOVLW HI_BYTE Value to load into TMR1H MOVWF TMR1H, F Write High byte MOVLW LO_BYTE Value to load into TMR1L MOVWF TMR1H, F Write Low byte Re-enable the Interrupt (if required) CONTINUE Continue with your code 14 Timer1 2000 Microchip Technology Inc. DS39514A-page 14-9

PIC18C Reference Manual 14.7 Timer1 Oscillator An alternate crystal oscillator circuit is built into the device. The output of this oscillator can be selected as the input into Timer1. The Timer1 oscillator is primarily intended to operate as a timebase for the timer modules therefore, the oscillator is primarily intended for a 32 khz crystal, which is an ideal frequency for real-time keeping. In real-time applications, the timer needs to increment during SLEEP, so SLEEP does not disable the Timer1 oscillator. For many applications, power consumption is also an issue, so the oscillator is designed to minimize power consumption. The Timer1 oscillator is enabled by setting the T1OSCEN control bit (T1CON register). After the Timer1 oscillator is enabled, the user must provide a software time delay to ensure proper oscillator start-up. Table 14-1 shows the capacitor selection for the Timer1 oscillator. Note: The Timer1 oscillator allows the counter to operate (increment) when the device is in sleep mode. This allows Timer1 to be used as a real-time clock. Table 14-1: Capacitor Selection for the Timer1 Oscillator Osc Type Freq C1 C2 LP 32 khz 33 pf 33 pf 100 khz 15 pf 15 pf 200 khz 15 pf 15 pf Crystals Tested: 32.768 khz Epson C-001R32.768K-A ± 20 PPM 100 khz Epson C-2 100.00 KC-P ± 20 PPM 200 khz STD XTL 200.000 khz ± 20 PPM Note 1: Higher capacitance increases the stability of oscillator but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. DS39514A-page 14-10 2000 Microchip Technology Inc.

Section 14. Timer1 14.8 Typical Application In Figure 14-4 an example application is given, where Timer1 is driven from an external 32 khz oscillator. The external 32 khz oscillator is typically used in applications where real-time needs to be kept, but it is also desirable to have the lowest possible power consumption. The Timer1 oscillator allows the device to be placed in sleep while the timer continues to increment. When Timer1 overflows, the interrupt wakes up the device so that the appropriate registers can be updated. Figure 14-4: Timer1 Application Power-Down Detect OSC1 8 VDD 4 Current Sink Backup Battery TMR1 4 TT1P 32 khz T1OSI T1OSO VSS 4 4x4 Keypad In this example, a 32 khz crystal is used as the time base for the Real Time Clock. If the clock needs to be updated at 1 second intervals, then the Timer1 must be loaded with a value to allow the Timer1 to overflow at the desired rate. In the case of a 1 second Timer1 overflow, the TMR1H register should be loaded with a value of 80k after each overflow. Note: The TMR1L register should never be modified, since an external clock is asychronous to the system clock. Writes to the TRM1L register may corrupt the real time counter value causing inaccuracies. 14 Timer1 2000 Microchip Technology Inc. DS39514A-page 14-11

PIC18C Reference Manual 14.9 Sleep Operation When Timer1 is configured for asynchronous operation, the TMR1 registers will continue to increment for each timer clock (or prescale multiple of clocks). When the TMR1 register overflows, the TMR1IF bit will get set. If enabled, this will generate an interrupt that will wake the processor from sleep mode. The Timer1 oscillator will add a delta current, due to the operation of this circuitry. That is, the power-down current will no longer only be the leakage current of the device, but also the active current of the Timer1 oscillator and other circuitry. 14.10 Resetting Timer1 Using a CCP Trigger Output If a CCP module is configured in compare mode to generate a Special Event Trigger (CCP1M3:CCP1M0 = 1011), this signal resets Timer1. Note: Timer1 must be configured for either timer or synchronized counter mode to take advantage of the special event trigger feature. If Timer1 is running in asynchronous counter mode, this reset operation may not work and should not be used. In the event that a write to Timer1 coincides with a special event trigger from the CCP module, the write will take precedence. In this mode of operation, the CCPRxH:CCPRxL register pair effectively becomes the period register for Timer1. 14.10.1 CCP Trigger and A/D Module The special event trigger from the CCP module does not set interrupt flag bit TMR1IF. Some devices that have the CCP Trigger capability also have an A/D module. These devices may be able to be configured, so the Special Event Trigger not only resets the Timer1 registers, 0but will start an A/D conversion. This allows a constant sampling rate for the A/D, as specified by the value of the compare registers. DS39514A-page 14-12 2000 Microchip Technology Inc.

Section 14. Timer1 14.11 Resetting Timer1 Register Pair (TMR1H:TMR1L) TMR1H and TMR1L registers are not cleared on any reset, only by the CCP special event triggers. T1CON register is reset to 00h on a Power-on Reset or a Brown-out Reset. In any other reset, the register is unaffected. Timer1 is the default time base for the CCP1 and CCP2 modules. The timer can be disabled as the time base for either CCP1, CCP2, or both, and Timer3 can be substituted. This is achieved by setting control bits in the Timer3 control register. This is explained in Section 16.8 - Timer3 and CCPx Enable. When Timer1 is disabled as a the time base for a CCP, the reset on Compare will have no effect on Timer1. 14.12 Timer1 Prescaler The prescaler counter is cleared on writes to the TMR1H or TMR1L registers. 14.12.1 Timer1 Prescaler 16-bit Read/WriteMode Writes to TMR1H do not clear the Timer1 prescaler in 16-bit read/write mode, because a write to TMR1H only modifies the Timer1 latch and does not change the contents of Timer1. The prescaler is only cleared on writes to TMR1L. Table 14-2:Registers Associated with Timer1 as a Timer/Counter Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u PIR TMR1IE (1) 0 0 PIE TMR1IE (1) 0 0 IPR TMR1IP (1) 0 0 TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu T1CON RD16 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu Legend: x = unknown,u = unchanged,- = unimplemented read as '0'. Shaded cells are not used by the Timer1 module. Note 1: The placement of this bit is device dependent. 14 Timer1 2000 Microchip Technology Inc. DS39514A-page 14-13

PIC18C Reference Manual 14.13 Initialization Since Timer1 has a software programmable clock source, there are three examples to show the initialization of each mode. Example 14-4 shows the initialization for the internal clock source, Example 14-5 shows the initialization for the external clock source, and Example 14-6 shows the initialization of the external oscillator mode. Example 14-4: Timer1 Initialization (Internal Clock Source) CLRF T1CON Stop Timer1, Internal Clock Source, T1 oscillator disabled, prescaler = 1:1 CLRF TMR1H Clear Timer1 High byte register CLRF TMR1L Clear Timer1 Low byte register CLRF INTCON Disable interrupts CLRF PIE1 Disable peripheral interrupts CLRF PIR1 Clear peripheral interrupts Flags MOVLW 0x30 Internal Clock source with 1:8 prescaler MOVWF T1CON Timer1 is stopped and T1 osc is disabled BSF T1CON, TMR1ON Timer1 starts to increment The Timer1 interrupt is disabled, do polling on the overflow bit T1_OVFL_WAIT BTFSS PIR1, TMR1IF GOTO T1_OVFL_WAIT Timer has overflowed BCF PIR1, TMR1IF Example 14-5: Timer1 Initialization (External Clock Source) CLRF T1CON Stop Timer1, Internal Clock Source, T1 oscillator disabled, prescaler = 1:1 CLRF TMR1H Clear Timer1 High byte register CLRF TMR1L Clear Timer1 Low byte register CLRF INTCON Disable interrupts CLRF PIE1 Disable peripheral interrupts CLRF PIR1 Clear peripheral interrupts Flags MOVLW 0x32 External Clock source with 1:8 prescaler MOVWF T1CON Clock source is synchronized to device Timer1 is stopped and T1 osc is disabled BSF T1CON, TMR1ON Timer1 starts to increment The Timer1 interrupt is disabled, do polling on the overflow bit T1_OVFL_WAIT BTFSS PIR1, TMR1IF GOTO T1_OVFL_WAIT Timer has overflowed BCF PIR1, TMR1IF DS39514A-page 14-14 2000 Microchip Technology Inc.

Section 14. Timer1 Example 14-6: Timer1 Initialization (External Oscillator Clock Source) CLRF T1CON Stop Timer1, Internal Clock Source, T1 oscillator disabled, prescaler = 1:1 CLRF TMR1H Clear Timer1 High byte register CLRF TMR1L Clear Timer1 Low byte register CLRF INTCON Disable interrupts CLRF PIE1 Disable peripheral interrupts CLRF PIR1 Clear peripheral interrupts Flags MOVLW 0x3E External Clock source with oscillator MOVWF T1CON circuitry, 1:8 prescaler, Clock source is asynchronous to device Timer1 is stopped BSF T1CON, TMR1ON Timer1 starts to increment The Timer1 interrupt is disabled, do polling on the overflow bit T1_OVFL_WAIT BTFSS PIR1, TMR1IF GOTO T1_OVFL_WAIT Timer has overflowed BCF PIR1, TMR1IF 14 Timer1 2000 Microchip Technology Inc. DS39514A-page 14-15

PIC18C Reference Manual 14.14 Design Tips Question 1: Timer1 does not seem to be keeping accurate time. Answer 1: There are a few reasons that this could occur: 1. You should never write to Timer1 where that could cause the loss of time. In most cases, that means you should not write to the TMR1L register, but if the conditions are OK, you may write to the TMR1H register. Normally, you write to the TMR1H register if you want the Timer1 overflow interrupt to be sooner than the full 16-bit time-out. 2. You should ensure that your layout uses good PCB layout techniques so noise does not couple onto the Timer1/Timer3 oscillator lines. DS39514A-page 14-16 2000 Microchip Technology Inc.

Section 14. Timer1 14.15 Related Application Notes This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the Enhanced family (that is they may be written for the Baseline, the Midrange, or High-end families), but the concepts are pertinent, and could be used (with modification and possible limitations). The current application notes related to Timer1 are: Title Application Note # Using Timer1 in Asynchronous Clock Mode AN580 Low Power Real Time Clock AN582 Yet another Clock using the PIC16C92X AN649 Note: Please visit the Microchip Web site for additional software code examples. These code examples are stand alone examples to assist in the understanding of the PIC18CXXX. The web address for these examples is: http://www.microchip.com/10/faqs/codeex/ 14 Timer1 2000 Microchip Technology Inc. DS39514A-page 14-17

PIC18C Reference Manual 14.16 Revision History Revision A This is the initial released revision of the Timer1 module description. DS39514A-page 14-18 2000 Microchip Technology Inc.