64Mbit, 2MX32 3V Flash Memory Module

64Mbit, 2MX32 3V Flash Memory Module Features 3.0V ± 10% read and write operation 1,000,000 Block Erase Cycles Access Times: 70,90,120 &150ns 4X(32 Equal Sectors of 64-Kbyte Each) Package Options: Individual Byte Selection x32, x16 & x8 66-Pin Ceramic PGA 1.385" SQ Automated Byte Write and Block Erase Package Height 0.215"/ 0.160 Product Description The MEF2M32 is a 3V-flash EEprom MCM, organized as 2 MEG by 32 bits and can be configured as 4 Mbit X16 or 8 Mbit X8. The package is a High-Temp multilayer cofired ceramic package. The module is based on "29LV160" Dice. Byte write and automated block erase flowcharts are identical to "29LV160" Data Sheet and should be used as a reference. Block Diagram (For PGA, Standard Configuration) December, 2003 Rev. A 1 OF 17

Pin Names (For PGA, Standard Configuration) Pin Name A0 A20 DQ0 DQ31 CS1# CS4# WE1# WE4# OE# Pin Function Address Inputs Data Inputs/Outputs Chip Selects Write Enables Output Enable GND Ground RESET# internally tied to VCC in the PGA package VCC Power (+5V ±10%) NC NO CONNECTION Note: # Symbol means Active Low Signal Pin Configuration for 66-Pin PGA (Top View) A B C F G H 1 DQ8 WE2# DQ15 DQ24 VCC DQ31 2 DQ9 CS2# DQ14 DQ25 CS4# DQ30 3 DQ10 GND DQ13 DQ26 WE4# DQ29 4 A14 DQ11 DQ12 A7 DQ27 DQ28 5 A16 A10 OE# A12 A4 A1 6 A11 A9 A17 A20 A5 A2 7 A0 A15 WE1# A13 A6 A3 8 A18 VCC DQ7 A8 WE3# DQ23 9 DQ0 CS1# DQ6 DQ16 CS3# DQ22 10 DQ1 A19 DQ5 DQ17 GND DQ21 11 DQ2 DQ3 DQ4 DQ18 DQ19 DQ20 December, 2003 Rev. A 2 OF 17

Absolute Maximum Ratings Item Supply Voltage Relative to GND (1) Voltage On Any Pin Except A9 (2) A9 (2) Storage Temperature Output Short Circuit Current (3) Rating -0.5 to +4.0V -0.5 to +4.0V -0.5 to +12.5V -65 C to +150 C 200mA Notes: (1) Minimum D.C Voltage on any input is -0.5V, may undershoot to GND-2.0V for periods <20ns Maximum D.C Voltage on any output is Vcc +0.5V, may overshoot to Vcc +2.0V for periods < 20ns (2) Minimum D.C Voltage on A9 is -0.5V, may undershoot to -2.0V for periods < 20ns Maximum D.C Voltage on A9 is +12.5V, may overshoot to +14.0V for periods < 20ns (3) No more than one output shorted at a time for periods < 1second Recommended Operating Conditions Parameter Symbol Min Max Unit Supply Voltage VCC 2.7 3.6 V Input High Voltage VIH 0.7X VCC VCC +0.3 V Input Low Voltage VIL -0.5 +0.8 V Operating (Military) TA -55 +125 C Temperature (Industrial) -40 +85 C December, 2003 Rev. A 3 OF 17

Erase and Programming Performance (8 bit Operation Mode) Parameter Min Typ Max Unit Comments Sector Erase Time 0.7 (1) 15 sec Chip Erase Time 25 (1) 45 sec Byte Programming Time 9 300 (2) µs Chip Programming Time 18 (1) 54 sec Notes: (1) 25 C, 5V VCC, 1,000,000 cycles Excludes 00H Programming prior to Erasure Excludes 00H Programming prior to Erasure Excludes System-level Overhead Excludes System-level Overhead (2) When programming a "1" over a "0", the Embedded Algorithms allow for 48 ms byte Program time Capacitance (TA = +25 C, VIN = 0, f = 1.0 MHz) Description Symbol Limits Unit OE# Capacitance COE 15 pf Write Enable Capacitance WE1# to WE4# CWE 15 pf Chip Enable Capacitance CS1# to CS4# CCE 15 pf DQ0 to DQ31 Capacitance CI/O 20 pf A0 to A20 Capacitance CAD 15 pf Note: These parameters are guaranteed by design but not tested. December, 2003 Rev. A 4 OF 17

DC Characteristics (TTL Compatible, 8 bit Operation Mode) Parameter Symbol Min Max Unit Test Condition Input Load Current ILI ±1.0 µa Vcc = Max, GND=Vss to Vcc A9 Input Load Current ILIT 35 µa Vcc = Max, A9 = 12.5V Output Leakage Current ILO ±1.0 µa Vcc = Max, VOUT=GND to Vcc Vcc Active Current (1) ICC1 16 ma CS# = VIL, OE#=VIH Vcc Active Current (2)(3) ICC2 30 ma CS# = VIL, OE#=VIH Vcc Stand by Current ICC3 5 µa Vcc = Max, CS# =OE# =VIH Input Low Level VIL -0.5 0.8 V Input High Level VIH 1.9 Vcc +0.3 V Voltage for Autoselect and Sector Protect VID 11.5 12.5 V Vcc = 3.3V Output Low Voltage VOL 0.45 V IOL = 4mA, Vcc = Min Output High Voltage VOH 2.3 V IOH = -2.0mA, Vcc = Min Low Vcc Lock-Out Voltage VLKO 2.3 2.5 V Notes: (1) The Icc current listed includes both the DC operating current and the frequency Dependent component (at 6 MHz) The frequency component typically is less than 2mA/MHz, with OE# at VIH (2) Icc active while Embedded Algorithm (program or erase) is in progress (3) Not 100% tested December, 2003 Rev. A 5 OF 17

Command Definitions Command Sequence Read/Reset Bus Write Cycles Req`d First Bus Write Cycle Reset 1 XXXH FOH Read 1 RA RD Second Bus Write Cycle Third Bus Write Cycle Fourth Bus Read/Write Cycle Fifth Bus Write Cycle Sixth Bus Write Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Autoselect 4 5555H AAH 2AAAH 55H 5555H 90H Byte Program 4 5555H AAH 2AAAH 55H 5555H AOH PA Data Chip Erase 6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Sector Erase 6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA 30H Sector Erase Suspend Sector Erase Resume Erase can be suspended during sector erase with Addr (don't care), Data (BOH) Erase can be resumed after suspend with Addr (don`t care), Data (30H) Legend: X =Don t care RA =Address of the memory location to be read. RD =Data read from location RA during read operation. PA =Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CS# pulse, whichever happens later. PD =Data to be programmed at location PA. Data latches on the rising edge of WE# or CS# pulse, whichever happens first. SA =Address of the sector to be verified (in autoselect mode) or erased. Address bits A20 A16 select a unique sector. SGA =Address of the sector group to be verified. Address bits A20 A18 select a unique sector group. December, 2003 Rev. A 6 OF 17

Notes: See Wave Tables for description of bus operations. All values are in hexadecimal. Except when reading array or autoselect data, all bus cycles are write operations. Address bits A20 A11 are don t cares for unlock and command cycles, unless SA or PA required. No unlock or command cycles required when reading array data. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). The fourth cycle of the autoselect command sequence is a read cycle. The data is 00h for an unprotected sector group and 01h for a protected sector group. Command is valid when device is ready to read array data or when device is in autoselect mode. The Unlock Bypass command is required prior to the Unlock Bypass Program command. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. The Erase Resume command is valid only during the Erase Suspend mode. December, 2003 Rev. A 7 OF 17

AC Characteristics Read Only Operations Parameter Symbol 70ns 90ns 120ns 150ns Limits Unit (1) (1) (1) (1) Read Cycle Time (3) TRC 70 90 120 150 Min ns Address to Output Delay (4) TACC 70 90 120 150 Max ns Chip Enable to Output Delay (5) TCE 70 90 120 150 Max ns Output Enable to Output Delay TOE 35 35 50 55 Max ns Chip Enable to Output High Z (2)(3) TDF 20 20 30 35 Max ns Output Enable to Output High Z (2)(3) Output Hold Time from Addresses, CS# or OE#, Whichever Occurs First TDF 20 20 30 35 Max ns TOH 0 0 0 0 Min ns Notes: (1) Test Conditions: Output Load........ 1 TTL gate and 100 pf Input rise and fall times..... 20ns Input pulse levels...... 0.45V to 2.3V Timing measurement reference level: Input.......... 0.8 and 2.0V Output.......... 0.8 and 2.0V (2) Output driver disable time (3) Not 100% tested (4) Test Setup: CS# = OE#=VIL (5) Test Setup: OE#=VIL December, 2003 Rev. A 8 OF 17

AC Characteristics (Con`t) Write/Erase/Program Operations Parameter Symbol 70ns 90ns 120ns 150ns Limits Unit Write Cycle Time TWC 70 90 120 150 Min ns Address Setup Time TAS 0 0 0 0 Min ns Address Hold Time TAH 45 45 50 50 Min ns Data Setup Time TDS 45 45 50 50 Min ns Data Hold Time TDH 0 0 0 0 Min ns Output Enable Setup Time TOES 0 0 0 0 Min ns Output Enable Read TOEH 0 0 0 0 Min ns Hold Time Toggle and Data Polling 10 10 10 10 Min ns Read Recover Time Before Write TGHWL 0 0 0 0 Min ns CS# Setup Time TCS 0 0 0 0 Min ns CS# Hold Time TCH 0 0 0 0 Min ns Write Pulse Width TWP 40 45 50 50 Min ns Write Pulse Width TWPH 20 20 20 20 Min ns Byte Programming Operation TWHWH1 14 16 16 16 Min µs Erase Operation TWHWH2 1.3 28 VCC Set Up Time TVCS 45 50 50 50 Min µs Voltage Transition Time* TVLHT 4 4 4 4 Max µs Write Pulse Width* TWPP 100 100 100 100 Min µs OE# Setup Time to WE# Active* TOESP 4 4 4 4 Min µs CS# Setup Time to WE# Active* TCSP 4 4 4 4 Min µs (*) - See protect/unprotected waveforms 1.5 30 1.5 30 1.5 30 Min Max sec sec December, 2003 Rev. A 9 OF 17

AC Characteristics Write/Erase/Program Operations (Alternate CS# Controlled Writes) Parameter Symbol 70ns 90ns 120ns 150ns Limits Unit Write Cycle Time TWC 70 90 120 150 Min ns Address Setup Time TAS 0 0 0 0 Min ns Address Hold Time TAH 45 45 50 50 Min ns Data Setup Time TDS 45 45 50 50 Min ns Data Hold Time TDH 0 0 0 0 Min ns Output Enable Setup Time TOES 0 0 0 0 Min ns Output Enable Read TOEH 0 0 0 0 Min ns Hold Time Toggle and Data Polling 10 10 10 10 Min ns Read Recover Time Before Write TGHEL 0 0 0 0 Min ns WE# Setup Time TWS 0 0 0 0 Min ns WE# Hold Time TWH 0 0 0 0 Min ns CS# Pulse Width TCP 40 45 50 50 Min ns CS# Pulse Width High TCPH 20 20 20 20 Min ns Byte Programming Operation TWHWH1 14 16 14 14 Min µs Erase Operation TWHWH2 1.3 28 1.5 30 1.5 30 1.5 30 Min Max Vcc Setup Time TVCS 45 50 50 50 Min µs sec sec December, 2003 Rev. A 10 OF 17

Timing Waveforms General Definitions and Notes 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the data written to the device. 4. Dout is the output of the data written to the device. 5. Timing indicates last two bus cycles of four bus cycle sequence. Timing Waveforms for Read Operation CS# December, 2003 Rev. A 11 OF 17

Timing Waveforms for Program Operation CS# Timing Waveforms for Chip/Sector Erase Operations CS# December, 2003 Rev. A 12 OF 17

Timing Waveforms for Data Polling during Embedded Algorithm Operations CS# Timing Waveforms for Toggle Bit During Embedded Algorithm Operations CS# December, 2003 Rev. A 13 OF 17

Timing Waveforms for Program Operation (Alternate CS# Controlled) CS# Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the data written to the device. 4. Dout is the output of the data written to the device. 5. Timing indicates last two bus cycles of four-bus cycle sequence. December, 2003 Rev. A 14 OF 17

Outline Drawing for 66-Pin Ceramic PGA (G1) December, 2003 Rev. A 15 OF 17

Outline Drawing for 66-Pin Thin Ceramic PGA (G2) December, 2003 Rev. A 16 OF 17

Ordering Information (Standard Industrial Screened Products*) Model Number Speed Package MEF2M32G1070I3 70ns PGA MEF2M32G1090I3 90ns PGA MEF2M32G1120I3 120ns PGA MEF2M32G1150I3 150ns PGA MEF2M32G2070I3 70ns PGA MEF2M32G2090I3 90ns PGA MEF2M32G2120I3 120ns PGA MEF2M32G2150I3 150ns PGA (*) - Contact Elisra for additional designs Part Number Breakdown December, 2003 Rev. A 17 OF 17