COMPANY PROFILE 1-1 SECTION 1. INTRODUCTION 1-1 Introduction... 1-2 Manual Objective... 1-3 Device Structure... 1-4 Development Support... 1-6 Device Varieties... 1-7 Style and Symbol Conventions... 1-12 Related Documents... 1-14 Related Application Notes... 1-17 Revision History... 1-18 SECTION 2. OSCILLATOR 2-1 Introduction... 2-2 Control Register... 2-3 Oscillator Configurations... 2-4 Crystal Oscillators/Ceramic Resonators... 2-6 External RC Oscillator... 2-15 HS4... 2-18 Switching to Low Power Clock Source... 2-19 Effects of Sleep Mode on the On-Chip Oscillator... 2-23 Effects of Device Reset on the On-Chip Oscillator... 2-23 Design Tips... 2-24 Related Application Notes... 2-25 Revision History... 2-26 SECTION 3. RESET 3-1 Introduction... 3-2 Resets and Delay Timers... 3-4 Registers and Status Bit Values... 3-14 Design Tips... 3-20 Related Application Notes... 3-21 Revision History... 3-22 SECTION 4. ARCHITECTURE 4-1 Introduction... 4-2 Clocking Scheme/Instruction Cycle... 4-5 Instruction Flow/Pipelining... 4-6 I/O Descriptions... 4-7 Design Tips... 4-14 Related Application Notes... 4-15 Revision History... 4-16 DS39500A-page iii
SECTION 5. CPU AND ALU 5-1 Introduction... 5-2 General Instruction Format... 5-6 Central Processing Unit (CPU)... 5-7 Instruction Clock... 5-8 Arithmetic Logical Unit (ALU)... 5-9 STATUS Register... 5-11 Design Tips... 5-14 Related Application Notes... 5-15 Revision History... 5-16 SECTION 6. HARDWARE 8X8 MULTIPLIER 6-1 Introduction... 6-2 Operation... 6-3 Design Tips... 6-6 Related Application Notes... 6-7 Revision History... 6-8 SECTION 7. MEMORY ORGANIZATION 7-1 Introduction... 7-2 Program Memory... 7-3 Program Counter (PC)... 7-6 Lookup Tables... 7-9 Stack... 7-12 Data Memory Organization... 7-13 Return Address Stack... 7-17 Initialization... 7-23 Design Tips... 7-24 Related Application Notes... 7-25 Revision History... 7-26 SECTION 8. TABLE READ/TABLE WRITE 8-1 Introduction... 8-2 Control Registers... 8-3 Program Memory... 8-6 Enabling Internal Programming... 8-12 External Program Memory Operation... 8-12 Initialization... 8-13 Design Tips... 8-14 Related Application Notes... 8-15 Revision History... 8-16 DS39500A-page iv
SECTION 9. SYSTEM BUS 9-1 Revision History... 9-2 SECTION 10. INTERRUPTS 10-1 Introduction... 10-2 Control Registers... 10-6 Interrupt Handling Operation... 10-19 Initialization... 10-29 Design Tips... 10-30 Related Application Notes... 10-31 Revision History... 10-32 SECTION 11. I/O PORTS 11-1 Introduction... 11-2 PORTA, TRISA, and the LATA Register... 11-8 PORTB, TRISB, and the LATB Register... 11-12 PORTC, TRISC, and the LATC Register... 11-16 PORTD, LATD, and the TRISD Register... 11-19 PORTE, TRISE, and the LATE Register... 11-21 PORTF, LATF, and the TRISF Register... 11-23 PORTG, LATG, and the TRISG Register... 11-25 PORTH, LATH, and the TRISH Register...11-27 PORTJ, LATJ, and the TRISJ Register... 11-29 PORTK, LATK, and the TRISK Register... 11-31 PORTL, LATL, and the TRISL Register... 11-33 Functions Multiplexed on I/O Pins... 11-35 I/O Programming Considerations... 11-37 Initialization... 11-40 Design Tips... 11-41 Related Application Notes... 11-43 Revision History... 11-44 SECTION 12. PARALLEL SLAVE PORT 12-1 Introduction... 12-2 Control Register... 12-3 Operation... 12-5 Operation in SLEEP Mode... 12-6 Effect of a RESET... 12-6 PSP Waveforms... 12-6 Design Tips... 12-8 Related Application Notes... 12-9 Revision History... 12-10 DS39500A-page v
SECTION 13. TIMER0 13-1 Introduction... 13-2 Control Register... 13-3 Operation... 13-4 Timer0 Interrupt... 13-5 Using Timer0 with an External Clock... 13-6 Timer0 Prescaler... 13-7 Initialization... 13-9 Design Tips... 13-10 Related Application Notes... 13-11 Revision History... 13-12 SECTION 14. TIMER1 14-1 Introduction... 14-2 Control Register... 14-4 Timer1 Operation in Timer Mode... 14-5 Timer1 Operation in Synchronized Counter Mode... 14-5 Timer1 Operation in Asynchronous Counter Mode... 14-6 Reading and Writing of Timer1... 14-7 Timer1 Oscillator... 14-10 Typical Application... 14-11 Sleep Operation... 14-12 Resetting Timer1 Using a CCP Trigger Output... 14-12 Resetting Timer1 Register Pair (TMR1H:TMR1L)... 14-13 Timer1 Prescaler... 14-13 Initialization... 14-14 Design Tips... 14-16 Related Application Notes... 14-17 Revision History... 14-18 SECTION 15. TIMER2 15-1 Introduction... 15-2 Control Register... 15-3 Timer Clock Source... 15-4 Timer (TMR2) and Period (PR2) Registers... 15-4 TMR2 Match Output... 15-4 Clearing the Timer2 Prescaler and Postscaler... 15-4 Sleep Operation... 15-4 Initialization... 15-5 Design Tips... 15-6 Related Application Notes... 15-7 Revision History... 15-8 DS39500A-page vi
SECTION 16. TIMER3 16-1 Introduction... 16-2 Control Registers... 16-3 Timer3 Operation in Timer Mode... 16-4 Timer3 Operation in Synchronized Counter Mode... 16-4 Timer3 Operation in Asynchronous Counter Mode... 16-5 Reading and Writing of Timer3... 16-6 Timer3 using the Timer1 Oscillator... 16-9 Timer3 and CCPx Enable... 16-10 Timer3 Prescaler... 16-10 16-bit Mode Timer Reads/Writes... 16-11 Typical Application... 16-12 Sleep Operation... 16-13 Timer3 Prescaler... 16-13 Initialization... 16-14 Design Tips... 16-16 Related Application Notes... 16-17 Revision History... 16-18 SECTION 17. COMPARE/CAPTURE/PWM (CCP) 17-1 Introduction... 17-2 CCP Control Register... 17-3 Capture Mode... 17-4 Compare Mode... 17-7 PWM Mode... 17-10 Initialization... 17-15 Design Tips... 17-17 Related Application Notes... 17-19 Revision History... 17-20 SECTION 18. ECCP 18-1 SECTION 19. SYNCHRONOUS SERIAL PORT (SSP) 19-1 Introduction... 19-2 Control Registers... 19-4 SPI Mode... 19-8 SSP I 2 C Operation... 19-18 Initialization... 19-28 Design Tips... 19-30 Related Application Notes... 19-31 Revision History... 19-32 DS39500A-page vii
SECTION 20. MASTER SSP 20-1 Introduction... 20-2 Control Registers... 20-4 SPI Mode... 20-9 MSSP I 2 C Operation... 20-18 Design Tips... 20-58 Related Application Notes... 20-59 Revision History... 20-60 SECTION 21. ADDRESSABLE USART 21-1 Introduction... 21-2 Control Registers... 21-3 USART Baud Rate Generator (BRG)... 21-5 USART Asynchronous Mode... 21-9 USART Synchronous Master Mode... 21-18 USART Synchronous Slave Mode... 21-23 Initialization... 21-25 Design Tips... 21-26 Related Application Notes... 21-27 Revision History... 21-28 SECTION 22. CAN 22-1 Introduction... 22-2 Control Registers for the CAN Module... 22-3 CAN Overview... 22-28 CAN Bus Features... 22-32 CAN Module Implementation... 22-33 Frame Types... 22-37 Modes of Operation... 22-44 CAN Bus Initialization... 22-48 Message Reception... 22-49 Transmission... 22-60 Error Detection... 22-69 Baud Rate Setting... 22-71 Interrupts... 22-75 Timestamping... 22-77 CAN Module I/O... 22-77 Design Tips... 22-78 Related Application Notes... 22-79 Revision History... 22-80 DS39500A-page viii
SECTION 23. COMPARATOR VOLTAGE REFERENCE 23-1 Introduction... 23-2 Control Register... 23-3 Configuring the Voltage Reference... 23-4 Voltage Reference Accuracy/Error... 23-5 Operation During Sleep... 23-5 Effects of a Reset... 23-5 Connection Considerations... 23-6 Initialization... 23-7 Design Tips... 23-8 Related Application Notes... 23-9 Revision History... 23-10 SECTION 24. COMPARATOR 24-1 Introduction... 24-2 Control Register... 24-3 Comparator Configuration... 24-4 Comparator Operation... 24-6 Comparator Reference... 24-6 Comparator Response Time... 24-8 Comparator Outputs... 24-8 Comparator Interrupts... 24-9 Comparator Operation During SLEEP... 24-9 Effects of a RESET... 24-9 Analog Input Connection Considerations... 24-10 Initialization... 24-11 Design Tips... 24-12 Related Application Notes... 24-13 Revision History... 24-14 SECTION 25. COMPATIBLE 10-BIT A/D CONVERTER 25-1 Introduction... 25-2 Control Register... 25-4 Operation... 25-7 A/D Acquisition Requirements... 25-8 Selecting the A/D Conversion Clock... 25-10 Configuring Analog Port Pins... 25-11 A/D Conversions... 25-12 Operation During Sleep... 25-16 Effects of a Reset... 25-16 A/D Accuracy/Error... 25-17 Connection Considerations... 25-18 Transfer Function... 25-18 Initialization... 25-19 Design Tips... 25-20 Related Application Notes... 25-21 Revision History... 25-22 DS39500A-page ix
SECTION 26. 10-BIT A/D CONVERTER 26-1 Introduction... 26-2 Control Register... 26-4 Operation... 26-7 A/D Acquisition Requirements... 26-8 Selecting the A/D Conversion Clock... 26-10 Configuring Analog Port Pins... 26-11 A/D Conversions... 26-12 Operation During Sleep... 26-16 Effects of a Reset... 26-16 A/D Accuracy/Error... 26-17 Connection Considerations... 26-18 Transfer Function... 26-18 Initialization... 26-19 Design Tips... 26-20 Related Application Notes... 26-21 Revision History... 26-22 SECTION 27. LOW VOLTAGE DETECT 27-1 Introduction... 27-2 Control Register... 27-4 Operation... 27-5 Operation During Sleep... 27-6 Effects of a Reset... 27-6 Initialization... 27-7 Design Tips... 27-8 Related Application Notes... 27-9 Revision History... 27-10 SECTION 28. WDT AND SLEEP MODE 28-1 Introduction... 28-2 Control Register... 28-3 Watchdog Timer (WDT) Operation... 28-4 SLEEP (Power-Down) Mode... 28-5 Initialization... 28-11 Design Tips... 28-12 Related Application Notes... 28-13 Revision History... 28-14 DS39500A-page x
SECTION 29. DEVICE CONFIGURATION BITS 29-1 Introduction... 29-2 Configuration Word Bits... 29-3 Program Verification/Code Protection... 29-10 ID Locations... 29-11 Device ID... 29-11 Design Tips... 29-12 Related Application Notes... 29-13 Revision History... 29-14 SECTION 30. IN-CIRCUIT SERIAL PROGRAMMING (ICSP ) 30-1 Introduction... 30-2 Entering In-Circuit Serial Programming Mode... 30-3 Application Circuit... 30-4 Programmer... 30-6 Programming Environment... 30-6 Other Benefits... 30-7 Field Programming of PICmicro OTP MCUs... 30-8 Field Programming of FLASH PICmicros... 30-10 Design Tips... 30-12 Related Application Notes... 30-13 Revision History... 30-14 SECTION 31. INSTRUCTION SET 31-1 Introduction... 31-2 Data Memory Map... 31-3 Instruction Formats... 31-9 Special Function Registers as Source/Destination... 31-12 Fast Register Stack... 31-13 Q Cycle Activity... 31-13 Instruction Descriptions... 31-14 Design Tips... 31-136 Related Application Notes... 31-137 Revision History... 31-138 DS39500A-page xi
SECTION 32. ELECTRICAL SPECIFICATIONS 32-1 Introduction... 32-2 Absolute Maximums... 32-3 Voltage vs Frequency Graph... 32-4 Device Voltage Specifications... 32-6 Device Current Specifications... 32-7 Input Threshold Levels... 32-10 I/O Current Specifications... 32-11 Output Drive Levels... 32-12 I/O Capacitive Loading... 32-13 Low Voltage Detect (LVD)... 32-14 EPROM/FLASH/Data EEPROM... 32-15 Comparators and Voltage Reference... 32-16 Timing Parameter Symbology... 32-18 Example External Clock Timing Waveforms and Requirements... 32-19 Example Phase Lock Loop (PLL) Timing Waveforms and Requirements... 32-20 Example Power-up and RESET Timing Waveforms and Requirements... 32-22 Example Timer0 and Timer1 Timing Waveforms and Requirements... 32-23 Example CCP Timing Waveforms and Requirements... 32-24 Example Parallel Slave Port (PSP) Timing Waveforms and Requirements... 32-25 Example SSP and Master SSP SPI Mode Timing Waveforms and Requirements... 32-26 Example SSP I 2 C Mode Timing Waveforms and Requirements... 32-30 Example Master SSP I 2 C Mode Timing Waveforms and Requirements... 32-32 Example USART/SCI Timing Waveforms and Requirements... 32-34 CAN Specifications... 32-35 Example 8-bit A/D Timing Waveforms and Requirements... 32-36 Example 10-bit A/D Timing Waveforms and Requirements... 32-38 Design Tips... 32-40 Related Application Notes... 32-41 Revision History... 32-42 SECTION 33. DEVICE CHARACTERISTICS 33-1 Introduction... 33-2 Characterization vs. Electrical Specification... 33-2 DC and AC Characteristics Graphs and Tables... 33-2 Revision History... 33-26 DS39500A-page xii
SECTION 34. DEVELOPMENT TOOLS 34-1 Introduction... 34-2 The Integrated Development Environment (IDE)... 34-3 MPLAB Software Language Support... 34-6 MPLAB-SIM Simulator Software... 34-8 MPLAB Emulator Hardware Support... 34-9 MPLAB High Performance Universal In-Circuit Emulator with MPLAB IDE... 34-9 MPLAB-ICD In-Circuit Debugger... 34-9 MPLAB Programmer Support... 34-10 Supplemental Tools... 34-11 Development Boards... 34-12 Development Tools for Other Microchip Products... 34-14 Related Application Notes... 34-15 Revision History... 34-16 SECTION 35. CODE DEVELOPMENT 35-1 Overview... 35-2 Good Practice... 35-3 Diagnostic Code Techniques... 35-5 Example Scenario and Implementation... 35-6 Implications of Using a High Level Language (HLL)... 35-7 Revision History... 35-8 SECTION 36. APPENDIX 36-1 Appendix A: I 2 C Overview... 36-1 Appendix B: CAN Overview... 36-12 Appendix C: Module Block Diagrams and Registers... 36-13 Appendix D: Register Definitions... 36-14 Appendix E: Migration Tips... 36-15 SECTION 37. GLOSSARY 37-1 Revision History... 37-14 SOURCE CODE Table of Contents INDEX DS39500A-page xiii
NOTES: DS39500A-page xiv