Course Topics - Outline Lecture 1 - Introduction Lecture 2 - Lexical conventions Lecture 3 - Data types Lecture 4 - Operators Lecture 5 - Behavioral modeling A Lecture 6 Behavioral modeling B Lecture 7 Behavioral modeling C Lecture 8 Data flow modeling Lecture 9 Gate Level modeling Lecture 10 Tasks and Functions Lecture 11 Advanced Modeling Techniques Lecture 12 - Coding Styles and Test Benches Lecture 13 - Switch Level modeling 1
2 Lecture 3 Data Types Nets Registers Register Data Types Examples Vectors Indexed part select Concatenation and Replication Arrays Memory Modeling Parameters Verilog Logic System Truth Tables Exercise 3
3 Nets Net: Data type that can be used to model physical connection between structural elements. Net has a value continuously driven by: - Continuous assignment - Module or gate instantiation The most commonly used net is declared with Keyword wire. Its default value is Z. wire c will continuously assume value at the output of AND gate. Net is a one bit value (scalar) by default unless it is declared vector (array of bits) explicitly. a b c
Net Data Types Net Data Type wire, tri wor, trior wand, triand tri0, tri1 supply0, supply1 trireg Functionality Interconnecting wire no special resolution function Wired outputs OR together (models ECL) Wired outputs AND together (models open-collector) Net pulls-down or pulls-up when not driven Net has a constant logic 0 or logic 1 (supply strength Ground or Vcc) Retains last value, when driven by z (tri-state). 4
Net Data types examples A B Y wire Y ; // declaration assign Y = A & B ; A B A dr Y Y wand Y ; // declaration assign Y = A ; assign Y = B ; wor Y; // declaration assign Y = A ; assign Y = B ; tri Y ; // declaration assign Y = (dr)? A : Z ; 5
Registers Registers are abstractions of storage devices found in real system. Register retains its value until it is overridden, within procedural blocks. Register types (keywords): reg,integer, real, time reg: any size, unsigned (can be declared as signed), default size is 1, default value is X integer: 32-bit signed variable (2 s complement) real: 64-bit, real number, decimal or scientific notations, default value 0, no range declaration time: 64-bit, unsigned. Defaults to initial value of 0 integer, real are similar to C programming. 6
Register Data Types Examples reg OK_flag ; reg [31:0] data1 ; reg [0:31] data2 ; // 1-bit register // Little Endian notation // Big Endian notation integer counter ; // 32-bit. initial counter = -1 ; real delta ; // delta = 2.13 ; delta = 4e10 ; time save_sim_time ; /* System function $time is invoked to get the current simulation time */ save_sim_time = $time ; 7
Vectors Vector : net or reg data types can be declared as vectors ( Multiple bit widths). If bit width is not specified the default is 1 bit (scalar). Example: wire [7:0] a ; reg [31:0] b ; Both bit-select and part-select can be used. Examples: reg [11:0] counter ; reg a ; reg [2:0] b ; a = counter[7] ; // bit seven is loaded into a b = counter[4:2] ; // bits 4, 3, and 2 are loaded into b 8
9 index part select Verilog1995 permits variable bit selects of vector but partselects must be constant. It is illegal to use a variable to select a specific byte out of a word. Verilog2001 allows indexing vectors using variable expressions to perform dynamic parts select. The syntax is as follows: [base_expression +: width_expression] or [base_expression -: width_expression] base_expression can be a variable expression, vary during simulation run-time but width_expression must be a constant Offset direction indicates if the width_expression is added (+:) or subtracted (-:) from the base_expression.
index part select examples reg [63:0] word ; reg [3:0] byte_num ; //a value from 0 to 7. reg [7:0] byten ; // If byte_num = 4 byten = word[byte_num*8 +: 8] ; //= word[39:32] reg [31:0] a ; b = a[8+:16] ; // b = a[23:8] c = a[31-:8] ; // c = a[31-24] 10
11 indexed part select example // Break down a 40-bit vector string into 5 separate bytes Use 5 bytes hard-coded slices Use indexed part select module indexarr ; reg [39:0] str ; // string initial begin str = "abcde ; $display("%s", str[7:0]) ; $display("%s", str[15:8]) ; $display("%s", str[23:16]) ; $display("%s", str[31:24]) ; $display("%s", str[39:32]) ; end endmodule // output: e, d, c, b, a module indexarr ; reg [39:0] str ; // string integer i ; initial begin str = "abcde ; for (i = 0 ; i < 5 ; i = i + 1) $display("%s", str[i*8 +: 8]) ; end endmodule
12 Concatenation and Replication The concatenation operator { } provides mechanism to append multiple operands. Operands must be sized. Examples: // A = 1 b1, B = 2 b00, C = 2 b10, D = 3 b110 Y = {B, C} ; // Result Y is 4 b0010 Y = {A, B, C, D, 3 b001} ; // Result Y is 11 b10010110001 Y = {A, B[0], C[1]} ; // Result Y is 3 b101 assign {b [7:0], b[15:8]} = {a[15:8], a [7:0]} ; // Byte swap assign FA_out = {cout, sum} ; // Full Adder output: carry out + Sum Repetitive concatenation of the same number, can be expressed by using the replication constant. Y = {4{A}} ; // Result Y is 4 b1111 Y = {4{A}, 2{B}, C} ; // Result Y is 10 b1111000010
13 n-bit Signals Multi-bit buses and signals are easily defined in Verilog. Example: 2-to-1 multiplexer with 8-bits operands module mux 2_to_1 (a, b, sel, out) ; input [7:0] a, b ; input sel ; output reg [7:0] out ; always @(a, b, sel) a 8 begin if (sel) out = a ; b 8 else out = b ; end endmodule 1 0 sel 8 out
Arrays Arrays are allowed for reg, integer, time and vector register data types. Multi-dimensional arrays can also be declared with any number of dimensions. Arrays of nets can also be used to connect ports of generated instances. Definition syntax <data_type_spec> {size} <variable_name> {array_size} Reference syntax <variable_name> {array_reference} {bit_reference} 14
Array Examples reg [7:0] my_reg [0:31] ; // Array of 32 byte-wide registers integer matrix [4:0] [0:255] ; // 2-dimentional Array of integers time chk_point [1:100] ; // 100 time checkpoint variables Array my_reg[15] ; // Referencing the 16th byte of the array register integer [3:0] out [31:0] ; // 32 4-bits output elements out[27][3] ; // Referencing bit number 3 in element number 27 15
16 Bit and part selects within arrays The Verilog-1995 standard does not permit directly accessing a bit or part select of an array word. A full array word has to copied to a temporary variable, and the bit or part selected from the temporary variable. Verilog-2001 removes this restriction, and allows bit selects and part selects of array words to be directly accessed. For example: /*select the high-order byte of one word in a 2-dimensional array of 32-bit reg variables */ reg [31:0] array2 [0:255][0:15] ; wire [7:0] out2 = array2[100][7][31:24] ;
17 Memory Modeling In digital simulation one needs to model - Register Files - RAMs - ROMs - FIFOs. Memories are modeled as array of registers. reg [7:0] my_memory[0:1023] ; // 1K bytes memory // read a byte from address 511 data_out = my_memory[511] ; // Write a byte to address 374 my_memory[374] = data_in ;
18 Parameters Parameter: A constant value declared within a module structure with the keyword parameter. The value can be used to define a set of attributes for the module which can characterize its behavior as well as its physical representation. Parameters allow us to define generic module. Hardcoded numbers should be avoided in module definition. Parameter values for each module instance can be overridden individually at compilation time. This allows module instances to be customized. Parameters values can be changed at module instantiation or by using the defparam statement. localparam keyword provides protection against defparam unintentional modifications.
Parameters tips defparam could be applied on parameter in any hierarchy in design: defparam top.sram_ctrl.wr_cmd.dt_width = 32 ; Parameters can get the result of operation on other parameters: parameter a = 8 ; parameter b = 4 ; parameter c = a * b ; // c = 32 19
To define parameter: Parameter syntax parameter (or localparam) <parameter_name> = <value> ; To override the value of defined parameter: defparam <parameter_path>.<parameter_name> = <value> ; Instantiate modules with new parameter values: Assignment by ordered list <module name> # (value 1, 2,.n) <instance name> () ; Note: if there is a missing value, last one gets the default value Assignment by name <module name> # (.a(value),,.n(value)) <instance name> () ; Note: if there is a missing name, it gets the default value 20
21 Parameters Examples parameter width = 32 ; wire [width-1:0] din ; // Data input width definition localparam state1 = 4 b0001, /* state machine encoding state2 = 4 b0010, cannot be changed */ state3 = 4 b0100, state4 = 4 b1000 ; module hello_world ; parameter id_num = 0 ; // define module id number = 0 module top ; defparam w1.id_num = 1, w2.id_num = 2 ; // instantiate two hello_world modules hello_world w1 () ; hello_world w2 () ; endmodule
Parameters Examples cont. module bus_master ; parameter delay1 = 2 ; // rise time parameter delay2 = 3 ; // fall time parameter delay3 = 7 ; // turn-off time... endmodule Top-level module passes parameters to instances b1, b2, b3 Assignment by order list: bus_master # (4, 5, 6) b1 () ; // b1: delay1=4, delay2=5, delay3=6 bus_master # (9, 4) b2 () ; // b2: delay1=9, delay2=4, delay3=7 Assignment by name: bus_master # (.delay2(4), delay3(7)) b3 () ; // b3: delay1=2, delay2=4, delay3=7 22
4 value logic system Verilog Logic System 0 1 X Z Logic zero or false condition Logic one or true condition unknown logic value or conflict high-impedance state, unconnected Note: x and z have limited use for synthesis 23
Four-valued Logic Logical operators work on three-valued logic 0 1 X Z 0 0 0 0 0 1 0 1 X X X 0 X X X Z 0 X X X Output 0 if one input is 0 Output X if both inputs are gibberish 24
And Truth Table AND 0 1 X 0 0 0 0 1 0 1 X X 0 X X 25
Or Truth Table OR 0 1 X 0 0 1 X 1 1 1 1 X X 1 X 26
Xor Truth Table XOR 0 1 X 0 0 1 X 1 1 0 X X X X X 27
Exercise 3 Indexed part select: 256bits data buffer. Select/break down to bytes by pointer + and to 32bits by pointer Part select (bytes) within Data_RAM array. Concatenation and Replication: 16bit MIPS immediate 2 s complement value to 32bit word. MIPS Instruction Memory 128 32bit words ROM. Asynchronous read. Initialized by inst_rom.list file Register File 32 32bits registers, 3 address ports, 2 for read, 1 for write, 2 output ports. Use Asynchronous read, synchronous write SRAM. Zero content @ reset. Parametric / Generic Ripple-Carry Adder (n-bits) 28