ES 210 Lab. Jack Ou, Ph.D.

ES 210 Lab Jack Ou, Ph.D. April 30, 2013

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Contents 1 555 Timer 5 1.1 A Monostable Circuit...................... 5 1.1.1 Parts............................ 5 1.1.2 A Monostable Circuit.................. 5 1.2 An Astable Circuit........................ 7 1.2.1 Parts............................ 7 1.2.2 An Astable Circuit.................... 7 2 Full Adder 9 2.1 Modeling a Full Adder with Verilog............... 9 2.2 FPGA Implementation of a Full Adder............. 9 2.3 Implement a Full Adder Using 74XX Logic Gates....... 9 2.4 Submission Checklist....................... 10 3 4-Bit Binary Adder with Look-ahead Carry 11 3.1 Modeling a 4-Bit Binary Adder with Verilog.......... 11 3.2 FPGA Implementation of a Full Adder............. 11 3.3 Implement a Full Adder Using 74XX Logic Gates....... 11 3.4 Submission Checklist....................... 12 4 Printed Circuit Board Layout 13 4.1 Procedure............................. 13 4.2 Submission Checklist....................... 13 5 PCB Fabrication 15 5.1 Procedure............................. 15 5.2 Submission Checklist....................... 16 3

4 CONTENTS 6 D Latch 17 6.1 Verilog Simulation........................ 17 6.1.1 Random Number Generator............... 17 6.1.2 Using Random Numbers in Verilog Simulation.... 17 6.1.3 Generate a Verilog Model of a D Latch........ 18 6.1.4 Generate a test bench for D Latch........... 18 6.2 NAND based D Latch...................... 18 6.3 Submission Checklist....................... 18 7 Test a D-Latch with a Pseudo Random Sequence 19 7.1 Random Number Generator................... 19 7.2 Mixed Signal Generator..................... 20 7.3 Test the D-Latch with a pseudo random sequence....... 20 7.4 Submission Checklist....................... 20 8 Clocked Sequential Circuit 21 8.1 Building a Verilog Model.................... 21 8.2 Hardware Implementation.................... 22 8.3 Submission Checklist....................... 22 9 Universal Shift Register 25 9.1 Model the Universal Shift Register in Verilog Model..... 25 9.2 Hardware Implementation.................... 26 9.3 Submission Checklist....................... 27 10 Synchronous Counter 29 10.1 Datasheet............................. 29 10.2 Hardware Implementation.................... 30 10.3 Submission Checklist....................... 30 11 Random Access Memory 31 11.1 Schematic............................. 31 11.2 Experiment............................ 32 11.3 Submission Checklist....................... 33

Chapter 1 555 Timer 1.1 A Monostable Circuit 1.1.1 Parts One 555 timer IC One 150 Ω resistor Two 100 kω resistor Two 22 µf capacitor Two 10 µf capacitor Two 1 µf capacitor 1.1.2 A Monostable Circuit You will build a monostable multivibrator circuit based on the NEC 555 timer IC. If you do not have a debounced switch available, you can use the debouncing circuit in Figure 1.1. The output from the debouncing circuit emits a positive voltage beginning when input switch is first pressed. The output remains high for a time after the switch is released. The delay is adjustable by changing the value of capacitor C 1 and C 2. 1. Build the monostable circuit in Figure 1.1. ( Use C 1 = C 2 = 22µF ) 2. Leave the switch open for now. Check the voltage reading at each pin against its expected voltage reading in Table 1.1 to make sure that the chip is biased correctly. 5

6 CHAPTER 1. 555 TIMER Figure 1.1: A monostable circuit Pin Expected Voltage 1 0 2 9V 3 0V 4 9V 5 6V 6 0V 7 0V 8 9V Table 1.1: Expected voltage reading when the switch is open 3. Attach a voltmeter across C 1. Close the switch and observe the voltage across C 1. What happens to the voltage across C 1? 4. What happens to the voltage at pin 7 after the LED is turned off? 5. The pulse width (time duration) of the positive pulse at the the output of the timer IC is determined by R 2 and C 1. The pulse width can be calculated approximately using Equation 1.1 where R 2 is in kω, C 1 is in µf, and the pulse width is in seconds. t P ulsew idth = 0.0011R 2 C 1 (1.1) 6. Change the pulse width by using different capacitors. Calculate the

1.2. AN ASTABLE CIRCUIT 7 expected duration of the pulse by using Equation 1.1. Measure the duration of the pulse width. Record the result in Table 1.2. R 2 C 1 Calculated t P ulsew idth Measured t P ulsew idth 100 kω 22 µf 100 kω 10 µf 100 kω 1 µf Table 1.2: Calculated/Measured pulse width 1.2 An Astable Circuit 1.2.1 Parts One 555 timer IC One 1 kω resistor One 1 MΩ resistor Two 1 µf capacitor One 360 kω resistor One 150 Ω resistor 1.2.2 An Astable Circuit An astable circuit can be used as a free running clock for digital circuits. 1. Build the astable circuit as shown in Figure 1.2. Use the following combination of resistors and capacitors: R 1 = 1kΩ, R 2 = 1MΩ, C 1 = C 2 = 1µF. 2. If you ve connected the circuit correctly, the LED should begin to blink as soon as you connect the power supply to the circuit. What is the period associated with the LED? 3. What will happen to the LED when R 2 is replaced with a smaller resistor? 4. Use a 360 kω resistor for R 2. Observe the period associated with the blinking LED. Record your result in Table 1.3.

8 CHAPTER 1. 555 TIMER Figure 1.2: The astable circuit R 1 R 2 C 1 Period (seconds) 1 kω 1 MΩ 1 µf 1 kω 360 kω 1 µf Table 1.3: Measured period

Chapter 2 Full Adder 2.1 Modeling a Full Adder with Verilog 1. Use Verilog to model the behavior of a full adder. 2. You should have the following Verilog files: (a) half_adder.v: a verilog model of the half adder cell. (b) half_adder_top.v: a test bench for half_adder.v. You may use reg to provide input to the half adder cell. (c) full_adder.v: a verilog model of the full adder cell. (d) full_adder_top.v: a test bench for full_adder.v. 2.2 FPGA Implementation of a Full Adder 1. Implement a full adder using the FPGA. You may use either the sliding switches or the push buttons as your inputs. 2.3 Implement a Full Adder Using 74XX Logic Gates 1. Use 74XX Logic Gates to build a full adder. You may use the 7486 as your XOR gate, the 7408 as your AND gate, and the 7432 as your OR. 9

10 CHAPTER 2. FULL ADDER 2.4 Submission Checklist 1. Simulation results of half_adder_top.v. 2. Simulation results of full_adder_top.v. 3. Demonstration of the FPGA board. 4. A truth table summarizing measured results of the FPGA adder.

Chapter 3 4-Bit Binary Adder with Look-ahead Carry 3.1 Modeling a 4-Bit Binary Adder with Verilog 1. Use Verilog to model the behavior of a 4-bit binary adder. 2. You should have the following Verilog files: (a) carry_lookahead.v: a verilog model for the carry lookahead cell. (b) four_bit_adder_carry_lookahead.v: a verilog model for the four-bit adder using a carry lookahead cell. (c) four_adder_carry_lookahead_top.v: a test bench for four_adder_carry_lookahead.v. 3.2 FPGA Implementation of a Full Adder 1. Implement the four bit adder the FPGA. You may use the sliding switches as your inputs and the LEDs above the switches as your outputs. 3.3 Implement a Full Adder Using 74XX Logic Gates 1. Use 74LS83 chip to build the four-bit adder. 11

12CHAPTER 3. 4-BIT BINARY ADDER WITH LOOK-AHEAD CARRY 3.4 Submission Checklist 1. Demonstrate of the FPGA board to the student assistant. 2. Demonstrate the four-bit adder you built with the 74LS83 chip.

Chapter 4 Printed Circuit Board Layout 4.1 Procedure 1. Use the lecture notes on PCB fabrication as a guide. Build your own PCB layout for the 4-bit binnary adder/subtractor circuit. 2. Start by building your own schematic for the adder/subtractor circuit. 3. Once you are done with the schematic entry, generate a board layout of your circuit. The vertical dimension of your circuit should be no more than 2.5 inches. 4. Connect the IC chips with wires. You can use both the top metal layer and the bottom metal layer for this layout. 4.2 Submission Checklist 1. A print-out of the schematic. 2. A print-out of the board level layout. 13

14 CHAPTER 4. PRINTED CIRCUIT BOARD LAYOUT

Chapter 5 PCB Fabrication 5.1 Procedure 1. Layout your PCB using Eagle. 2. Print out your layout on paper. Ask someone to look over your layout. 3. Print the layout to a transparency. Run the transparency through the laser twice to produce better ink transfer. 4. Cut the transparency with a paper cutter. 5. Cut a PCB Board. Smooth out the rouge edge with a Dremel. 6. Clean the PCB with a Scotch pad. 7. Use Acetone to remove any oil or grease on the board. 8. Tape the transparency to a cleaned PCB Board. 9. Use either a hobby iron or a laminator to transfer the ink onto the PCB. 10. While the PCB is still warm, apply pressure to the PCB with a pair of C-clamps. Come back in 10 minutes. 11. Drill a couple of holes to make sure the top metal layer is lined up with the bottom metal layer. 12. Peel the transparency off the PCB carefully. 13. Fix incomplete ink transfer with a Sharpie. 15

16 CHAPTER 5. PCB FABRICATION 14. Submerge the PCB in Ferric Chloride acid. Please wear gloves and the protective eye glasses. You must work with a partner while you are in the etching facility. 15. Secure the lid and use a swirling motion to agitate the solution for 15 minutes to 30 minutes until the unwated copper is removed. You must agitate the solution constantly. 16. After the excess copper is removed, pour water over the board to halt the etching process. 17. Dispose the left over chemical properly. 18. Drill holes on the PCB. 19. Solder components onto the PCB. 20. Test the functionaly of your four-bit adder. 21. Demosntrate the functionally of your adder. 5.2 Submission Checklist 1. Electronic submission of schematic and board layout. 2. Submit a print out of schematic and layout. Please print the top metal layer and bottom metal layer on separate pages. 3. Demo the PCB. Partial credits will be given for non-functional circuits.

Chapter 6 D Latch 6.1 Verilog Simulation 6.1.1 Random Number Generator 1. Run b_ran_bits.m to generate a random vector of binary numbers. Please modify the path of bit_str.txt. 2. Answer the following questions about b_ran_bits.m. (a) What is the purpose of rand()? (b) What is the purpose of round()? (c) What is the dimension (size) of r? 6.1.2 Using Random Numbers in Verilog Simulation 1. Download and compile t_vector.v. 2. Verify the functionality of t_vector. by running the functional simulation. Please use a 100 MHz clock to drive dck. 3. Please answer the following questions about t_vector.v. (a) What stores the binary numbers loaded from bit_str.txt? (b) Is there a delay between the rising edge of dclk and dout? 17

18 CHAPTER 6. D LATCH 6.1.3 Generate a Verilog Model of a D Latch (a) Use Verilog to model the behavior of a D latch. model should have the following terminals: The Verilog i. q: output, type reg. Why should q be declared as a reg as opposed to a wire? ii. d: input, type wire. iii. enable: input, type wire. 6.1.4 Generate a test bench for D Latch (a) Use the lecture notes as a guide. d_latch_tb.v. Write the Verilog code for 6.2 NAND based D Latch 1. Use the lecture notes as a guide, build a D latch using only NAND gates and an inverter. 2. Set En = 1. What is Q for D = 1? What is Q for D = 0? 3. Begin by setting En = 1 and D = 1. Next, set En = 0. Change D from a logic 1 to 0, does Q change with D? 6.3 Submission Checklist 1. Printout of t_vector.v, d_latch_tb, and d_latch (10 points). 2. Waveform of t_vector.v and d_latch_tb.v (10 points). 3. Questions embedded in the instructions (10 points).

Chapter 7 Test a D-Latch with a Pseudo Random Sequence 7.1 Random Number Generator 1. Learn to generate a pseudo random sequence in hardware using the following link: http://en.wikipedia.org/wiki/linear_feedback_shift_register 2. Assume that a pseudo random number generator is built with a 4 bit shift register and an XOR gate. If the content of the shift register is updated at the rising edge of a clock, how many clock cycles does it take for the binary numbers to repeat? 3. Please use 74LS194 as the shift register and 74LS86 as the XOR to build a 4-bit random number generator. (a) Set S0 to VCC. (b) Set S1 to GND. (c) Use pin number 2 as the shift right input. (Apply the output of the XOR gate to pin number 2) (d) Set the clear terminal to VDD. (e) Connect pin number 16 to VCC and pin number 8 to GND. (f) Use pin number 11 as the clock. Read the following section on instruction for using the mixed signal generator as the function generator. 19

20CHAPTER 7. TEST A D-LATCH WITH A PSEUDO RANDOM SEQUENCE 7.2 Mixed Signal Generator 1. Use the Wave Gen from the mixed signal generator. (a) Press default setup. (b) Press Auto Scale. (c) Set Waveform to square. (d) Set Frequency to 1 KHz. (e) Set Amplitude to 5.00 Vpp. (f) Set Offset to 2.5 V. (g) Set Duty Cycle to 50 percent. 2. Press Trigger (a) Set trigger type to Edge. (b) Set the source to the output of the latch. (c) Set the rising edge. 3. Press Mode/Coupling. (a) Set Mode to normal. (b) Adjust the Holdoff until the waveforms are triggered properly. 7.3 Test the D-Latch with a pseudo random sequence 1. Now that you are able to generate a pseudo random sequence with a linear shift register. Drive the input of D-Latch with the data pattern from the random number generator. You may use the same clock to drive the D-latch. 7.4 Submission Checklist 1. Display the data, clock and the output of the D-latch on the scope. Save the screenshot as a *.bmp file. Submit it a print-out of the screen shot. (10 points) 2. Make comments about the waveforms you have captured. Does your circuit behave correctly as a D-Latch? (2 points)

Chapter 8 Clocked Sequential Circuit 8.1 Building a Verilog Model 1. Using fig5p16.v and fig5p16_tb.v as a starting point, modify the verilog files in order to model the operation of the sequential circuit in Figure 8.1. Figure 8.1: The State Diagram of a Sequential Circuit. 21

22 CHAPTER 8. CLOCKED SEQUENTIAL CIRCUIT 8.2 Hardware Implementation 1. We have shown in the lecture notes that the state diagram in Figure 8.1 can be converted into the schematic in Figure 8.2. Figure 8.2: The State Diagram of the Sequential Circuit in Figure 8.1 2. Please build the circuit shown in Figure 8.2. To generate the input (x), you will need to build the same random number generator you built last week. You will need generate the clock signal from the mixed signal scope and use it to drive both the random number generator and the flip-flops. Please use the datasheets available from google doc. (a) Use 74LS175N as the D flip-flop. supplied to terminal 1? (b) Use 74LS32N as the OR gate. (c) Use 74LS08 as the AND gate. What shold be the voltage 8.3 Submission Checklist 1. Submit a print out of state, next state, x, y, and clock used in verilog simulation. (10 points)

8.3. SUBMISSION CHECKLIST 23 2. Display A, B, clock, x and y on the mixed signal scope, save the waveform as a graphic file, and submit a print out of the waveform. (10 points)

24 CHAPTER 8. CLOCKED SEQUENTIAL CIRCUIT

Chapter 9 Universal Shift Register 9.1 Model the Universal Shift Register in Verilog Model 1. We are going to model the universal shift register shown in Figure 9.1. The universal shift register has four distincts mode of operations shown in Figure 9.2. Figure 9.1: Construction of a Universal Shift Register. 2. Use the lecture notes as a guide and build the verilog models associated with the universal shift register. The shift register can be modeled both behaviorally and strcturally. You will do both in this experiment. 25

26 CHAPTER 9. UNIVERSAL SHIFT REGISTER Figure 9.2: Mode Control of the shift register. (a) Start by generating the random numbers you need for this exercise. Save the random numbers using the file names used in shift_register_4_beh_tb.v and shift_register_4_str_tb.v. You can use b_ran_bits.m to generate the random numbers. (b) Insert additional statements in shift_register_4_str.v and shift_register_4_beh.v in order to make the verilog models functional. (c) Run the test bench associated with each verilog model and confirm that the shfit register will work correctly in each mode. Please take a look at the lecture notes to study the output waveforms of the shift register. 9.2 Hardware Implementation 1. You will learn to built a shift-right register using only D flip-flops and 4-to-1 MUXs shown in Figure 9.1. (a) Use MC74HC175N as the D flip-flop. (b) Use 74LS153 as the 4-to-1 MUX. i. Read the spec sheet carefully and determine the voltage that must be supplied to terminal 15. Also read the data sheet carefully so as to set the MUX to read binary numbers from C 1. 2. You can generate the random number using the random number circuit you built last week. Question: How should the binary numbers be supplied to the universal shift register?

9.3. SUBMISSION CHECKLIST 27 9.3 Submission Checklist 1. Hardcopy of shift_register_4_str.v and shift_register_4_beh.v, as well as the waveform generated with each test bench. (10 points) 2. Demonstrate the shift-right property of the shift register on the mixed signal oscilloscope. Save and printout the wafeform displayed on the mixed signal scope. You may consult the lecture notes for reference. (10 points)

28 CHAPTER 9. UNIVERSAL SHIFT REGISTER

Chapter 10 Synchronous Counter 10.1 Datasheet 1. You will learn to operate DM74LS193 as an up counter in this experiment. Please download the datasheet from the google drive for this experiment. 2. According to the datasheet, the direction of counting is determined by which count input is pulsed while the other count input is held HIGH. (a) We will build a synchronous counter that counts up from 0000. (b) Using the connection diagram on page 1 of the datasheet as a reference, what should be connected to pin #4? What should be connected to pin #5? Please assume that a clock of 1 KHz with a low of 0V and a high of 5 V is available for pulsing an input. 3. According to the Recommended Operating Conditions section of the datasheet, what value should be used for V CC? 4. What bias voltage should provided for pin #8? 5. According to the datasheet, this counter was designed to be cascaded without the need for external circuitry. What outputs are used for this purpose? Are they needed in this experiment? 6. What is the purpose of the clear input? Should it be set to a high level or a low level? According to the timing diagram on page 3 of the datasheet, how are Q A, Q B, Q C and Q D affected by the clear input? 29

30 CHAPTER 10. SYNCHRONOUS COUNTER Figure 10.1: Partial Logic Diagram 7. You will use the paritial Logic Diagram in Figure 10.1 to answer the following question. (a) What is w1 if CLEAR=1? What is w1 if CLEAR=0 and LOAD=1? (b) What is the output of gate X in Figure 10.1 if LOAD=1? (c) What is w2 if CLEAR =0? (d) Replace the circuitry in the red retangle in Figure 10.1 by applying the DeMorgan s theorem. What is the signal provided to the reset terminal of the T flip-flop when LOAD=1 and CLEAR=0? 10.2 Hardware Implementation 1. Build a frequency divider with DM74LS193. Observe the outputs at Q A, Q B, Q C, and Q D. Does the circuit behave as a frequency divider? 10.3 Submission Checklist 1. A screen shot of the divider outputs. (10 points) 2. Please answers all the questions in this lab. (20 points)

Chapter 11 Random Access Memory 11.1 Schematic 1. We will build a simple memory circuit with DM8599. Please download the spec sheet from the Google drive before you proceed. 2. DM8599 is a random access memory capable of storing 64 bits. Please answer the following questions with the help of the datasheet. (a) How many words does it store? (b) What is the length of each word? (e.g. how many bits are in each word?) (c) How many bits are used as address bits? What are the pin numbers of the address bits? (d) How many bits are used as data inputs? What are the pin numbers of the input bits? (e) How many bits are the output bits (sense outputs in the datasheet)? What are the pin numbers of the outputs? (f) Which terminal is used for memory enable (ME)? (g) What terminal is used for write enable (WE)? (h) According to the datasheet, information will be read as the complement of what was written into the memory. If you put in a 1 to the memory, what do you get at the output? 31

32 CHAPTER 11. RANDOM ACCESS MEMORY 11.2 Experiment Figure 11.1: Schematic of a RAM. 1. You will build the memory circuit shown in Figure 11.1 on a breadboard. You may use the sliding switches on the protoboard to generate

11.3. SUBMISSION CHECKLIST 33 binary inputs of the memory. 2. Please write 1111 to the location specified by 1010 address bits. 3. Please write 0110 to the location specified by 1011 address bits. (Question: how is the Hold operation useful?) 4. Please read the outputs from the location specified by 1010. Are you getting the outputs you expected? 5. Please read the outputs from the location specified by 1011. Are you getting the outputs you expected? 11.3 Submission Checklist 1. Please answer questions in this experiment. (20 points) 2. Create a video demo of your memory circuit and upload demo to the google drive. (10 points)